arch/arm/include/asm/armv7m.h

   1 /*
   2  * (C) Copyright 2010,2011
   3  * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
   4  *
   5  * (C) Copyright 2015
   6  * Kamil Lulko, <kamil.lulko@gmail.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef ARMV7M_H
  12 #define ARMV7M_H
  13
  14 #if defined(__ASSEMBLY__)
  15 .syntax unified
  16 .thumb
  17 #endif
  18
  19 /* armv7m fixed base addresses */
  20 #define V7M_SCS_BASE            0xE000E000
  21 #define V7M_NVIC_BASE           (V7M_SCS_BASE + 0x0100)
  22 #define V7M_SCB_BASE            (V7M_SCS_BASE + 0x0D00)
  23 #define V7M_PROC_FTR_BASE       (V7M_SCS_BASE + 0x0D78)
  24 #define V7M_MPU_BASE            (V7M_SCS_BASE + 0x0D90)
  25 #define V7M_FPU_BASE            (V7M_SCS_BASE + 0x0F30)
  26 #define V7M_CACHE_MAINT_BASE    (V7M_SCS_BASE + 0x0F50)
  27 #define V7M_ACCESS_CNTL_BASE    (V7M_SCS_BASE + 0x0F90)
  28
  29 #define V7M_SCB_VTOR            0x08
  30
  31 #if !defined(__ASSEMBLY__)
  32 struct v7m_scb {
  33         uint32_t cpuid;         /* CPUID Base Register */
  34         uint32_t icsr;          /* Interrupt Control and State Register */
  35         uint32_t vtor;          /* Vector Table Offset Register */
  36         uint32_t aircr;         /* App Interrupt and Reset Control Register */
  37         uint32_t scr;           /* offset 0x10: System Control Register */
  38         uint32_t ccr;           /* offset 0x14: Config and Control Register */
  39         uint32_t shpr1;         /* offset 0x18: System Handler Priority Reg 1 */
  40         uint32_t shpr2;         /* offset 0x1c: System Handler Priority Reg 2 */
  41         uint32_t shpr3;         /* offset 0x20: System Handler Priority Reg 3 */
  42         uint32_t shcrs;         /* offset 0x24: System Handler Control State */
  43         uint32_t cfsr;          /* offset 0x28: Configurable Fault Status Reg */
  44         uint32_t hfsr;          /* offset 0x2C: HardFault Status Register */
  45         uint32_t res;           /* offset 0x30: reserved */
  46         uint32_t mmar;          /* offset 0x34: MemManage Fault Address Reg */
  47         uint32_t bfar;          /* offset 0x38: BusFault Address Reg */
  48         uint32_t afsr;          /* offset 0x3C: Auxiliary Fault Status Reg */
  49 };
  50 #define V7M_SCB                         ((struct v7m_scb *)V7M_SCB_BASE)
  51
  52 #define V7M_AIRCR_VECTKEY               0x5fa
  53 #define V7M_AIRCR_VECTKEY_SHIFT         16
  54 #define V7M_AIRCR_ENDIAN                (1 << 15)
  55 #define V7M_AIRCR_PRIGROUP_SHIFT        8
  56 #define V7M_AIRCR_PRIGROUP_MSK          (0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
  57 #define V7M_AIRCR_SYSRESET              (1 << 2)
  58
  59 #define V7M_ICSR_VECTACT_MSK            0xFF
  60
  61 #define V7M_CCR_DCACHE                  16
  62 #define V7M_CCR_ICACHE                  17
  63
  64 struct v7m_mpu {
  65         uint32_t type;          /* Type Register */
  66         uint32_t ctrl;          /* Control Register */
  67         uint32_t rnr;           /* Region Number Register */
  68         uint32_t rbar;          /* Region Base Address Register */
  69         uint32_t rasr;          /* Region Attribute and Size Register */
  70 };
  71 #define V7M_MPU                         ((struct v7m_mpu *)V7M_MPU_BASE)
  72
  73 #endif /* !defined(__ASSEMBLY__) */
  74 #endif /* ARMV7M_H */