arch/arm/include/asm/gic.h

   1 #ifndef __GIC_H__
   2 #define __GIC_H__
   3
   4 /* Register offsets for the ARM generic interrupt controller (GIC) */
   5
   6 #define GIC_DIST_OFFSET         0x1000
   7 #define GIC_CPU_OFFSET_A9       0x0100
   8 #define GIC_CPU_OFFSET_A15      0x2000
   9
  10 /* Distributor Registers */
  11 #define GICD_CTLR               0x0000
  12 #define GICD_TYPER              0x0004
  13 #define GICD_IIDR               0x0008
  14 #define GICD_STATUSR            0x0010
  15 #define GICD_SETSPI_NSR         0x0040
  16 #define GICD_CLRSPI_NSR         0x0048
  17 #define GICD_SETSPI_SR          0x0050
  18 #define GICD_CLRSPI_SR          0x0058
  19 #define GICD_SEIR               0x0068
  20 #define GICD_IGROUPRn           0x0080
  21 #define GICD_ISENABLERn         0x0100
  22 #define GICD_ICENABLERn         0x0180
  23 #define GICD_ISPENDRn           0x0200
  24 #define GICD_ICPENDRn           0x0280
  25 #define GICD_ISACTIVERn         0x0300
  26 #define GICD_ICACTIVERn         0x0380
  27 #define GICD_IPRIORITYRn        0x0400
  28 #define GICD_ITARGETSRn         0x0800
  29 #define GICD_ICFGR              0x0c00
  30 #define GICD_IGROUPMODRn        0x0d00
  31 #define GICD_NSACRn             0x0e00
  32 #define GICD_SGIR               0x0f00
  33 #define GICD_CPENDSGIRn         0x0f10
  34 #define GICD_SPENDSGIRn         0x0f20
  35 #define GICD_IROUTERn           0x6000
  36
  37 /* Cpu Interface Memory Mapped Registers */
  38 #define GICC_CTLR               0x0000
  39 #define GICC_PMR                0x0004
  40 #define GICC_BPR                0x0008
  41 #define GICC_IAR                0x000C
  42 #define GICC_EOIR               0x0010
  43 #define GICC_RPR                0x0014
  44 #define GICC_HPPIR              0x0018
  45 #define GICC_ABPR               0x001c
  46 #define GICC_AIAR               0x0020
  47 #define GICC_AEOIR              0x0024
  48 #define GICC_AHPPIR             0x0028
  49 #define GICC_APRn               0x00d0
  50 #define GICC_NSAPRn             0x00e0
  51 #define GICC_IIDR               0x00fc
  52 #define GICC_DIR                0x1000
  53
  54 /* ReDistributor Registers for Control and Physical LPIs */
  55 #define GICR_CTLR               0x0000
  56 #define GICR_IIDR               0x0004
  57 #define GICR_TYPER              0x0008
  58 #define GICR_STATUSR            0x0010
  59 #define GICR_WAKER              0x0014
  60 #define GICR_SETLPIR            0x0040
  61 #define GICR_CLRLPIR            0x0048
  62 #define GICR_SEIR               0x0068
  63 #define GICR_PROPBASER          0x0070
  64 #define GICR_PENDBASER          0x0078
  65 #define GICR_INVLPIR            0x00a0
  66 #define GICR_INVALLR            0x00b0
  67 #define GICR_SYNCR              0x00c0
  68 #define GICR_MOVLPIR            0x0100
  69 #define GICR_MOVALLR            0x0110
  70
  71 /* ReDistributor Registers for SGIs and PPIs */
  72 #define GICR_IGROUPRn           0x0080
  73 #define GICR_ISENABLERn         0x0100
  74 #define GICR_ICENABLERn         0x0180
  75 #define GICR_ISPENDRn           0x0200
  76 #define GICR_ICPENDRn           0x0280
  77 #define GICR_ISACTIVERn         0x0300
  78 #define GICR_ICACTIVERn         0x0380
  79 #define GICR_IPRIORITYRn        0x0400
  80 #define GICR_ICFGR0             0x0c00
  81 #define GICR_ICFGR1             0x0c04
  82 #define GICR_IGROUPMODRn        0x0d00
  83 #define GICR_NSACRn             0x0e00
  84
  85 /* Cpu Interface System Registers */
  86 #define ICC_IAR0_EL1            S3_0_C12_C8_0
  87 #define ICC_IAR1_EL1            S3_0_C12_C12_0
  88 #define ICC_EOIR0_EL1           S3_0_C12_C8_1
  89 #define ICC_EOIR1_EL1           S3_0_C12_C12_1
  90 #define ICC_HPPIR0_EL1          S3_0_C12_C8_2
  91 #define ICC_HPPIR1_EL1          S3_0_C12_C12_2
  92 #define ICC_BPR0_EL1            S3_0_C12_C8_3
  93 #define ICC_BPR1_EL1            S3_0_C12_C12_3
  94 #define ICC_DIR_EL1             S3_0_C12_C11_1
  95 #define ICC_PMR_EL1             S3_0_C4_C6_0
  96 #define ICC_RPR_EL1             S3_0_C12_C11_3
  97 #define ICC_CTLR_EL1            S3_0_C12_C12_4
  98 #define ICC_CTLR_EL3            S3_6_C12_C12_4
  99 #define ICC_SRE_EL1             S3_0_C12_C12_5
 100 #define ICC_SRE_EL2             S3_4_C12_C9_5
 101 #define ICC_SRE_EL3             S3_6_C12_C12_5
 102 #define ICC_IGRPEN0_EL1         S3_0_C12_C12_6
 103 #define ICC_IGRPEN1_EL1         S3_0_C12_C12_7
 104 #define ICC_IGRPEN1_EL3         S3_6_C12_C12_7
 105 #define ICC_SEIEN_EL1           S3_0_C12_C13_0
 106 #define ICC_SGI0R_EL1           S3_0_C12_C11_7
 107 #define ICC_SGI1R_EL1           S3_0_C12_C11_5
 108 #define ICC_ASGI1R_EL1          S3_0_C12_C11_6
 109
 110 #endif /* __GIC_H__ */