]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/include/asm/imx-common/regs-apbh.h
bcec6e0b95aaeb92bda39bf1b55eb38615b118e9
2 * Freescale i.MX28 APBH Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #ifndef __REGS_APBH_H__
27 #define __REGS_APBH_H__
29 #include <asm/imx-common/regs-common.h>
33 #if defined(CONFIG_MX23)
34 struct mxs_apbh_regs
{
35 mxs_reg_32(hw_apbh_ctrl0
)
36 mxs_reg_32(hw_apbh_ctrl1
)
37 mxs_reg_32(hw_apbh_ctrl2
)
38 mxs_reg_32(hw_apbh_channel_ctrl
)
42 mxs_reg_32(hw_apbh_ch_curcmdar
)
43 mxs_reg_32(hw_apbh_ch_nxtcmdar
)
44 mxs_reg_32(hw_apbh_ch_cmd
)
45 mxs_reg_32(hw_apbh_ch_bar
)
46 mxs_reg_32(hw_apbh_ch_sema
)
47 mxs_reg_32(hw_apbh_ch_debug1
)
48 mxs_reg_32(hw_apbh_ch_debug2
)
51 mxs_reg_32(hw_apbh_ch0_curcmdar
)
52 mxs_reg_32(hw_apbh_ch0_nxtcmdar
)
53 mxs_reg_32(hw_apbh_ch0_cmd
)
54 mxs_reg_32(hw_apbh_ch0_bar
)
55 mxs_reg_32(hw_apbh_ch0_sema
)
56 mxs_reg_32(hw_apbh_ch0_debug1
)
57 mxs_reg_32(hw_apbh_ch0_debug2
)
58 mxs_reg_32(hw_apbh_ch1_curcmdar
)
59 mxs_reg_32(hw_apbh_ch1_nxtcmdar
)
60 mxs_reg_32(hw_apbh_ch1_cmd
)
61 mxs_reg_32(hw_apbh_ch1_bar
)
62 mxs_reg_32(hw_apbh_ch1_sema
)
63 mxs_reg_32(hw_apbh_ch1_debug1
)
64 mxs_reg_32(hw_apbh_ch1_debug2
)
65 mxs_reg_32(hw_apbh_ch2_curcmdar
)
66 mxs_reg_32(hw_apbh_ch2_nxtcmdar
)
67 mxs_reg_32(hw_apbh_ch2_cmd
)
68 mxs_reg_32(hw_apbh_ch2_bar
)
69 mxs_reg_32(hw_apbh_ch2_sema
)
70 mxs_reg_32(hw_apbh_ch2_debug1
)
71 mxs_reg_32(hw_apbh_ch2_debug2
)
72 mxs_reg_32(hw_apbh_ch3_curcmdar
)
73 mxs_reg_32(hw_apbh_ch3_nxtcmdar
)
74 mxs_reg_32(hw_apbh_ch3_cmd
)
75 mxs_reg_32(hw_apbh_ch3_bar
)
76 mxs_reg_32(hw_apbh_ch3_sema
)
77 mxs_reg_32(hw_apbh_ch3_debug1
)
78 mxs_reg_32(hw_apbh_ch3_debug2
)
79 mxs_reg_32(hw_apbh_ch4_curcmdar
)
80 mxs_reg_32(hw_apbh_ch4_nxtcmdar
)
81 mxs_reg_32(hw_apbh_ch4_cmd
)
82 mxs_reg_32(hw_apbh_ch4_bar
)
83 mxs_reg_32(hw_apbh_ch4_sema
)
84 mxs_reg_32(hw_apbh_ch4_debug1
)
85 mxs_reg_32(hw_apbh_ch4_debug2
)
86 mxs_reg_32(hw_apbh_ch5_curcmdar
)
87 mxs_reg_32(hw_apbh_ch5_nxtcmdar
)
88 mxs_reg_32(hw_apbh_ch5_cmd
)
89 mxs_reg_32(hw_apbh_ch5_bar
)
90 mxs_reg_32(hw_apbh_ch5_sema
)
91 mxs_reg_32(hw_apbh_ch5_debug1
)
92 mxs_reg_32(hw_apbh_ch5_debug2
)
93 mxs_reg_32(hw_apbh_ch6_curcmdar
)
94 mxs_reg_32(hw_apbh_ch6_nxtcmdar
)
95 mxs_reg_32(hw_apbh_ch6_cmd
)
96 mxs_reg_32(hw_apbh_ch6_bar
)
97 mxs_reg_32(hw_apbh_ch6_sema
)
98 mxs_reg_32(hw_apbh_ch6_debug1
)
99 mxs_reg_32(hw_apbh_ch6_debug2
)
100 mxs_reg_32(hw_apbh_ch7_curcmdar
)
101 mxs_reg_32(hw_apbh_ch7_nxtcmdar
)
102 mxs_reg_32(hw_apbh_ch7_cmd
)
103 mxs_reg_32(hw_apbh_ch7_bar
)
104 mxs_reg_32(hw_apbh_ch7_sema
)
105 mxs_reg_32(hw_apbh_ch7_debug1
)
106 mxs_reg_32(hw_apbh_ch7_debug2
)
109 mxs_reg_32(hw_apbh_version
)
112 #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
113 struct mxs_apbh_regs
{
114 mxs_reg_32(hw_apbh_ctrl0
)
115 mxs_reg_32(hw_apbh_ctrl1
)
116 mxs_reg_32(hw_apbh_ctrl2
)
117 mxs_reg_32(hw_apbh_channel_ctrl
)
118 mxs_reg_32(hw_apbh_devsel
)
119 mxs_reg_32(hw_apbh_dma_burst_size
)
120 mxs_reg_32(hw_apbh_debug
)
122 uint32_t reserved
[36];
126 mxs_reg_32(hw_apbh_ch_curcmdar
)
127 mxs_reg_32(hw_apbh_ch_nxtcmdar
)
128 mxs_reg_32(hw_apbh_ch_cmd
)
129 mxs_reg_32(hw_apbh_ch_bar
)
130 mxs_reg_32(hw_apbh_ch_sema
)
131 mxs_reg_32(hw_apbh_ch_debug1
)
132 mxs_reg_32(hw_apbh_ch_debug2
)
135 mxs_reg_32(hw_apbh_ch0_curcmdar
)
136 mxs_reg_32(hw_apbh_ch0_nxtcmdar
)
137 mxs_reg_32(hw_apbh_ch0_cmd
)
138 mxs_reg_32(hw_apbh_ch0_bar
)
139 mxs_reg_32(hw_apbh_ch0_sema
)
140 mxs_reg_32(hw_apbh_ch0_debug1
)
141 mxs_reg_32(hw_apbh_ch0_debug2
)
142 mxs_reg_32(hw_apbh_ch1_curcmdar
)
143 mxs_reg_32(hw_apbh_ch1_nxtcmdar
)
144 mxs_reg_32(hw_apbh_ch1_cmd
)
145 mxs_reg_32(hw_apbh_ch1_bar
)
146 mxs_reg_32(hw_apbh_ch1_sema
)
147 mxs_reg_32(hw_apbh_ch1_debug1
)
148 mxs_reg_32(hw_apbh_ch1_debug2
)
149 mxs_reg_32(hw_apbh_ch2_curcmdar
)
150 mxs_reg_32(hw_apbh_ch2_nxtcmdar
)
151 mxs_reg_32(hw_apbh_ch2_cmd
)
152 mxs_reg_32(hw_apbh_ch2_bar
)
153 mxs_reg_32(hw_apbh_ch2_sema
)
154 mxs_reg_32(hw_apbh_ch2_debug1
)
155 mxs_reg_32(hw_apbh_ch2_debug2
)
156 mxs_reg_32(hw_apbh_ch3_curcmdar
)
157 mxs_reg_32(hw_apbh_ch3_nxtcmdar
)
158 mxs_reg_32(hw_apbh_ch3_cmd
)
159 mxs_reg_32(hw_apbh_ch3_bar
)
160 mxs_reg_32(hw_apbh_ch3_sema
)
161 mxs_reg_32(hw_apbh_ch3_debug1
)
162 mxs_reg_32(hw_apbh_ch3_debug2
)
163 mxs_reg_32(hw_apbh_ch4_curcmdar
)
164 mxs_reg_32(hw_apbh_ch4_nxtcmdar
)
165 mxs_reg_32(hw_apbh_ch4_cmd
)
166 mxs_reg_32(hw_apbh_ch4_bar
)
167 mxs_reg_32(hw_apbh_ch4_sema
)
168 mxs_reg_32(hw_apbh_ch4_debug1
)
169 mxs_reg_32(hw_apbh_ch4_debug2
)
170 mxs_reg_32(hw_apbh_ch5_curcmdar
)
171 mxs_reg_32(hw_apbh_ch5_nxtcmdar
)
172 mxs_reg_32(hw_apbh_ch5_cmd
)
173 mxs_reg_32(hw_apbh_ch5_bar
)
174 mxs_reg_32(hw_apbh_ch5_sema
)
175 mxs_reg_32(hw_apbh_ch5_debug1
)
176 mxs_reg_32(hw_apbh_ch5_debug2
)
177 mxs_reg_32(hw_apbh_ch6_curcmdar
)
178 mxs_reg_32(hw_apbh_ch6_nxtcmdar
)
179 mxs_reg_32(hw_apbh_ch6_cmd
)
180 mxs_reg_32(hw_apbh_ch6_bar
)
181 mxs_reg_32(hw_apbh_ch6_sema
)
182 mxs_reg_32(hw_apbh_ch6_debug1
)
183 mxs_reg_32(hw_apbh_ch6_debug2
)
184 mxs_reg_32(hw_apbh_ch7_curcmdar
)
185 mxs_reg_32(hw_apbh_ch7_nxtcmdar
)
186 mxs_reg_32(hw_apbh_ch7_cmd
)
187 mxs_reg_32(hw_apbh_ch7_bar
)
188 mxs_reg_32(hw_apbh_ch7_sema
)
189 mxs_reg_32(hw_apbh_ch7_debug1
)
190 mxs_reg_32(hw_apbh_ch7_debug2
)
191 mxs_reg_32(hw_apbh_ch8_curcmdar
)
192 mxs_reg_32(hw_apbh_ch8_nxtcmdar
)
193 mxs_reg_32(hw_apbh_ch8_cmd
)
194 mxs_reg_32(hw_apbh_ch8_bar
)
195 mxs_reg_32(hw_apbh_ch8_sema
)
196 mxs_reg_32(hw_apbh_ch8_debug1
)
197 mxs_reg_32(hw_apbh_ch8_debug2
)
198 mxs_reg_32(hw_apbh_ch9_curcmdar
)
199 mxs_reg_32(hw_apbh_ch9_nxtcmdar
)
200 mxs_reg_32(hw_apbh_ch9_cmd
)
201 mxs_reg_32(hw_apbh_ch9_bar
)
202 mxs_reg_32(hw_apbh_ch9_sema
)
203 mxs_reg_32(hw_apbh_ch9_debug1
)
204 mxs_reg_32(hw_apbh_ch9_debug2
)
205 mxs_reg_32(hw_apbh_ch10_curcmdar
)
206 mxs_reg_32(hw_apbh_ch10_nxtcmdar
)
207 mxs_reg_32(hw_apbh_ch10_cmd
)
208 mxs_reg_32(hw_apbh_ch10_bar
)
209 mxs_reg_32(hw_apbh_ch10_sema
)
210 mxs_reg_32(hw_apbh_ch10_debug1
)
211 mxs_reg_32(hw_apbh_ch10_debug2
)
212 mxs_reg_32(hw_apbh_ch11_curcmdar
)
213 mxs_reg_32(hw_apbh_ch11_nxtcmdar
)
214 mxs_reg_32(hw_apbh_ch11_cmd
)
215 mxs_reg_32(hw_apbh_ch11_bar
)
216 mxs_reg_32(hw_apbh_ch11_sema
)
217 mxs_reg_32(hw_apbh_ch11_debug1
)
218 mxs_reg_32(hw_apbh_ch11_debug2
)
219 mxs_reg_32(hw_apbh_ch12_curcmdar
)
220 mxs_reg_32(hw_apbh_ch12_nxtcmdar
)
221 mxs_reg_32(hw_apbh_ch12_cmd
)
222 mxs_reg_32(hw_apbh_ch12_bar
)
223 mxs_reg_32(hw_apbh_ch12_sema
)
224 mxs_reg_32(hw_apbh_ch12_debug1
)
225 mxs_reg_32(hw_apbh_ch12_debug2
)
226 mxs_reg_32(hw_apbh_ch13_curcmdar
)
227 mxs_reg_32(hw_apbh_ch13_nxtcmdar
)
228 mxs_reg_32(hw_apbh_ch13_cmd
)
229 mxs_reg_32(hw_apbh_ch13_bar
)
230 mxs_reg_32(hw_apbh_ch13_sema
)
231 mxs_reg_32(hw_apbh_ch13_debug1
)
232 mxs_reg_32(hw_apbh_ch13_debug2
)
233 mxs_reg_32(hw_apbh_ch14_curcmdar
)
234 mxs_reg_32(hw_apbh_ch14_nxtcmdar
)
235 mxs_reg_32(hw_apbh_ch14_cmd
)
236 mxs_reg_32(hw_apbh_ch14_bar
)
237 mxs_reg_32(hw_apbh_ch14_sema
)
238 mxs_reg_32(hw_apbh_ch14_debug1
)
239 mxs_reg_32(hw_apbh_ch14_debug2
)
240 mxs_reg_32(hw_apbh_ch15_curcmdar
)
241 mxs_reg_32(hw_apbh_ch15_nxtcmdar
)
242 mxs_reg_32(hw_apbh_ch15_cmd
)
243 mxs_reg_32(hw_apbh_ch15_bar
)
244 mxs_reg_32(hw_apbh_ch15_sema
)
245 mxs_reg_32(hw_apbh_ch15_debug1
)
246 mxs_reg_32(hw_apbh_ch15_debug2
)
249 mxs_reg_32(hw_apbh_version
)
255 #define APBH_CTRL0_SFTRST (1 << 31)
256 #define APBH_CTRL0_CLKGATE (1 << 30)
257 #define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
258 #define APBH_CTRL0_APB_BURST_EN (1 << 28)
259 #if defined(CONFIG_MX23)
260 #define APBH_CTRL0_RSVD0_MASK (0xf << 24)
261 #define APBH_CTRL0_RSVD0_OFFSET 24
262 #define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
263 #define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
264 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
265 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
266 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
267 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
268 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
269 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
270 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
271 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
272 #elif defined(CONFIG_MX28)
273 #define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
274 #define APBH_CTRL0_RSVD0_OFFSET 16
275 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
276 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
277 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
278 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
279 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
280 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
281 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
282 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
283 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
284 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
285 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
286 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
287 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
288 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
289 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
290 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
291 #elif defined(CONFIG_MX6)
292 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
293 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
294 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
295 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
296 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
297 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
298 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
299 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
300 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
301 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
304 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
305 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
306 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
307 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
308 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
309 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
310 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
311 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
312 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
313 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
314 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
315 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
316 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
317 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
318 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
319 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
320 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
321 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
322 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
323 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
324 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
325 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
326 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
327 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
328 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
329 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
330 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
331 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
332 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
333 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
334 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
335 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
336 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
337 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
339 #define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
340 #define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
341 #define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
342 #define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
343 #define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
344 #define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
345 #define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
346 #define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
347 #define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
348 #define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
349 #define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
350 #define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
351 #define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
352 #define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
353 #define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
354 #define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
355 #define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
356 #define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
357 #define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
358 #define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
359 #define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
360 #define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
361 #define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
362 #define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
363 #define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
364 #define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
365 #define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
366 #define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
367 #define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
368 #define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
369 #define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
370 #define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
372 #if defined(CONFIG_MX28)
373 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
374 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
375 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
376 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
377 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
378 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
379 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
380 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
381 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
382 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
383 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
384 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
385 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
386 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
387 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
388 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
389 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
390 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
391 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
392 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
393 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
394 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
395 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
396 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
397 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
398 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
399 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
400 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
401 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
402 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
403 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
404 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
407 #if defined(CONFIG_MX6)
408 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
411 #if defined(CONFIG_MX23)
412 #define APBH_DEVSEL_CH7_MASK (0xf << 28)
413 #define APBH_DEVSEL_CH7_OFFSET 28
414 #define APBH_DEVSEL_CH6_MASK (0xf << 24)
415 #define APBH_DEVSEL_CH6_OFFSET 24
416 #define APBH_DEVSEL_CH5_MASK (0xf << 20)
417 #define APBH_DEVSEL_CH5_OFFSET 20
418 #define APBH_DEVSEL_CH4_MASK (0xf << 16)
419 #define APBH_DEVSEL_CH4_OFFSET 16
420 #define APBH_DEVSEL_CH3_MASK (0xf << 12)
421 #define APBH_DEVSEL_CH3_OFFSET 12
422 #define APBH_DEVSEL_CH2_MASK (0xf << 8)
423 #define APBH_DEVSEL_CH2_OFFSET 8
424 #define APBH_DEVSEL_CH1_MASK (0xf << 4)
425 #define APBH_DEVSEL_CH1_OFFSET 4
426 #define APBH_DEVSEL_CH0_MASK (0xf << 0)
427 #define APBH_DEVSEL_CH0_OFFSET 0
428 #elif defined(CONFIG_MX28)
429 #define APBH_DEVSEL_CH15_MASK (0x3 << 30)
430 #define APBH_DEVSEL_CH15_OFFSET 30
431 #define APBH_DEVSEL_CH14_MASK (0x3 << 28)
432 #define APBH_DEVSEL_CH14_OFFSET 28
433 #define APBH_DEVSEL_CH13_MASK (0x3 << 26)
434 #define APBH_DEVSEL_CH13_OFFSET 26
435 #define APBH_DEVSEL_CH12_MASK (0x3 << 24)
436 #define APBH_DEVSEL_CH12_OFFSET 24
437 #define APBH_DEVSEL_CH11_MASK (0x3 << 22)
438 #define APBH_DEVSEL_CH11_OFFSET 22
439 #define APBH_DEVSEL_CH10_MASK (0x3 << 20)
440 #define APBH_DEVSEL_CH10_OFFSET 20
441 #define APBH_DEVSEL_CH9_MASK (0x3 << 18)
442 #define APBH_DEVSEL_CH9_OFFSET 18
443 #define APBH_DEVSEL_CH8_MASK (0x3 << 16)
444 #define APBH_DEVSEL_CH8_OFFSET 16
445 #define APBH_DEVSEL_CH7_MASK (0x3 << 14)
446 #define APBH_DEVSEL_CH7_OFFSET 14
447 #define APBH_DEVSEL_CH6_MASK (0x3 << 12)
448 #define APBH_DEVSEL_CH6_OFFSET 12
449 #define APBH_DEVSEL_CH5_MASK (0x3 << 10)
450 #define APBH_DEVSEL_CH5_OFFSET 10
451 #define APBH_DEVSEL_CH4_MASK (0x3 << 8)
452 #define APBH_DEVSEL_CH4_OFFSET 8
453 #define APBH_DEVSEL_CH3_MASK (0x3 << 6)
454 #define APBH_DEVSEL_CH3_OFFSET 6
455 #define APBH_DEVSEL_CH2_MASK (0x3 << 4)
456 #define APBH_DEVSEL_CH2_OFFSET 4
457 #define APBH_DEVSEL_CH1_MASK (0x3 << 2)
458 #define APBH_DEVSEL_CH1_OFFSET 2
459 #define APBH_DEVSEL_CH0_MASK (0x3 << 0)
460 #define APBH_DEVSEL_CH0_OFFSET 0
463 #if defined(CONFIG_MX28)
464 #define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
465 #define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
466 #define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
467 #define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
468 #define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
469 #define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
470 #define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
471 #define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
472 #define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
473 #define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
474 #define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
475 #define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
476 #define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
477 #define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
478 #define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
479 #define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
480 #define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
481 #define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
482 #define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
483 #define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
484 #define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
485 #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
486 #define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
487 #define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
488 #define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
489 #define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
490 #define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
491 #define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
492 #define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
493 #define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
494 #define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
495 #define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
497 #define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
498 #define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
499 #define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
500 #define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
501 #define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
502 #define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
503 #define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
504 #define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
505 #define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
506 #define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
508 #define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
509 #define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
510 #define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
511 #define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
512 #define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
514 #define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
517 #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
518 #define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
520 #define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
521 #define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
523 #define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
524 #define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
525 #define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
526 #define APBH_CHn_CMD_CMDWORDS_OFFSET 12
527 #define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
528 #define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
529 #define APBH_CHn_CMD_SEMAPHORE (1 << 6)
530 #define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
531 #define APBH_CHn_CMD_NANDLOCK (1 << 4)
532 #define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
533 #define APBH_CHn_CMD_CHAIN (1 << 2)
534 #define APBH_CHn_CMD_COMMAND_MASK 0x3
535 #define APBH_CHn_CMD_COMMAND_OFFSET 0
536 #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
537 #define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
538 #define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
539 #define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
541 #define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
542 #define APBH_CHn_BAR_ADDRESS_OFFSET 0
544 #define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
545 #define APBH_CHn_SEMA_RSVD2_OFFSET 24
546 #define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
547 #define APBH_CHn_SEMA_PHORE_OFFSET 16
548 #define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
549 #define APBH_CHn_SEMA_RSVD1_OFFSET 8
550 #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
551 #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
553 #define APBH_CHn_DEBUG1_REQ (1 << 31)
554 #define APBH_CHn_DEBUG1_BURST (1 << 30)
555 #define APBH_CHn_DEBUG1_KICK (1 << 29)
556 #define APBH_CHn_DEBUG1_END (1 << 28)
557 #define APBH_CHn_DEBUG1_SENSE (1 << 27)
558 #define APBH_CHn_DEBUG1_READY (1 << 26)
559 #define APBH_CHn_DEBUG1_LOCK (1 << 25)
560 #define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
561 #define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
562 #define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
563 #define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
564 #define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
565 #define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
566 #define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
567 #define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
568 #define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
569 #define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
570 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
571 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
572 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
573 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
574 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
575 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
576 #define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
577 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
578 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
579 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
580 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
581 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
582 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
583 #define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
584 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
585 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
586 #define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
587 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
588 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
590 #define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
591 #define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
592 #define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
593 #define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
595 #define APBH_VERSION_MAJOR_MASK (0xff << 24)
596 #define APBH_VERSION_MAJOR_OFFSET 24
597 #define APBH_VERSION_MINOR_MASK (0xff << 16)
598 #define APBH_VERSION_MINOR_OFFSET 16
599 #define APBH_VERSION_STEP_MASK 0xffff
600 #define APBH_VERSION_STEP_OFFSET 0
602 #endif /* __REGS_APBH_H__ */
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