arch/arm/include/asm/mach-imx/sys_proto.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2009
   4  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   5  */
   6
   7 #ifndef _SYS_PROTO_H_
   8 #define _SYS_PROTO_H_
   9
  10 #include <asm/io.h>
  11 #include <asm/mach-imx/regs-common.h>
  12 #include <asm/mach-imx/module_fuse.h>
  13 #include <linux/bitops.h>
  14 #include "../arch-imx/cpu.h"
  15
  16 struct bd_info;
  17
  18 #define soc_rev() (get_cpu_rev() & 0xFF)
  19 #define is_soc_rev(rev) (soc_rev() == rev)
  20
  21 /* returns MXC_CPU_ value */
  22 #define cpu_type(rev) (((rev) >> 12) & 0x1ff)
  23 #define soc_type(rev) (((rev) >> 12) & 0xf0)
  24 /* both macros return/take MXC_CPU_ constants */
  25 #define get_cpu_type() (cpu_type(get_cpu_rev()))
  26 #define get_soc_type() (soc_type(get_cpu_rev()))
  27 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
  28 #define is_soc_type(soc) (get_soc_type() == soc)
  29
  30 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
  31 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
  32 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
  33 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
  34 #define is_imx9() (is_soc_type(MXC_SOC_IMX9))
  35 #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
  36
  37 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
  38 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
  39 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
  40 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
  41 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
  42 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
  43 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
  44 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
  45 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
  46 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
  47 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
  48
  49 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
  50
  51 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
  52 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
  53 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
  54 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
  55 #define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP))
  56 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
  57         is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
  58         is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
  59 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
  60 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
  61 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
  62 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
  63 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
  64 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
  65         is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
  66         is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
  67         is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
  68 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
  69 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
  70 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
  71 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
  72 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
  73 #define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
  74 #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
  75 #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
  76 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)  || is_cpu_type(MXC_CPU_IMX8MPD) || \
  77         is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
  78 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
  79 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
  80 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
  81 #define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
  82
  83 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
  84
  85 #define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
  86
  87 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
  88 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
  89
  90 #ifdef CONFIG_MX6
  91 #define IMX6_SRC_GPR10_BMODE                    BIT(28)
  92 #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT   BIT(30)
  93
  94 #define IMX6_BMODE_MASK                 GENMASK(7, 0)
  95 #define IMX6_BMODE_SHIFT                4
  96 #define IMX6_BMODE_EIM_MASK             BIT(3)
  97 #define IMX6_BMODE_EIM_SHIFT            3
  98 #define IMX6_BMODE_SERIAL_ROM_MASK      GENMASK(26, 24)
  99 #define IMX6_BMODE_SERIAL_ROM_SHIFT     24
 100
 101 enum imx6_bmode_serial_rom {
 102         IMX6_BMODE_ECSPI1,
 103         IMX6_BMODE_ECSPI2,
 104         IMX6_BMODE_ECSPI3,
 105         IMX6_BMODE_ECSPI4,
 106         IMX6_BMODE_ECSPI5,
 107         IMX6_BMODE_I2C1,
 108         IMX6_BMODE_I2C2,
 109         IMX6_BMODE_I2C3,
 110 };
 111
 112 enum imx6_bmode_eim {
 113         IMX6_BMODE_NOR,
 114         IMX6_BMODE_ONENAND,
 115 };
 116
 117 enum imx6_bmode {
 118         IMX6_BMODE_EIM,
 119 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 120         IMX6_BMODE_QSPI,
 121         IMX6_BMODE_RESERVED,
 122 #else
 123         IMX6_BMODE_RESERVED,
 124         IMX6_BMODE_SATA,
 125 #endif
 126         IMX6_BMODE_SERIAL_ROM,
 127         IMX6_BMODE_SD,
 128         IMX6_BMODE_ESD,
 129         IMX6_BMODE_MMC,
 130         IMX6_BMODE_EMMC,
 131         IMX6_BMODE_NAND_MIN,
 132         IMX6_BMODE_NAND_MAX = 0xf,
 133 };
 134
 135 u32 imx6_src_get_boot_mode(void);
 136 void gpr_init(void);
 137
 138 #endif /* CONFIG_MX6 */
 139
 140 #ifdef CONFIG_MX7
 141 #define IMX7_SRC_GPR10_BMODE                    BIT(28)
 142 #define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT   BIT(30)
 143 #endif
 144
 145 /* address translation table */
 146 struct rproc_att {
 147         u32 da; /* device address (From Cortex M4 view) */
 148         u32 sa; /* system bus address */
 149         u32 size; /* size of reg range */
 150 };
 151
 152 const struct rproc_att *imx_bootaux_get_hostmap(void);
 153
 154 struct rom_api {
 155         u16 ver;
 156         u16 tag;
 157         u32 reserved1;
 158         u32 (*download_image)(u8 *dest, u32 offset, u32 size,  u32 xor);
 159         u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
 160 };
 161
 162 enum boot_dev_type_e {
 163         BT_DEV_TYPE_SD = 1,
 164         BT_DEV_TYPE_MMC = 2,
 165         BT_DEV_TYPE_NAND = 3,
 166         BT_DEV_TYPE_FLEXSPINOR = 4,
 167         BT_DEV_TYPE_SPI_NOR = 6,
 168
 169         BT_DEV_TYPE_USB = 0xE,
 170         BT_DEV_TYPE_MEM_DEV = 0xF,
 171
 172         BT_DEV_TYPE_INVALID = 0xFF
 173 };
 174
 175 #define QUERY_ROM_VER           1
 176 #define QUERY_BT_DEV            2
 177 #define QUERY_PAGE_SZ           3
 178 #define QUERY_IVT_OFF           4
 179 #define QUERY_BT_STAGE          5
 180 #define QUERY_IMG_OFF           6
 181
 182 #define ROM_API_OKAY            0xF0
 183
 184 extern struct rom_api *g_rom_api;
 185 extern unsigned long rom_pointer[];
 186
 187 ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
 188 ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
 189
 190 u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
 191 u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
 192
 193 /* For i.MX ULP */
 194 #define BT0CFG_LPBOOT_MASK      0x1
 195 #define BT0CFG_DUALBOOT_MASK    0x2
 196
 197 enum bt_mode {
 198         LOW_POWER_BOOT,         /* LP_BT = 1 */
 199         DUAL_BOOT,              /* LP_BT = 0, DUAL_BT = 1 */
 200         SINGLE_BOOT             /* LP_BT = 0, DUAL_BT = 0 */
 201 };
 202
 203 u32 get_nr_cpus(void);
 204 u32 get_cpu_rev(void);
 205 u32 get_cpu_speed_grade_hz(void);
 206 u32 get_cpu_temp_grade(int *minc, int *maxc);
 207 const char *get_imx_type(u32 imxtype);
 208 u32 imx_ddr_size(void);
 209 void sdelay(unsigned long);
 210 void set_chipselect_size(int const);
 211
 212 void init_aips(void);
 213 void init_src(void);
 214 void init_snvs(void);
 215 void imx_wdog_disable_powerdown(void);
 216
 217 void board_mem_get_layout(u64 *phys_sdram_1_start,
 218                           u64 *phys_sdram_1_size,
 219                           u64 *phys_sdram_2_start,
 220                           u64 *phys_sdram_2_size);
 221
 222 int arch_auxiliary_core_check_up(u32 core_id);
 223
 224 int board_mmc_get_env_dev(int devno);
 225
 226 int nxp_board_rev(void);
 227 char nxp_board_rev_string(void);
 228
 229 /*
 230  * Initializes on-chip ethernet controllers.
 231  * to override, implement board_eth_init()
 232  */
 233 int fecmxc_initialize(struct bd_info *bis);
 234 u32 get_ahb_clk(void);
 235 u32 get_periph_clk(void);
 236
 237 void lcdif_power_down(void);
 238
 239 int mxs_reset_block(struct mxs_register_32 *reg);
 240 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 241 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 242
 243 void board_late_mmc_env_init(void);
 244
 245 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 246                            unsigned long reg1, unsigned long reg2,
 247                            unsigned long reg3);
 248 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
 249                                 unsigned long *reg1, unsigned long reg2,
 250                                 unsigned long reg3);
 251
 252 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 253
 254 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
 255 void enable_ca7_smp(void);
 256 #endif
 257
 258 enum boot_device get_boot_device(void);
 259
 260 #endif