3 * Texas Instruments, <www.ti.com>
5 * Aneesh V <aneesh@ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _OMAP_COMMON_H_
10 #define _OMAP_COMMON_H_
16 #define NUM_SYS_CLKS 7
23 u32 cm_clkmode_dpll_core
;
24 u32 cm_idlest_dpll_core
;
25 u32 cm_autoidle_dpll_core
;
26 u32 cm_clksel_dpll_core
;
27 u32 cm_div_m2_dpll_core
;
28 u32 cm_div_m3_dpll_core
;
29 u32 cm_div_h11_dpll_core
;
30 u32 cm_div_h12_dpll_core
;
31 u32 cm_div_h13_dpll_core
;
32 u32 cm_div_h14_dpll_core
;
33 u32 cm_div_h21_dpll_core
;
34 u32 cm_div_h24_dpll_core
;
35 u32 cm_ssc_deltamstep_dpll_core
;
36 u32 cm_ssc_modfreqdiv_dpll_core
;
37 u32 cm_emu_override_dpll_core
;
38 u32 cm_div_h22_dpllcore
;
39 u32 cm_div_h23_dpll_core
;
40 u32 cm_clkmode_dpll_mpu
;
41 u32 cm_idlest_dpll_mpu
;
42 u32 cm_autoidle_dpll_mpu
;
43 u32 cm_clksel_dpll_mpu
;
44 u32 cm_div_m2_dpll_mpu
;
45 u32 cm_ssc_deltamstep_dpll_mpu
;
46 u32 cm_ssc_modfreqdiv_dpll_mpu
;
47 u32 cm_bypclk_dpll_mpu
;
48 u32 cm_clkmode_dpll_iva
;
49 u32 cm_idlest_dpll_iva
;
50 u32 cm_autoidle_dpll_iva
;
51 u32 cm_clksel_dpll_iva
;
52 u32 cm_div_h11_dpll_iva
;
53 u32 cm_div_h12_dpll_iva
;
54 u32 cm_ssc_deltamstep_dpll_iva
;
55 u32 cm_ssc_modfreqdiv_dpll_iva
;
56 u32 cm_bypclk_dpll_iva
;
57 u32 cm_clkmode_dpll_abe
;
58 u32 cm_idlest_dpll_abe
;
59 u32 cm_autoidle_dpll_abe
;
60 u32 cm_clksel_dpll_abe
;
61 u32 cm_div_m2_dpll_abe
;
62 u32 cm_div_m3_dpll_abe
;
63 u32 cm_ssc_deltamstep_dpll_abe
;
64 u32 cm_ssc_modfreqdiv_dpll_abe
;
65 u32 cm_clkmode_dpll_ddrphy
;
66 u32 cm_idlest_dpll_ddrphy
;
67 u32 cm_autoidle_dpll_ddrphy
;
68 u32 cm_clksel_dpll_ddrphy
;
69 u32 cm_div_m2_dpll_ddrphy
;
70 u32 cm_div_h11_dpll_ddrphy
;
71 u32 cm_div_h12_dpll_ddrphy
;
72 u32 cm_div_h13_dpll_ddrphy
;
73 u32 cm_ssc_deltamstep_dpll_ddrphy
;
74 u32 cm_clkmode_dpll_dsp
;
75 u32 cm_shadow_freq_config1
;
76 u32 cm_clkmode_dpll_gmac
;
77 u32 cm_mpu_mpu_clkctrl
;
81 u32 cm_dsp_dsp_clkctrl
;
84 u32 cm1_abe_clkstctrl
;
85 u32 cm1_abe_l4abe_clkctrl
;
86 u32 cm1_abe_aess_clkctrl
;
87 u32 cm1_abe_pdm_clkctrl
;
88 u32 cm1_abe_dmic_clkctrl
;
89 u32 cm1_abe_mcasp_clkctrl
;
90 u32 cm1_abe_mcbsp1_clkctrl
;
91 u32 cm1_abe_mcbsp2_clkctrl
;
92 u32 cm1_abe_mcbsp3_clkctrl
;
93 u32 cm1_abe_slimbus_clkctrl
;
94 u32 cm1_abe_timer5_clkctrl
;
95 u32 cm1_abe_timer6_clkctrl
;
96 u32 cm1_abe_timer7_clkctrl
;
97 u32 cm1_abe_timer8_clkctrl
;
98 u32 cm1_abe_wdt3_clkctrl
;
101 u32 cm_clksel_mpu_m3_iss_root
;
102 u32 cm_clksel_usb_60mhz
;
104 u32 cm_core_dvfs_perf1
;
105 u32 cm_core_dvfs_perf2
;
106 u32 cm_core_dvfs_perf3
;
107 u32 cm_core_dvfs_perf4
;
108 u32 cm_core_dvfs_current
;
109 u32 cm_iva_dvfs_perf_tesla
;
110 u32 cm_iva_dvfs_perf_ivahd
;
111 u32 cm_iva_dvfs_perf_abe
;
112 u32 cm_iva_dvfs_current
;
113 u32 cm_clkmode_dpll_per
;
114 u32 cm_idlest_dpll_per
;
115 u32 cm_autoidle_dpll_per
;
116 u32 cm_clksel_dpll_per
;
117 u32 cm_div_m2_dpll_per
;
118 u32 cm_div_m3_dpll_per
;
119 u32 cm_div_h11_dpll_per
;
120 u32 cm_div_h12_dpll_per
;
121 u32 cm_div_h13_dpll_per
;
122 u32 cm_div_h14_dpll_per
;
123 u32 cm_ssc_deltamstep_dpll_per
;
124 u32 cm_ssc_modfreqdiv_dpll_per
;
125 u32 cm_emu_override_dpll_per
;
126 u32 cm_clkmode_dpll_usb
;
127 u32 cm_idlest_dpll_usb
;
128 u32 cm_autoidle_dpll_usb
;
129 u32 cm_clksel_dpll_usb
;
130 u32 cm_div_m2_dpll_usb
;
131 u32 cm_ssc_deltamstep_dpll_usb
;
132 u32 cm_ssc_modfreqdiv_dpll_usb
;
133 u32 cm_clkdcoldo_dpll_usb
;
134 u32 cm_clkmode_dpll_pcie_ref
;
135 u32 cm_clkmode_apll_pcie
;
136 u32 cm_idlest_apll_pcie
;
137 u32 cm_div_m2_apll_pcie
;
138 u32 cm_clkvcoldo_apll_pcie
;
139 u32 cm_clkmode_dpll_unipro
;
140 u32 cm_idlest_dpll_unipro
;
141 u32 cm_autoidle_dpll_unipro
;
142 u32 cm_clksel_dpll_unipro
;
143 u32 cm_div_m2_dpll_unipro
;
144 u32 cm_ssc_deltamstep_dpll_unipro
;
145 u32 cm_ssc_modfreqdiv_dpll_unipro
;
146 u32 cm_coreaon_usb_phy_core_clkctrl
;
147 u32 cm_coreaon_usb_phy2_core_clkctrl
;
150 u32 cm_coreaon_bandgap_clkctrl
;
151 u32 cm_coreaon_io_srcomp_clkctrl
;
152 u32 cm_l3_1_clkstctrl
;
153 u32 cm_l3_1_dynamicdep
;
154 u32 cm_l3_1_l3_1_clkctrl
;
155 u32 cm_l3_2_clkstctrl
;
156 u32 cm_l3_2_dynamicdep
;
157 u32 cm_l3_2_l3_2_clkctrl
;
158 u32 cm_l3_gpmc_clkctrl
;
159 u32 cm_l3_2_ocmc_ram_clkctrl
;
160 u32 cm_mpu_m3_clkstctrl
;
161 u32 cm_mpu_m3_staticdep
;
162 u32 cm_mpu_m3_dynamicdep
;
163 u32 cm_mpu_m3_mpu_m3_clkctrl
;
164 u32 cm_sdma_clkstctrl
;
165 u32 cm_sdma_staticdep
;
166 u32 cm_sdma_dynamicdep
;
167 u32 cm_sdma_sdma_clkctrl
;
168 u32 cm_memif_clkstctrl
;
169 u32 cm_memif_dmm_clkctrl
;
170 u32 cm_memif_emif_fw_clkctrl
;
171 u32 cm_memif_emif_1_clkctrl
;
172 u32 cm_memif_emif_2_clkctrl
;
173 u32 cm_memif_dll_clkctrl
;
174 u32 cm_memif_emif_h1_clkctrl
;
175 u32 cm_memif_emif_h2_clkctrl
;
176 u32 cm_memif_dll_h_clkctrl
;
177 u32 cm_c2c_clkstctrl
;
178 u32 cm_c2c_staticdep
;
179 u32 cm_c2c_dynamicdep
;
180 u32 cm_c2c_sad2d_clkctrl
;
181 u32 cm_c2c_modem_icr_clkctrl
;
182 u32 cm_c2c_sad2d_fw_clkctrl
;
183 u32 cm_l4cfg_clkstctrl
;
184 u32 cm_l4cfg_dynamicdep
;
185 u32 cm_l4cfg_l4_cfg_clkctrl
;
186 u32 cm_l4cfg_hw_sem_clkctrl
;
187 u32 cm_l4cfg_mailbox_clkctrl
;
188 u32 cm_l4cfg_sar_rom_clkctrl
;
189 u32 cm_l3instr_clkstctrl
;
190 u32 cm_l3instr_l3_3_clkctrl
;
191 u32 cm_l3instr_l3_instr_clkctrl
;
192 u32 cm_l3instr_intrconn_wp1_clkctrl
;
195 u32 cm_ivahd_clkstctrl
;
196 u32 cm_ivahd_ivahd_clkctrl
;
197 u32 cm_ivahd_sl2_clkctrl
;
200 u32 cm_cam_clkstctrl
;
201 u32 cm_cam_iss_clkctrl
;
202 u32 cm_cam_fdif_clkctrl
;
203 u32 cm_cam_vip1_clkctrl
;
204 u32 cm_cam_vip2_clkctrl
;
205 u32 cm_cam_vip3_clkctrl
;
206 u32 cm_cam_lvdsrx_clkctrl
;
207 u32 cm_cam_csi1_clkctrl
;
208 u32 cm_cam_csi2_clkctrl
;
211 u32 cm_dss_clkstctrl
;
212 u32 cm_dss_dss_clkctrl
;
215 u32 cm_sgx_clkstctrl
;
216 u32 cm_sgx_sgx_clkctrl
;
219 u32 cm_l3init_clkstctrl
;
222 u32 cm_l3init_hsmmc1_clkctrl
;
223 u32 cm_l3init_hsmmc2_clkctrl
;
224 u32 cm_l3init_hsi_clkctrl
;
225 u32 cm_l3init_hsusbhost_clkctrl
;
226 u32 cm_l3init_hsusbotg_clkctrl
;
227 u32 cm_l3init_hsusbtll_clkctrl
;
228 u32 cm_l3init_p1500_clkctrl
;
229 u32 cm_l3init_sata_clkctrl
;
230 u32 cm_l3init_fsusb_clkctrl
;
231 u32 cm_l3init_ocp2scp1_clkctrl
;
232 u32 cm_l3init_ocp2scp3_clkctrl
;
233 u32 cm_l3init_usb_otg_ss_clkctrl
;
235 u32 prm_irqstatus_mpu_2
;
238 u32 cm_l4per_clkstctrl
;
239 u32 cm_l4per_dynamicdep
;
240 u32 cm_l4per_adc_clkctrl
;
241 u32 cm_l4per_gptimer10_clkctrl
;
242 u32 cm_l4per_gptimer11_clkctrl
;
243 u32 cm_l4per_gptimer2_clkctrl
;
244 u32 cm_l4per_gptimer3_clkctrl
;
245 u32 cm_l4per_gptimer4_clkctrl
;
246 u32 cm_l4per_gptimer9_clkctrl
;
247 u32 cm_l4per_elm_clkctrl
;
248 u32 cm_l4per_gpio2_clkctrl
;
249 u32 cm_l4per_gpio3_clkctrl
;
250 u32 cm_l4per_gpio4_clkctrl
;
251 u32 cm_l4per_gpio5_clkctrl
;
252 u32 cm_l4per_gpio6_clkctrl
;
253 u32 cm_l4per_hdq1w_clkctrl
;
254 u32 cm_l4per_hecc1_clkctrl
;
255 u32 cm_l4per_hecc2_clkctrl
;
256 u32 cm_l4per_i2c1_clkctrl
;
257 u32 cm_l4per_i2c2_clkctrl
;
258 u32 cm_l4per_i2c3_clkctrl
;
259 u32 cm_l4per_i2c4_clkctrl
;
260 u32 cm_l4per_l4per_clkctrl
;
261 u32 cm_l4per_mcasp2_clkctrl
;
262 u32 cm_l4per_mcasp3_clkctrl
;
263 u32 cm_l4per_mgate_clkctrl
;
264 u32 cm_l4per_mcspi1_clkctrl
;
265 u32 cm_l4per_mcspi2_clkctrl
;
266 u32 cm_l4per_mcspi3_clkctrl
;
267 u32 cm_l4per_mcspi4_clkctrl
;
268 u32 cm_l4per_gpio7_clkctrl
;
269 u32 cm_l4per_gpio8_clkctrl
;
270 u32 cm_l4per_mmcsd3_clkctrl
;
271 u32 cm_l4per_mmcsd4_clkctrl
;
272 u32 cm_l4per_msprohg_clkctrl
;
273 u32 cm_l4per_slimbus2_clkctrl
;
274 u32 cm_l4per_qspi_clkctrl
;
275 u32 cm_l4per_uart1_clkctrl
;
276 u32 cm_l4per_uart2_clkctrl
;
277 u32 cm_l4per_uart3_clkctrl
;
278 u32 cm_l4per_uart4_clkctrl
;
279 u32 cm_l4per_mmcsd5_clkctrl
;
280 u32 cm_l4per_i2c5_clkctrl
;
281 u32 cm_l4per_uart5_clkctrl
;
282 u32 cm_l4per_uart6_clkctrl
;
283 u32 cm_l4sec_clkstctrl
;
284 u32 cm_l4sec_staticdep
;
285 u32 cm_l4sec_dynamicdep
;
286 u32 cm_l4sec_aes1_clkctrl
;
287 u32 cm_l4sec_aes2_clkctrl
;
288 u32 cm_l4sec_des3des_clkctrl
;
289 u32 cm_l4sec_pkaeip29_clkctrl
;
290 u32 cm_l4sec_rng_clkctrl
;
291 u32 cm_l4sec_sha2md51_clkctrl
;
292 u32 cm_l4sec_cryptodma_clkctrl
;
295 u32 cm_abe_pll_ref_clksel
;
297 u32 cm_abe_pll_sys_clksel
;
298 u32 cm_wkup_clkstctrl
;
299 u32 cm_wkup_l4wkup_clkctrl
;
300 u32 cm_wkup_wdtimer1_clkctrl
;
301 u32 cm_wkup_wdtimer2_clkctrl
;
302 u32 cm_wkup_gpio1_clkctrl
;
303 u32 cm_wkup_gptimer1_clkctrl
;
304 u32 cm_wkup_gptimer12_clkctrl
;
305 u32 cm_wkup_synctimer_clkctrl
;
306 u32 cm_wkup_usim_clkctrl
;
307 u32 cm_wkup_sarram_clkctrl
;
308 u32 cm_wkup_keyboard_clkctrl
;
309 u32 cm_wkup_rtc_clkctrl
;
310 u32 cm_wkup_bandgap_clkctrl
;
311 u32 cm_wkupaon_scrm_clkctrl
;
312 u32 cm_wkupaon_io_srcomp_clkctrl
;
316 u32 prm_vc_val_bypass
;
317 u32 prm_vc_cfg_i2c_mode
;
318 u32 prm_vc_cfg_i2c_clk
;
319 u32 prm_abbldo_mpu_setup
;
320 u32 prm_abbldo_mpu_ctrl
;
322 u32 cm_div_m4_dpll_core
;
323 u32 cm_div_m5_dpll_core
;
324 u32 cm_div_m6_dpll_core
;
325 u32 cm_div_m7_dpll_core
;
326 u32 cm_div_m4_dpll_iva
;
327 u32 cm_div_m5_dpll_iva
;
328 u32 cm_div_m4_dpll_ddrphy
;
329 u32 cm_div_m5_dpll_ddrphy
;
330 u32 cm_div_m6_dpll_ddrphy
;
331 u32 cm_div_m4_dpll_per
;
332 u32 cm_div_m5_dpll_per
;
333 u32 cm_div_m6_dpll_per
;
334 u32 cm_div_m7_dpll_per
;
335 u32 cm_l3instr_intrconn_wp1_clkct
;
336 u32 cm_l3init_usbphy_clkctrl
;
337 u32 cm_l4per_mcbsp4_clkctrl
;
338 u32 prm_vc_cfg_channel
;
340 /* SCRM stuff, used by some boards */
345 u32 cm_gmac_gmac_clkctrl
;
346 u32 cm_gmac_clkstctrl
;
349 struct omap_sys_ctrl_regs
{
351 u32 control_core_mac_id_0_lo
;
352 u32 control_core_mac_id_0_hi
;
353 u32 control_core_mac_id_1_lo
;
354 u32 control_core_mac_id_1_hi
;
355 u32 control_std_fuse_opp_vdd_mpu_2
;
356 u32 control_phy_power_usb
;
357 u32 control_core_mmr_lock1
;
358 u32 control_core_mmr_lock2
;
359 u32 control_core_mmr_lock3
;
360 u32 control_core_mmr_lock4
;
361 u32 control_core_mmr_lock5
;
362 u32 control_core_control_io1
;
363 u32 control_core_control_io2
;
365 u32 control_std_fuse_opp_bgap
;
366 u32 control_ldosram_iva_voltage_ctrl
;
367 u32 control_ldosram_mpu_voltage_ctrl
;
368 u32 control_ldosram_core_voltage_ctrl
;
369 u32 control_usbotghs_ctrl
;
370 u32 control_phy_power_sata
;
371 u32 control_padconf_core_base
;
372 u32 control_paconf_global
;
373 u32 control_paconf_mode
;
374 u32 control_smart1io_padconf_0
;
375 u32 control_smart1io_padconf_1
;
376 u32 control_smart1io_padconf_2
;
377 u32 control_smart2io_padconf_0
;
378 u32 control_smart2io_padconf_1
;
379 u32 control_smart2io_padconf_2
;
380 u32 control_smart3io_padconf_0
;
381 u32 control_smart3io_padconf_1
;
384 u32 control_camera_rx
;
385 u32 control_hdmi_tx_phy
;
386 u32 control_uniportm
;
389 u32 control_usb2phycore
;
392 u32 control_ddr3ch1_0
;
393 u32 control_ddr3ch2_0
;
394 u32 control_ddrch1_0
;
395 u32 control_ddrch1_1
;
396 u32 control_ddrch2_0
;
397 u32 control_ddrch2_1
;
398 u32 control_lpddr2ch1_0
;
399 u32 control_lpddr2ch1_1
;
403 u32 control_ddr_control_ext_0
;
404 u32 control_lpddr2io1_0
;
405 u32 control_lpddr2io1_1
;
406 u32 control_lpddr2io1_2
;
407 u32 control_lpddr2io1_3
;
408 u32 control_lpddr2io2_0
;
409 u32 control_lpddr2io2_1
;
410 u32 control_lpddr2io2_2
;
411 u32 control_lpddr2io2_3
;
413 u32 control_usbb_hsic_control
;
415 u32 control_core_control_spare_rw
;
416 u32 control_core_control_spare_r
;
417 u32 control_core_control_spare_r_c0
;
418 u32 control_srcomp_north_side
;
419 u32 control_srcomp_south_side
;
420 u32 control_srcomp_east_side
;
421 u32 control_srcomp_west_side
;
422 u32 control_srcomp_code_latch
;
423 u32 control_pbiaslite
;
424 u32 control_port_emif1_sdram_config
;
425 u32 control_port_emif1_lpddr2_nvm_config
;
426 u32 control_port_emif2_sdram_config
;
427 u32 control_emif1_sdram_config_ext
;
428 u32 control_emif2_sdram_config_ext
;
429 u32 control_wkup_ldovbb_mpu_voltage_ctrl
;
430 u32 control_smart1nopmio_padconf_0
;
431 u32 control_smart1nopmio_padconf_1
;
432 u32 control_padconf_mode
;
433 u32 control_xtal_oscillator
;
435 u32 control_ckobuffer
;
436 u32 control_wkup_control_spare_rw
;
437 u32 control_wkup_control_spare_r
;
438 u32 control_wkup_control_spare_r_c0
;
439 u32 control_srcomp_east_side_wkup
;
449 u32 control_efuse_10
;
450 u32 control_efuse_11
;
451 u32 control_efuse_12
;
452 u32 control_efuse_13
;
453 u32 control_padconf_wkup_base
;
474 u32 cm_autoidle_dpll
;
478 u32 cm_div_m4_h11_dpll
;
479 u32 cm_div_m5_h12_dpll
;
480 u32 cm_div_m6_h13_dpll
;
481 u32 cm_div_m7_h14_dpll
;
490 const struct dpll_params
*mpu
;
491 const struct dpll_params
*core
;
492 const struct dpll_params
*per
;
493 const struct dpll_params
*abe
;
494 const struct dpll_params
*iva
;
495 const struct dpll_params
*usb
;
496 const struct dpll_params
*ddr
;
497 const struct dpll_params
*gmac
;
507 void (*pmic_bus_init
)(void);
508 int (*pmic_write
)(u8 sa
, u8 reg_addr
, u8 reg_data
);
512 * struct volts_efuse_data - efuse definition for voltage
513 * @reg: register address for efuse
514 * @reg_bits: Number of bits in a register address, mandatory.
516 struct volts_efuse_data
{
524 struct volts_efuse_data efuse
;
525 struct pmic_data
*pmic
;
537 extern struct prcm_regs
const **prcm
;
538 extern struct prcm_regs
const omap5_es1_prcm
;
539 extern struct prcm_regs
const omap5_es2_prcm
;
540 extern struct prcm_regs
const omap4_prcm
;
541 extern struct prcm_regs
const dra7xx_prcm
;
542 extern struct dplls
const **dplls_data
;
543 extern struct vcores_data
const **omap_vcores
;
544 extern const u32 sys_clk_array
[8];
545 extern struct omap_sys_ctrl_regs
const **ctrl
;
546 extern struct omap_sys_ctrl_regs
const omap4_ctrl
;
547 extern struct omap_sys_ctrl_regs
const omap5_ctrl
;
548 extern struct omap_sys_ctrl_regs
const dra7xx_ctrl
;
550 void hw_data_init(void);
552 const struct dpll_params
*get_mpu_dpll_params(struct dplls
const *);
553 const struct dpll_params
*get_core_dpll_params(struct dplls
const *);
554 const struct dpll_params
*get_per_dpll_params(struct dplls
const *);
555 const struct dpll_params
*get_iva_dpll_params(struct dplls
const *);
556 const struct dpll_params
*get_usb_dpll_params(struct dplls
const *);
557 const struct dpll_params
*get_abe_dpll_params(struct dplls
const *);
559 void do_enable_clocks(u32
const *clk_domains
,
560 u32
const *clk_modules_hw_auto
,
561 u32
const *clk_modules_explicit_en
,
564 void setup_post_dividers(u32
const base
,
565 const struct dpll_params
*params
);
566 u32
omap_ddr_clk(void);
567 u32
get_sys_clk_index(void);
568 void enable_basic_clocks(void);
569 void enable_basic_uboot_clocks(void);
570 void scale_vcores(struct vcores_data
const *);
571 u32
get_offset_code(u32 volt_offset
, struct pmic_data
*pmic
);
572 void do_scale_vcore(u32 vcore_reg
, u32 volt_mv
, struct pmic_data
*pmic
);
573 void abb_setup(u32 fuse
, u32 ldovbb
, u32 setup
, u32 control
,
574 u32 txdone
, u32 txdone_mask
, u32 opp
);
575 s8
abb_setup_ldovbb(u32 fuse
, u32 ldovbb
);
577 void usb_fake_mac_from_die_id(u32
*id
);
580 #define OMAP_ABB_NOMINAL_OPP 0
581 #define OMAP_ABB_FAST_OPP 1
582 #define OMAP_ABB_SLOW_OPP 3
583 #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
584 #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
585 #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
586 #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
587 #define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
588 #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
589 #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
590 #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
592 static inline u32
omap_revision(void)
594 extern u32
*const omap_si_rev
;
598 #define OMAP44xx 0x44000000
600 static inline u8
is_omap44xx(void)
602 extern u32
*const omap_si_rev
;
603 return (*omap_si_rev
& 0xFF000000) == OMAP44xx
;
606 #define OMAP54xx 0x54000000
608 static inline u8
is_omap54xx(void)
610 extern u32
*const omap_si_rev
;
611 return ((*omap_si_rev
& 0xFF000000) == OMAP54xx
);
614 #define DRA7XX 0x07000000
616 static inline u8
is_dra7xx(void)
618 extern u32
*const omap_si_rev
;
619 return ((*omap_si_rev
& 0xFF000000) == DRA7XX
);
625 * Moving this to common, so that most of code can be moved to common,
630 #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
631 #define OMAP4430_ES1_0 0x44300100
632 #define OMAP4430_ES2_0 0x44300200
633 #define OMAP4430_ES2_1 0x44300210
634 #define OMAP4430_ES2_2 0x44300220
635 #define OMAP4430_ES2_3 0x44300230
636 #define OMAP4460_ES1_0 0x44600100
637 #define OMAP4460_ES1_1 0x44600110
638 #define OMAP4470_ES1_0 0x44700100
641 #define OMAP5430_SILICON_ID_INVALID 0
642 #define OMAP5430_ES1_0 0x54300100
643 #define OMAP5432_ES1_0 0x54320100
644 #define OMAP5430_ES2_0 0x54300200
645 #define OMAP5432_ES2_0 0x54320200
648 #define DRA752_ES1_0 0x07520100
649 #define DRA752_ES1_1 0x07520110
650 #define DRA722_ES1_0 0x07220100
653 * SRAM scratch space entries
655 #define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
656 #define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
657 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
658 #define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
659 #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
660 #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
661 #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
662 #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
663 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
664 #define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
666 #endif /* _OMAP_COMMON_H_ */