]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/lib/cache-cp15.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/system.h>
26 #include <asm/cache.h>
27 #include <linux/compiler.h>
29 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
31 DECLARE_GLOBAL_DATA_PTR
;
33 void __arm_init_before_mmu(void)
36 void arm_init_before_mmu(void)
37 __attribute__((weak
, alias("__arm_init_before_mmu")));
39 __weak
void arm_init_domains(void)
43 static void cp_delay (void)
47 /* copro seems to need some delay between reading and writing */
48 for (i
= 0; i
< 100; i
++)
50 asm volatile("" : : : "memory");
53 void set_section_dcache(int section
, enum dcache_option option
)
55 u32
*page_table
= (u32
*)gd
->arch
.tlb_addr
;
58 value
= (section
<< MMU_SECTION_SHIFT
) | (3 << 10);
60 page_table
[section
] = value
;
63 void __mmu_page_table_flush(unsigned long start
, unsigned long stop
)
65 debug("%s: Warning: not implemented\n", __func__
);
68 void mmu_page_table_flush(unsigned long start
, unsigned long stop
)
69 __attribute__((weak
, alias("__mmu_page_table_flush")));
71 void mmu_set_region_dcache_behaviour(u32 start
, int size
,
72 enum dcache_option option
)
74 u32
*page_table
= (u32
*)gd
->arch
.tlb_addr
;
77 end
= ALIGN(start
+ size
, MMU_SECTION_SIZE
) >> MMU_SECTION_SHIFT
;
78 start
= start
>> MMU_SECTION_SHIFT
;
79 debug("%s: start=%x, size=%x, option=%d\n", __func__
, start
, size
,
81 for (upto
= start
; upto
< end
; upto
++)
82 set_section_dcache(upto
, option
);
83 mmu_page_table_flush((u32
)&page_table
[start
], (u32
)&page_table
[end
]);
86 __weak
void dram_bank_mmu_setup(int bank
)
91 debug("%s: bank: %d\n", __func__
, bank
);
92 for (i
= bd
->bi_dram
[bank
].start
>> 20;
93 i
< (bd
->bi_dram
[bank
].start
+ bd
->bi_dram
[bank
].size
) >> 20;
95 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
96 set_section_dcache(i
, DCACHE_WRITETHROUGH
);
98 set_section_dcache(i
, DCACHE_WRITEBACK
);
103 /* to activate the MMU we need to set up virtual memory: use 1M areas */
104 static inline void mmu_setup(void)
109 arm_init_before_mmu();
110 /* Set up an identity-mapping for all 4GB, rw for everyone */
111 for (i
= 0; i
< 4096; i
++)
112 set_section_dcache(i
, DCACHE_OFF
);
114 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
115 dram_bank_mmu_setup(i
);
118 /* Copy the page table address to cp15 */
119 asm volatile("mcr p15, 0, %0, c2, c0, 0"
120 : : "r" (gd
->arch
.tlb_addr
) : "memory");
121 /* Set the access control to all-supervisor */
122 asm volatile("mcr p15, 0, %0, c3, c0, 0"
127 /* and enable the mmu */
128 reg
= get_cr(); /* get control reg. */
133 static int mmu_enabled(void)
135 return get_cr() & CR_M
;
138 /* cache_bit must be either CR_I or CR_C */
139 static void cache_enable(uint32_t cache_bit
)
143 /* The data cache is not active unless the mmu is enabled too */
144 if ((cache_bit
== CR_C
) && !mmu_enabled())
146 reg
= get_cr(); /* get control reg. */
148 set_cr(reg
| cache_bit
);
151 /* cache_bit must be either CR_I or CR_C */
152 static void cache_disable(uint32_t cache_bit
)
159 if (cache_bit
== CR_C
) {
160 /* if cache isn;t enabled no need to disable */
161 if ((reg
& CR_C
) != CR_C
)
163 /* if disabling data cache, disable mmu too */
168 if (cache_bit
== (CR_C
| CR_M
))
170 set_cr(reg
& ~cache_bit
);
174 #ifdef CONFIG_SYS_ICACHE_OFF
175 void icache_enable (void)
180 void icache_disable (void)
185 int icache_status (void)
187 return 0; /* always off */
190 void icache_enable(void)
195 void icache_disable(void)
200 int icache_status(void)
202 return (get_cr() & CR_I
) != 0;
206 #ifdef CONFIG_SYS_DCACHE_OFF
207 void dcache_enable (void)
212 void dcache_disable (void)
217 int dcache_status (void)
219 return 0; /* always off */
222 void dcache_enable(void)
227 void dcache_disable(void)
232 int dcache_status(void)
234 return (get_cr() & CR_C
) != 0;