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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/lib/cache-cp15.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/system.h>
27 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
29 DECLARE_GLOBAL_DATA_PTR
;
31 void __arm_init_before_mmu(void)
34 void arm_init_before_mmu(void)
35 __attribute__((weak
, alias("__arm_init_before_mmu")));
37 static void cp_delay (void)
41 /* copro seems to need some delay between reading and writing */
42 for (i
= 0; i
< 100; i
++)
44 asm volatile("" : : : "memory");
47 void set_section_dcache(int section
, enum dcache_option option
)
49 u32
*page_table
= (u32
*)gd
->tlb_addr
;
52 value
= (section
<< MMU_SECTION_SHIFT
) | (3 << 10);
54 page_table
[section
] = value
;
57 void __mmu_page_table_flush(unsigned long start
, unsigned long stop
)
59 debug("%s: Warning: not implemented\n", __func__
);
62 void mmu_page_table_flush(unsigned long start
, unsigned long stop
)
63 __attribute__((weak
, alias("__mmu_page_table_flush")));
65 void mmu_set_region_dcache_behaviour(u32 start
, int size
,
66 enum dcache_option option
)
68 u32
*page_table
= (u32
*)gd
->tlb_addr
;
71 end
= ALIGN(start
+ size
, MMU_SECTION_SIZE
) >> MMU_SECTION_SHIFT
;
72 start
= start
>> MMU_SECTION_SHIFT
;
73 debug("%s: start=%x, size=%x, option=%d\n", __func__
, start
, size
,
75 for (upto
= start
; upto
< end
; upto
++)
76 set_section_dcache(upto
, option
);
77 mmu_page_table_flush((u32
)&page_table
[start
], (u32
)&page_table
[end
]);
80 static inline void dram_bank_mmu_setup(int bank
)
85 debug("%s: bank: %d\n", __func__
, bank
);
86 for (i
= bd
->bi_dram
[bank
].start
>> 20;
87 i
< (bd
->bi_dram
[bank
].start
+ bd
->bi_dram
[bank
].size
) >> 20;
89 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
90 set_section_dcache(i
, DCACHE_WRITETHROUGH
);
92 set_section_dcache(i
, DCACHE_WRITEBACK
);
97 /* to activate the MMU we need to set up virtual memory: use 1M areas */
98 static inline void mmu_setup(void)
103 arm_init_before_mmu();
104 /* Set up an identity-mapping for all 4GB, rw for everyone */
105 for (i
= 0; i
< 4096; i
++)
106 set_section_dcache(i
, DCACHE_OFF
);
108 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
109 dram_bank_mmu_setup(i
);
112 /* Copy the page table address to cp15 */
113 asm volatile("mcr p15, 0, %0, c2, c0, 0"
114 : : "r" (gd
->tlb_addr
) : "memory");
115 /* Set the access control to all-supervisor */
116 asm volatile("mcr p15, 0, %0, c3, c0, 0"
118 /* and enable the mmu */
119 reg
= get_cr(); /* get control reg. */
124 static int mmu_enabled(void)
126 return get_cr() & CR_M
;
129 /* cache_bit must be either CR_I or CR_C */
130 static void cache_enable(uint32_t cache_bit
)
134 /* The data cache is not active unless the mmu is enabled too */
135 if ((cache_bit
== CR_C
) && !mmu_enabled())
137 reg
= get_cr(); /* get control reg. */
139 set_cr(reg
| cache_bit
);
142 /* cache_bit must be either CR_I or CR_C */
143 static void cache_disable(uint32_t cache_bit
)
150 if (cache_bit
== CR_C
) {
151 /* if cache isn;t enabled no need to disable */
152 if ((reg
& CR_C
) != CR_C
)
154 /* if disabling data cache, disable mmu too */
158 set_cr(reg
& ~cache_bit
);
162 #ifdef CONFIG_SYS_ICACHE_OFF
163 void icache_enable (void)
168 void icache_disable (void)
173 int icache_status (void)
175 return 0; /* always off */
178 void icache_enable(void)
183 void icache_disable(void)
188 int icache_status(void)
190 return (get_cr() & CR_I
) != 0;
194 #ifdef CONFIG_SYS_DCACHE_OFF
195 void dcache_enable (void)
200 void dcache_disable (void)
205 int dcache_status (void)
207 return 0; /* always off */
210 void dcache_enable(void)
215 void dcache_disable(void)
220 int dcache_status(void)
222 return (get_cr() & CR_C
) != 0;