arch/arm/lib/cache-cp15.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/system.h>
  26
  27 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 void __arm_init_before_mmu(void)
  32 {
  33 }
  34 void arm_init_before_mmu(void)
  35         __attribute__((weak, alias("__arm_init_before_mmu")));
  36
  37 static void cp_delay (void)
  38 {
  39         volatile int i;
  40
  41         /* copro seems to need some delay between reading and writing */
  42         for (i = 0; i < 100; i++)
  43                 nop();
  44         asm volatile("" : : : "memory");
  45 }
  46
  47 void set_section_dcache(int section, enum dcache_option option)
  48 {
  49         u32 *page_table = (u32 *)gd->tlb_addr;
  50         u32 value;
  51
  52         value = (section << MMU_SECTION_SHIFT) | (3 << 10);
  53         value |= option;
  54         page_table[section] = value;
  55 }
  56
  57 void __mmu_page_table_flush(unsigned long start, unsigned long stop)
  58 {
  59         debug("%s: Warning: not implemented\n", __func__);
  60 }
  61
  62 void mmu_page_table_flush(unsigned long start, unsigned long stop)
  63         __attribute__((weak, alias("__mmu_page_table_flush")));
  64
  65 void mmu_set_region_dcache_behaviour(u32 start, int size,
  66                                      enum dcache_option option)
  67 {
  68         u32 *page_table = (u32 *)gd->tlb_addr;
  69         u32 upto, end;
  70
  71         end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
  72         start = start >> MMU_SECTION_SHIFT;
  73         debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
  74               option);
  75         for (upto = start; upto < end; upto++)
  76                 set_section_dcache(upto, option);
  77         mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
  78 }
  79
  80 static inline void dram_bank_mmu_setup(int bank)
  81 {
  82         bd_t *bd = gd->bd;
  83         int     i;
  84
  85         debug("%s: bank: %d\n", __func__, bank);
  86         for (i = bd->bi_dram[bank].start >> 20;
  87              i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
  88              i++) {
  89 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  90                 set_section_dcache(i, DCACHE_WRITETHROUGH);
  91 #else
  92                 set_section_dcache(i, DCACHE_WRITEBACK);
  93 #endif
  94         }
  95 }
  96
  97 /* to activate the MMU we need to set up virtual memory: use 1M areas */
  98 static inline void mmu_setup(void)
  99 {
 100         int i;
 101         u32 reg;
 102
 103         arm_init_before_mmu();
 104         /* Set up an identity-mapping for all 4GB, rw for everyone */
 105         for (i = 0; i < 4096; i++)
 106                 set_section_dcache(i, DCACHE_OFF);
 107
 108         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 109                 dram_bank_mmu_setup(i);
 110         }
 111
 112         /* Copy the page table address to cp15 */
 113         asm volatile("mcr p15, 0, %0, c2, c0, 0"
 114                      : : "r" (gd->tlb_addr) : "memory");
 115         /* Set the access control to all-supervisor */
 116         asm volatile("mcr p15, 0, %0, c3, c0, 0"
 117                      : : "r" (~0));
 118         /* and enable the mmu */
 119         reg = get_cr(); /* get control reg. */
 120         cp_delay();
 121         set_cr(reg | CR_M);
 122 }
 123
 124 static int mmu_enabled(void)
 125 {
 126         return get_cr() & CR_M;
 127 }
 128
 129 /* cache_bit must be either CR_I or CR_C */
 130 static void cache_enable(uint32_t cache_bit)
 131 {
 132         uint32_t reg;
 133
 134         /* The data cache is not active unless the mmu is enabled too */
 135         if ((cache_bit == CR_C) && !mmu_enabled())
 136                 mmu_setup();
 137         reg = get_cr(); /* get control reg. */
 138         cp_delay();
 139         set_cr(reg | cache_bit);
 140 }
 141
 142 /* cache_bit must be either CR_I or CR_C */
 143 static void cache_disable(uint32_t cache_bit)
 144 {
 145         uint32_t reg;
 146
 147         reg = get_cr();
 148         cp_delay();
 149
 150         if (cache_bit == CR_C) {
 151                 /* if cache isn;t enabled no need to disable */
 152                 if ((reg & CR_C) != CR_C)
 153                         return;
 154                 /* if disabling data cache, disable mmu too */
 155                 cache_bit |= CR_M;
 156                 flush_dcache_all();
 157         }
 158         set_cr(reg & ~cache_bit);
 159 }
 160 #endif
 161
 162 #ifdef CONFIG_SYS_ICACHE_OFF
 163 void icache_enable (void)
 164 {
 165         return;
 166 }
 167
 168 void icache_disable (void)
 169 {
 170         return;
 171 }
 172
 173 int icache_status (void)
 174 {
 175         return 0;                                       /* always off */
 176 }
 177 #else
 178 void icache_enable(void)
 179 {
 180         cache_enable(CR_I);
 181 }
 182
 183 void icache_disable(void)
 184 {
 185         cache_disable(CR_I);
 186 }
 187
 188 int icache_status(void)
 189 {
 190         return (get_cr() & CR_I) != 0;
 191 }
 192 #endif
 193
 194 #ifdef CONFIG_SYS_DCACHE_OFF
 195 void dcache_enable (void)
 196 {
 197         return;
 198 }
 199
 200 void dcache_disable (void)
 201 {
 202         return;
 203 }
 204
 205 int dcache_status (void)
 206 {
 207         return 0;                                       /* always off */
 208 }
 209 #else
 210 void dcache_enable(void)
 211 {
 212         cache_enable(CR_C);
 213 }
 214
 215 void dcache_disable(void)
 216 {
 217         cache_disable(CR_C);
 218 }
 219
 220 int dcache_status(void)
 221 {
 222         return (get_cr() & CR_C) != 0;
 223 }
 224 #endif