arch/arm/lib/cache-cp15.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/system.h>
  10 #include <asm/cache.h>
  11 #include <linux/compiler.h>
  12
  13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 __weak void arm_init_before_mmu(void)
  18 {
  19 }
  20
  21 __weak void arm_init_domains(void)
  22 {
  23 }
  24
  25 static void cp_delay (void)
  26 {
  27         volatile int i;
  28
  29         /* copro seems to need some delay between reading and writing */
  30         for (i = 0; i < 100; i++)
  31                 nop();
  32         asm volatile("" : : : "memory");
  33 }
  34
  35 void set_section_dcache(int section, enum dcache_option option)
  36 {
  37         u32 *page_table = (u32 *)gd->arch.tlb_addr;
  38         u32 value;
  39
  40         value = (section << MMU_SECTION_SHIFT) | (3 << 10);
  41         value |= option;
  42         page_table[section] = value;
  43 }
  44
  45 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  46 {
  47         debug("%s: Warning: not implemented\n", __func__);
  48 }
  49
  50 void mmu_set_region_dcache_behaviour(u32 start, int size,
  51                                      enum dcache_option option)
  52 {
  53         u32 *page_table = (u32 *)gd->arch.tlb_addr;
  54         u32 upto, end;
  55
  56         end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
  57         start = start >> MMU_SECTION_SHIFT;
  58         debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
  59               option);
  60         for (upto = start; upto < end; upto++)
  61                 set_section_dcache(upto, option);
  62         mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
  63 }
  64
  65 __weak void dram_bank_mmu_setup(int bank)
  66 {
  67         bd_t *bd = gd->bd;
  68         int     i;
  69
  70         debug("%s: bank: %d\n", __func__, bank);
  71         for (i = bd->bi_dram[bank].start >> 20;
  72              i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
  73              i++) {
  74 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  75                 set_section_dcache(i, DCACHE_WRITETHROUGH);
  76 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  77                 set_section_dcache(i, DCACHE_WRITEALLOC);
  78 #else
  79                 set_section_dcache(i, DCACHE_WRITEBACK);
  80 #endif
  81         }
  82 }
  83
  84 /* to activate the MMU we need to set up virtual memory: use 1M areas */
  85 static inline void mmu_setup(void)
  86 {
  87         int i;
  88         u32 reg;
  89
  90         arm_init_before_mmu();
  91         /* Set up an identity-mapping for all 4GB, rw for everyone */
  92         for (i = 0; i < 4096; i++)
  93                 set_section_dcache(i, DCACHE_OFF);
  94
  95         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  96                 dram_bank_mmu_setup(i);
  97         }
  98
  99         /* Copy the page table address to cp15 */
 100         asm volatile("mcr p15, 0, %0, c2, c0, 0"
 101                      : : "r" (gd->arch.tlb_addr) : "memory");
 102         /* Set the access control to all-supervisor */
 103         asm volatile("mcr p15, 0, %0, c3, c0, 0"
 104                      : : "r" (~0));
 105
 106         arm_init_domains();
 107
 108         /* and enable the mmu */
 109         reg = get_cr(); /* get control reg. */
 110         cp_delay();
 111         set_cr(reg | CR_M);
 112 }
 113
 114 static int mmu_enabled(void)
 115 {
 116         return get_cr() & CR_M;
 117 }
 118
 119 /* cache_bit must be either CR_I or CR_C */
 120 static void cache_enable(uint32_t cache_bit)
 121 {
 122         uint32_t reg;
 123
 124         /* The data cache is not active unless the mmu is enabled too */
 125         if ((cache_bit == CR_C) && !mmu_enabled())
 126                 mmu_setup();
 127         reg = get_cr(); /* get control reg. */
 128         cp_delay();
 129         set_cr(reg | cache_bit);
 130 }
 131
 132 /* cache_bit must be either CR_I or CR_C */
 133 static void cache_disable(uint32_t cache_bit)
 134 {
 135         uint32_t reg;
 136
 137         reg = get_cr();
 138         cp_delay();
 139
 140         if (cache_bit == CR_C) {
 141                 /* if cache isn;t enabled no need to disable */
 142                 if ((reg & CR_C) != CR_C)
 143                         return;
 144                 /* if disabling data cache, disable mmu too */
 145                 cache_bit |= CR_M;
 146         }
 147         reg = get_cr();
 148         cp_delay();
 149         if (cache_bit == (CR_C | CR_M))
 150                 flush_dcache_all();
 151         set_cr(reg & ~cache_bit);
 152 }
 153 #endif
 154
 155 #ifdef CONFIG_SYS_ICACHE_OFF
 156 void icache_enable (void)
 157 {
 158         return;
 159 }
 160
 161 void icache_disable (void)
 162 {
 163         return;
 164 }
 165
 166 int icache_status (void)
 167 {
 168         return 0;                                       /* always off */
 169 }
 170 #else
 171 void icache_enable(void)
 172 {
 173         cache_enable(CR_I);
 174 }
 175
 176 void icache_disable(void)
 177 {
 178         cache_disable(CR_I);
 179 }
 180
 181 int icache_status(void)
 182 {
 183         return (get_cr() & CR_I) != 0;
 184 }
 185 #endif
 186
 187 #ifdef CONFIG_SYS_DCACHE_OFF
 188 void dcache_enable (void)
 189 {
 190         return;
 191 }
 192
 193 void dcache_disable (void)
 194 {
 195         return;
 196 }
 197
 198 int dcache_status (void)
 199 {
 200         return 0;                                       /* always off */
 201 }
 202 #else
 203 void dcache_enable(void)
 204 {
 205         cache_enable(CR_C);
 206 }
 207
 208 void dcache_disable(void)
 209 {
 210         cache_disable(CR_C);
 211 }
 212
 213 int dcache_status(void)
 214 {
 215         return (get_cr() & CR_C) != 0;
 216 }
 217 #endif