3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/types.h>
10 #include <asm/armv7.h>
11 #include <asm/pl310.h>
15 struct pl310_regs
*const pl310
= (struct pl310_regs
*)CONFIG_SYS_PL310_BASE
;
17 static void pl310_cache_sync(void)
19 writel(0, &pl310
->pl310_cache_sync
);
22 static void pl310_background_op_all_ways(u32
*op_reg
)
24 u32 assoc_16
, associativity
, way_mask
;
26 assoc_16
= readl(&pl310
->pl310_aux_ctrl
) &
27 PL310_AUX_CTRL_ASSOCIATIVITY_MASK
;
33 way_mask
= (1 << associativity
) - 1;
34 /* Invalidate all ways */
35 writel(way_mask
, op_reg
);
36 /* Wait for all ways to be invalidated */
37 while (readl(op_reg
) && way_mask
)
42 void v7_outer_cache_inval_all(void)
44 pl310_background_op_all_ways(&pl310
->pl310_inv_way
);
47 void v7_outer_cache_flush_all(void)
49 pl310_background_op_all_ways(&pl310
->pl310_clean_inv_way
);
52 /* Flush(clean invalidate) memory from start to stop-1 */
53 void v7_outer_cache_flush_range(u32 start
, u32 stop
)
55 /* PL310 currently supports only 32 bytes cache line */
56 u32 pa
, line_size
= 32;
59 * Align to the beginning of cache-line - this ensures that
60 * the first 5 bits are 0 as required by PL310 TRM
62 start
&= ~(line_size
- 1);
64 for (pa
= start
; pa
< stop
; pa
= pa
+ line_size
)
65 writel(pa
, &pl310
->pl310_clean_inv_line_pa
);
70 /* invalidate memory from start to stop-1 */
71 void v7_outer_cache_inval_range(u32 start
, u32 stop
)
73 /* PL310 currently supports only 32 bytes cache line */
74 u32 pa
, line_size
= 32;
77 * If start address is not aligned to cache-line do not
78 * invalidate the first cache-line
80 if (start
& (line_size
- 1)) {
81 printf("ERROR: %s - start address is not aligned - 0x%08x\n",
83 /* move to next cache line */
84 start
= (start
+ line_size
- 1) & ~(line_size
- 1);
88 * If stop address is not aligned to cache-line do not
89 * invalidate the last cache-line
91 if (stop
& (line_size
- 1)) {
92 printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
94 /* align to the beginning of this cache line */
95 stop
&= ~(line_size
- 1);
98 for (pa
= start
; pa
< stop
; pa
= pa
+ line_size
)
99 writel(pa
, &pl310
->pl310_inv_line_pa
);