arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2009-2011
   7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   8  * esd electronic system design gmbh <www.esd.eu>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/at91_common.h>
  16 #include <asm/arch/at91_pmc.h>
  17 #include <asm/arch/gpio.h>
  18
  19 /*
  20  * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
  21  * peripheral pins. Good to have if hardware is soldered optionally
  22  * or in case of SPI no slave is selected. Avoid lines to float
  23  * needlessly. Use a short local PUP define.
  24  *
  25  * Due to errata "TXD floats when CTS is inactive" pullups are always
  26  * on for TXD pins.
  27  */
  28 #ifdef CONFIG_AT91_GPIO_PULLUP
  29 # define PUP CONFIG_AT91_GPIO_PULLUP
  30 #else
  31 # define PUP 0
  32 #endif
  33
  34 void at91_serial0_hw_init(void)
  35 {
  36         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  37
  38         at91_set_a_periph(AT91_PIO_PORTA, 26, 1);               /* TXD0 */
  39         at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);             /* RXD0 */
  40         writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  41 }
  42
  43 void at91_serial1_hw_init(void)
  44 {
  45         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  46
  47         at91_set_a_periph(AT91_PIO_PORTD, 0, 1);                /* TXD1 */
  48         at91_set_a_periph(AT91_PIO_PORTD, 1, PUP);              /* RXD1 */
  49         writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  50 }
  51
  52 void at91_serial2_hw_init(void)
  53 {
  54         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  55
  56         at91_set_a_periph(AT91_PIO_PORTD, 2, 1);                /* TXD2 */
  57         at91_set_a_periph(AT91_PIO_PORTD, 3, PUP);              /* RXD2 */
  58         writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  59 }
  60
  61 void at91_seriald_hw_init(void)
  62 {
  63         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  64
  65         at91_set_a_periph(AT91_PIO_PORTC, 30, PUP);             /* DRXD */
  66         at91_set_a_periph(AT91_PIO_PORTC, 31, 1);               /* DTXD */
  67         writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  68 }
  69
  70 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
  71 void at91_spi0_hw_init(unsigned long cs_mask)
  72 {
  73         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  74
  75         at91_set_b_periph(AT91_PIO_PORTA, 0, PUP);      /* SPI0_MISO */
  76         at91_set_b_periph(AT91_PIO_PORTA, 1, PUP);      /* SPI0_MOSI */
  77         at91_set_b_periph(AT91_PIO_PORTA, 2, PUP);      /* SPI0_SPCK */
  78
  79         /* Enable clock */
  80         writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  81
  82         if (cs_mask & (1 << 0)) {
  83                 at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
  84         }
  85         if (cs_mask & (1 << 1)) {
  86                 at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
  87         }
  88         if (cs_mask & (1 << 2)) {
  89                 at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
  90         }
  91         if (cs_mask & (1 << 3)) {
  92                 at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
  93         }
  94         if (cs_mask & (1 << 4)) {
  95                 at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
  96         }
  97         if (cs_mask & (1 << 5)) {
  98                 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
  99         }
 100         if (cs_mask & (1 << 6)) {
 101                 at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
 102         }
 103         if (cs_mask & (1 << 7)) {
 104                 at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
 105         }
 106 }
 107
 108 void at91_spi1_hw_init(unsigned long cs_mask)
 109 {
 110         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 111
 112         at91_set_a_periph(AT91_PIO_PORTB, 12, PUP);     /* SPI1_MISO */
 113         at91_set_a_periph(AT91_PIO_PORTB, 13, PUP);     /* SPI1_MOSI */
 114         at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);     /* SPI1_SPCK */
 115
 116         /* Enable clock */
 117         writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 118
 119         if (cs_mask & (1 << 0)) {
 120                 at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
 121         }
 122         if (cs_mask & (1 << 1)) {
 123                 at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
 124         }
 125         if (cs_mask & (1 << 2)) {
 126                 at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
 127         }
 128         if (cs_mask & (1 << 3)) {
 129                 at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
 130         }
 131         if (cs_mask & (1 << 4)) {
 132                 at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
 133         }
 134         if (cs_mask & (1 << 5)) {
 135                 at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
 136         }
 137         if (cs_mask & (1 << 6)) {
 138                 at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
 139         }
 140         if (cs_mask & (1 << 7)) {
 141                 at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
 142         }
 143 }
 144 #endif
 145
 146 #if defined(CONFIG_GENERIC_ATMEL_MCI)
 147 void at91_mci_hw_init(void)
 148 {
 149         /* Enable mci clock */
 150         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 151         writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
 152
 153         at91_set_a_periph(AT91_PIO_PORTA, 6, PUP);      /* MCI1_CK */
 154
 155 #if defined(CONFIG_ATMEL_MCI_PORTB)
 156         at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);     /* MCI1_CDB */
 157         at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);     /* MCI1_DB0 */
 158         at91_set_a_periph(AT91_PIO_PORTA, 23, PUP);     /* MCI1_DB1 */
 159         at91_set_a_periph(AT91_PIO_PORTA, 24, PUP);     /* MCI1_DB2 */
 160         at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);     /* MCI1_DB3 */
 161 #else
 162         at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);      /* MCI1_CDA */
 163         at91_set_a_periph(AT91_PIO_PORTA, 8, PUP);      /* MCI1_DA0 */
 164         at91_set_a_periph(AT91_PIO_PORTA, 9, PUP);      /* MCI1_DA1 */
 165         at91_set_a_periph(AT91_PIO_PORTA, 10, PUP);     /* MCI1_DA2 */
 166         at91_set_a_periph(AT91_PIO_PORTA, 11, PUP);     /* MCI1_DA3 */
 167 #endif
 168 }
 169 #endif
 170
 171 #ifdef CONFIG_MACB
 172 void at91_macb_hw_init(void)
 173 {
 174         at91_set_a_periph(AT91_PIO_PORTE, 21, 0);       /* ETXCK_EREFCK */
 175         at91_set_b_periph(AT91_PIO_PORTC, 25, 0);       /* ERXDV */
 176         at91_set_a_periph(AT91_PIO_PORTE, 25, 0);       /* ERX0 */
 177         at91_set_a_periph(AT91_PIO_PORTE, 26, 0);       /* ERX1 */
 178         at91_set_a_periph(AT91_PIO_PORTE, 27, 0);       /* ERXER */
 179         at91_set_a_periph(AT91_PIO_PORTE, 28, 0);       /* ETXEN */
 180         at91_set_a_periph(AT91_PIO_PORTE, 23, 0);       /* ETX0 */
 181         at91_set_a_periph(AT91_PIO_PORTE, 24, 0);       /* ETX1 */
 182         at91_set_a_periph(AT91_PIO_PORTE, 30, 0);       /* EMDIO */
 183         at91_set_a_periph(AT91_PIO_PORTE, 29, 0);       /* EMDC */
 184
 185 #ifndef CONFIG_RMII
 186         at91_set_a_periph(AT91_PIO_PORTE, 22, 0);       /* ECRS */
 187         at91_set_b_periph(AT91_PIO_PORTC, 26, 0);       /* ECOL */
 188         at91_set_b_periph(AT91_PIO_PORTC, 22, 0);       /* ERX2 */
 189         at91_set_b_periph(AT91_PIO_PORTC, 23, 0);       /* ERX3 */
 190         at91_set_b_periph(AT91_PIO_PORTC, 27, 0);       /* ERXCK */
 191         at91_set_b_periph(AT91_PIO_PORTC, 20, 0);       /* ETX2 */
 192         at91_set_b_periph(AT91_PIO_PORTC, 21, 0);       /* ETX3 */
 193         at91_set_b_periph(AT91_PIO_PORTC, 24, 0);       /* ETXER */
 194 #endif
 195 }
 196 #endif
 197
 198 #ifdef CONFIG_USB_OHCI_NEW
 199 void at91_uhp_hw_init(void)
 200 {
 201         /* Enable VBus on UHP ports */
 202         at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
 203         at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
 204 }
 205 #endif
 206
 207 #ifdef CONFIG_AT91_CAN
 208 void at91_can_hw_init(void)
 209 {
 210         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 211
 212         at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* CAN_TX */
 213         at91_set_a_periph(AT91_PIO_PORTA, 14, 1);       /* CAN_RX */
 214
 215         /* Enable clock */
 216         writel(1 << ATMEL_ID_CAN, &pmc->pcer);
 217 }
 218 #endif