2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/at91_pmc.h>
16 #include <asm/arch/clk.h>
18 #if !defined(CONFIG_AT91FAMILY)
19 # error You need to define CONFIG_AT91FAMILY in your board config!
22 DECLARE_GLOBAL_DATA_PTR
;
24 static unsigned long at91_css_to_rate(unsigned long css
)
27 case AT91_PMC_MCKR_CSS_SLOW
:
28 return CONFIG_SYS_AT91_SLOW_CLOCK
;
29 case AT91_PMC_MCKR_CSS_MAIN
:
30 return gd
->arch
.main_clk_rate_hz
;
31 case AT91_PMC_MCKR_CSS_PLLA
:
32 return gd
->arch
.plla_rate_hz
;
38 static u32
at91_pll_rate(u32 freq
, u32 reg
)
43 mul
= (reg
>> 18) & 0x7f;
54 int at91_clock_init(unsigned long main_clock
)
57 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
58 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
61 * When the bootloader initialized the main oscillator correctly,
62 * there's no problem using the cycle counter. But if it didn't,
63 * or when using oscillator bypass mode, we must be told the speed
68 tmp
= readl(&pmc
->mcfr
);
69 } while (!(tmp
& AT91_PMC_MCFR_MAINRDY
));
70 tmp
&= AT91_PMC_MCFR_MAINF_MASK
;
71 main_clock
= tmp
* (CONFIG_SYS_AT91_SLOW_CLOCK
/ 16);
74 gd
->arch
.main_clk_rate_hz
= main_clock
;
76 /* report if PLLA is more than mildly overclocked */
77 gd
->arch
.plla_rate_hz
= at91_pll_rate(main_clock
, readl(&pmc
->pllar
));
80 * MCK and CPU derive from one of those primary clocks.
81 * For now, assume this parentage won't change.
83 mckr
= readl(&pmc
->mckr
);
85 /* plla divisor by 2 */
87 gd
->arch
.plla_rate_hz
>>= 1;
89 gd
->arch
.mck_rate_hz
= at91_css_to_rate(mckr
& AT91_PMC_MCKR_CSS_MASK
);
90 freq
= gd
->arch
.mck_rate_hz
;
93 freq
>>= mckr
& AT91_PMC_MCKR_PRES_MASK
;
95 switch (mckr
& AT91_PMC_MCKR_MDIV_MASK
) {
96 case AT91_PMC_MCKR_MDIV_2
:
97 gd
->arch
.mck_rate_hz
= freq
/ 2;
99 case AT91_PMC_MCKR_MDIV_3
:
100 gd
->arch
.mck_rate_hz
= freq
/ 3;
102 case AT91_PMC_MCKR_MDIV_4
:
103 gd
->arch
.mck_rate_hz
= freq
/ 4;
109 gd
->arch
.cpu_clk_rate_hz
= freq
;
114 void at91_plla_init(u32 pllar
)
116 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
118 writel(pllar
, &pmc
->pllar
);
119 while (!(readl(&pmc
->sr
) & (AT91_PMC_LOCKA
| AT91_PMC_MCKRDY
)))
123 void at91_mck_init(u32 mckr
)
125 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
128 tmp
= readl(&pmc
->mckr
);
129 tmp
&= ~(AT91_PMC_MCKR_CSS_MASK
|
130 AT91_PMC_MCKR_PRES_MASK
|
131 AT91_PMC_MCKR_MDIV_MASK
|
132 AT91_PMC_MCKR_PLLADIV_2
);
133 #ifdef CPU_HAS_H32MXDIV
134 tmp
&= ~AT91_PMC_MCKR_H32MXDIV
;
137 tmp
|= mckr
& (AT91_PMC_MCKR_CSS_MASK
|
138 AT91_PMC_MCKR_PRES_MASK
|
139 AT91_PMC_MCKR_MDIV_MASK
|
140 AT91_PMC_MCKR_PLLADIV_2
);
141 #ifdef CPU_HAS_H32MXDIV
142 tmp
|= mckr
& AT91_PMC_MCKR_H32MXDIV
;
145 writel(tmp
, &pmc
->mckr
);
147 while (!(readl(&pmc
->sr
) & AT91_PMC_MCKRDY
))
151 void at91_periph_clk_enable(int id
)
153 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
156 if (id
> AT91_PMC_PCR_PID_MASK
)
159 regval
= AT91_PMC_PCR_EN
| AT91_PMC_PCR_CMD_WRITE
| id
;
161 writel(regval
, &pmc
->pcr
);
164 void at91_periph_clk_disable(int id
)
166 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
169 if (id
> AT91_PMC_PCR_PID_MASK
)
172 regval
= AT91_PMC_PCR_CMD_WRITE
| id
;
174 writel(regval
, &pmc
->pcr
);