arch/arm/mach-at91/include/mach/at91sam9x5.h

   1 /*
   2  * Chip-specific header file for the AT91SAM9x5 family
   3  *
   4  *  Copyright (C) 2012-2013 Atmel Corporation.
   5  *
   6  * Definitions for the SoC:
   7  * AT91SAM9x5 & AT91SAM9N12
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __AT91SAM9X5_H__
  13 #define __AT91SAM9X5_H__
  14
  15 #define CONFIG_AT91FAMILY       /* it's a member of AT91 family */
  16
  17 /*
  18  * Peripheral identifiers/interrupts.
  19  */
  20 #define ATMEL_ID_FIQ    0       /* Advanced Interrupt Controller (FIQ) */
  21 #define ATMEL_ID_SYS    1       /* System Controller Interrupt */
  22 #define ATMEL_ID_PIOAB  2       /* Parallel I/O Controller A and B */
  23 #define ATMEL_ID_PIOCD  3       /* Parallel I/O Controller C and D */
  24 #define ATMEL_ID_SMD    4       /* SMD Soft Modem (SMD), only for AT91SAM9X5 */
  25 #define ATMEL_ID_FUSE   4       /* FUSE Controller, only for AT91SAM9N12 */
  26 #define ATMEL_ID_USART0 5       /* USART 0 */
  27 #define ATMEL_ID_USART1 6       /* USART 1 */
  28 #define ATMEL_ID_USART2 7       /* USART 2 */
  29 #define ATMEL_ID_USART3 8       /* USART 3 */
  30 #define ATMEL_ID_TWI0   9       /* Two-Wire Interface 0 */
  31 #define ATMEL_ID_TWI1   10      /* Two-Wire Interface 1 */
  32 #define ATMEL_ID_TWI2   11      /* Two-Wire Interface 2 */
  33 #define ATMEL_ID_HSMCI0 12      /* High Speed Multimedia Card Interface 0 */
  34 #define ATMEL_ID_SPI0   13      /* Serial Peripheral Interface 0 */
  35 #define ATMEL_ID_SPI1   14      /* Serial Peripheral Interface 1 */
  36 #define ATMEL_ID_UART0  15      /* UART 0 */
  37 #define ATMEL_ID_UART1  16      /* UART 1 */
  38 #define ATMEL_ID_TC01   17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
  39 #define ATMEL_ID_PWM    18      /* Pulse Width Modulation Controller */
  40 #define ATMEL_ID_ADC    19      /* ADC Controller */
  41 #define ATMEL_ID_DMAC0  20      /* DMA Controller 0 */
  42 #define ATMEL_ID_DMAC1  21      /* DMA Controller 1 */
  43 #define ATMEL_ID_UHPHS  22      /* USB Host High Speed */
  44 #define ATMEL_ID_UDPHS  23      /* USB Device High Speed */
  45 #define ATMEL_ID_EMAC0  24      /* Ethernet MAC0 */
  46 #define ATMEL_ID_LCDC   25      /* LCD Controller */
  47 #define ATMEL_ID_HSMCI1 26      /* High Speed Multimedia Card Interface 1 */
  48 #define ATMEL_ID_EMAC1  27      /* Ethernet MAC1 */
  49 #define ATMEL_ID_SSC    28      /* Synchronous Serial Controller */
  50 #define ATMEL_ID_TRNG   30      /* True Random Number Generator */
  51 #define ATMEL_ID_IRQ    31      /* Advanced Interrupt Controller */
  52
  53 /*
  54  * User Peripheral physical base addresses.
  55  */
  56 #define ATMEL_BASE_SPI0         0xf0000000
  57 #define ATMEL_BASE_SPI1         0xf0004000
  58 #define ATMEL_BASE_HSMCI0       0xf0008000
  59 #define ATMEL_BASE_HSMCI1       0xf000c000
  60 #define ATMEL_BASE_SSC          0xf0010000
  61 #define ATMEL_BASE_CAN0         0xf8000000
  62 #define ATMEL_BASE_CAN1         0xf8004000
  63 #define ATMEL_BASE_TC0          0xf8008000
  64 #define ATMEL_BASE_TC1          0xf8008040
  65 #define ATMEL_BASE_TC2          0xf8008080
  66 #define ATMEL_BASE_TC3          0xf800c000
  67 #define ATMEL_BASE_TC4          0xf800c040
  68 #define ATMEL_BASE_TC5          0xf800c080
  69 #define ATMEL_BASE_TWI0         0xf8010000
  70 #define ATMEL_BASE_TWI1         0xf8014000
  71 #define ATMEL_BASE_TWI2         0xf8018000
  72 #define ATMEL_BASE_USART0       0xf801c000
  73 #define ATMEL_BASE_USART1       0xf8020000
  74 #define ATMEL_BASE_USART2       0xf8024000
  75 #define ATMEL_BASE_USART3       0xf8028000
  76 #define ATMEL_BASE_EMAC0        0xf802c000
  77 #define ATMEL_BASE_EMAC1        0xf8030000
  78 #define ATMEL_BASE_PWM          0xf8034000
  79 #define ATMEL_BASE_LCDC         0xf8038000
  80 #define ATMEL_BASE_UDPHS        0xf803c000
  81 #define ATMEL_BASE_UART0        0xf8040000
  82 #define ATMEL_BASE_UART1        0xf8044000
  83 #define ATMEL_BASE_ISI          0xf8048000
  84 #define ATMEL_BASE_ADC          0xf804c000
  85 #define ATMEL_BASE_SYS          0xffffc000
  86
  87 /*
  88  * System Peripherals
  89  */
  90 #define ATMEL_BASE_FUSE         0xffffdc00
  91 #define ATMEL_BASE_MATRIX       0xffffde00
  92 #define ATMEL_BASE_PMECC        0xffffe000
  93 #define ATMEL_BASE_PMERRLOC     0xffffe600
  94 #define ATMEL_BASE_DDRSDRC      0xffffe800
  95 #define ATMEL_BASE_SMC          0xffffea00
  96 #define ATMEL_BASE_DMAC0        0xffffec00
  97 #define ATMEL_BASE_DMAC1        0xffffee00
  98 #define ATMEL_BASE_AIC          0xfffff000
  99 #define ATMEL_BASE_DBGU         0xfffff200
 100 #define ATMEL_BASE_PIOA         0xfffff400
 101 #define ATMEL_BASE_PIOB         0xfffff600
 102 #define ATMEL_BASE_PIOC         0xfffff800
 103 #define ATMEL_BASE_PIOD         0xfffffa00
 104 #define ATMEL_BASE_PMC          0xfffffc00
 105 #define ATMEL_BASE_RSTC         0xfffffe00
 106 #define ATMEL_BASE_SHDWC        0xfffffe10
 107 #define ATMEL_BASE_PIT          0xfffffe30
 108 #define ATMEL_BASE_WDT          0xfffffe40
 109 #define ATMEL_BASE_GPBR         0xfffffe60
 110 #define ATMEL_BASE_RTC          0xfffffeb0
 111
 112 /*
 113  * Internal Memory.
 114  */
 115 #define ATMEL_BASE_ROM          0x00100000 /* Internal ROM base address */
 116 #define ATMEL_BASE_SRAM         0x00300000 /* Internal SRAM base address */
 117
 118 #ifdef CONFIG_AT91SAM9N12
 119 #define ATMEL_BASE_OHCI         0x00500000 /* USB Host controller */
 120 #else   /* AT91SAM9X5 */
 121 #define ATMEL_BASE_SMD          0x00400000 /* SMD Controller */
 122 #define ATMEL_BASE_UDPHS_FIFO   0x00500000 /* USB Device HS controller */
 123 #define ATMEL_BASE_OHCI         0x00600000 /* USB Host controller (OHCI) */
 124 #define ATMEL_BASE_EHCI         0x00700000 /* USB Host controller (EHCI) */
 125 #endif
 126
 127 /* 9x5 series chip id definitions */
 128 #define ARCH_ID_AT91SAM9X5      0x819a05a0
 129 #define ARCH_ID_VERSION_MASK    0x1f
 130 #define ARCH_EXID_AT91SAM9G15   0x00000000
 131 #define ARCH_EXID_AT91SAM9G35   0x00000001
 132 #define ARCH_EXID_AT91SAM9X35   0x00000002
 133 #define ARCH_EXID_AT91SAM9G25   0x00000003
 134 #define ARCH_EXID_AT91SAM9X25   0x00000004
 135
 136 #define cpu_is_at91sam9x5()     (get_chip_id() == ARCH_ID_AT91SAM9X5)
 137 #define cpu_is_at91sam9g15()    (cpu_is_at91sam9x5() && \
 138                         (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
 139 #define cpu_is_at91sam9g25()    (cpu_is_at91sam9x5() && \
 140                         (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
 141 #define cpu_is_at91sam9g35()    (cpu_is_at91sam9x5() && \
 142                         (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
 143 #define cpu_is_at91sam9x25()    (cpu_is_at91sam9x5() && \
 144                         (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
 145 #define cpu_is_at91sam9x35()    (cpu_is_at91sam9x5() && \
 146                         (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
 147
 148 /*
 149  * Cpu Name
 150  */
 151 #ifdef CONFIG_AT91SAM9N12
 152 #define ATMEL_CPU_NAME  "AT91SAM9N12"
 153 #else   /* AT91SAM9X5 */
 154 #define ATMEL_CPU_NAME  get_cpu_name()
 155 #endif
 156
 157 /* Timer */
 158 #define CONFIG_SYS_TIMER_COUNTER        0xfffffe3c
 159
 160 /*
 161  * Other misc defines
 162  */
 163 #define ATMEL_PIO_PORTS         4
 164 #define CPU_HAS_PIO3
 165 #define PIO_SCDR_DIV            (0x3fff <<  0)  /* Slow Clock Divider Mask */
 166 #define ATMEL_PMC_UHP           AT91SAM926x_PMC_UHP
 167 #define ATMEL_ID_UHP            ATMEL_ID_UHPHS
 168
 169 /*
 170  * PMECC table in ROM
 171  */
 172 #define ATMEL_PMECC_INDEX_OFFSET_512    0x8000
 173 #define ATMEL_PMECC_INDEX_OFFSET_1024   0x10000
 174
 175 /*
 176  * at91sam9x5 specific prototypes
 177  */
 178 #ifndef __ASSEMBLY__
 179 unsigned int get_chip_id(void);
 180 unsigned int get_extension_chip_id(void);
 181 unsigned int has_emac1(void);
 182 unsigned int has_emac0(void);
 183 unsigned int has_lcdc(void);
 184 char *get_cpu_name(void);
 185 #endif
 186
 187 #endif