arch/arm/mach-at91/include/mach/sama5d2_smc.h

   1 /*
   2  * Copyright (C) 2017 Microchip Corporation.
   3  *
   4  * Static Memory Controllers (SMC) - System peripherals registers.
   5  * Based on SAMA5D2 datasheet.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef SAMA5D2_SMC_H
  11 #define SAMA5D2_SMC_H
  12
  13 #ifdef __ASSEMBLY__
  14 #define AT91_ASM_SMC_SETUP0     (ATMEL_BASE_SMC + 0x700)
  15 #define AT91_ASM_SMC_PULSE0     (ATMEL_BASE_SMC + 0x704)
  16 #define AT91_ASM_SMC_CYCLE0     (ATMEL_BASE_SMC + 0x708)
  17 #define AT91_ASM_SMC_TIMINGS0   (ATMEL_BASE_SMC + 0x70c)
  18 #define AT91_ASM_SMC_MODE0      (ATMEL_BASE_SMC + 0x710)
  19 #else
  20 struct at91_cs {
  21         u32     setup;          /* 0x600 SMC Setup Register */
  22         u32     pulse;          /* 0x604 SMC Pulse Register */
  23         u32     cycle;          /* 0x608 SMC Cycle Register */
  24         u32     timings;        /* 0x60C SMC Cycle Register */
  25         u32     mode;           /* 0x610 SMC Mode Register */
  26 };
  27
  28 struct at91_smc {
  29         struct at91_cs cs[4];
  30 };
  31 #endif /*  __ASSEMBLY__ */
  32
  33 #define AT91_SMC_SETUP_NWE(x)           (x & 0x3f)
  34 #define AT91_SMC_SETUP_NCS_WR(x)        ((x & 0x3f) << 8)
  35 #define AT91_SMC_SETUP_NRD(x)           ((x & 0x3f) << 16)
  36 #define AT91_SMC_SETUP_NCS_RD(x)        ((x & 0x3f) << 24)
  37
  38 #define AT91_SMC_PULSE_NWE(x)           (x & 0x7f)
  39 #define AT91_SMC_PULSE_NCS_WR(x)        ((x & 0x7f) << 8)
  40 #define AT91_SMC_PULSE_NRD(x)           ((x & 0x7f) << 16)
  41 #define AT91_SMC_PULSE_NCS_RD(x)        ((x & 0x7f) << 24)
  42
  43 #define AT91_SMC_CYCLE_NWE(x)           (x & 0x1ff)
  44 #define AT91_SMC_CYCLE_NRD(x)           ((x & 0x1ff) << 16)
  45
  46 #define AT91_SMC_TIMINGS_TCLR(x)        (x & 0xf)
  47 #define AT91_SMC_TIMINGS_TADL(x)        ((x & 0xf) << 4)
  48 #define AT91_SMC_TIMINGS_TAR(x)         ((x & 0xf) << 8)
  49 #define AT91_SMC_TIMINGS_OCMS(x)        ((x & 0x1) << 12)
  50 #define AT91_SMC_TIMINGS_TRR(x)         ((x & 0xf) << 16)
  51 #define AT91_SMC_TIMINGS_TWB(x)         ((x & 0xf) << 24)
  52 #define AT91_SMC_TIMINGS_RBNSEL(x)      ((x & 0xf) << 28)
  53 #define AT91_SMC_TIMINGS_NFSEL(x)       ((x & 0x1) << 31)
  54
  55 #define AT91_SMC_MODE_RM_NCS            0x00000000
  56 #define AT91_SMC_MODE_RM_NRD            0x00000001
  57 #define AT91_SMC_MODE_WM_NCS            0x00000000
  58 #define AT91_SMC_MODE_WM_NWE            0x00000002
  59
  60 #define AT91_SMC_MODE_EXNW_DISABLE      0x00000000
  61 #define AT91_SMC_MODE_EXNW_FROZEN       0x00000020
  62 #define AT91_SMC_MODE_EXNW_READY        0x00000030
  63
  64 #define AT91_SMC_MODE_BAT               0x00000100
  65 #define AT91_SMC_MODE_DBW_8             0x00000000
  66 #define AT91_SMC_MODE_DBW_16            0x00001000
  67 #define AT91_SMC_MODE_DBW_32            0x00002000
  68 #define AT91_SMC_MODE_TDF_CYCLE(x)      ((x & 0xf) << 16)
  69 #define AT91_SMC_MODE_TDF               0x00100000
  70 #define AT91_SMC_MODE_PMEN              0x01000000
  71 #define AT91_SMC_MODE_PS_4              0x00000000
  72 #define AT91_SMC_MODE_PS_8              0x10000000
  73 #define AT91_SMC_MODE_PS_16             0x20000000
  74 #define AT91_SMC_MODE_PS_32             0x30000000
  75
  76 #endif