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[thirdparty/linux.git] / arch / arm / mach-davinci / da850.c
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15 #include <linux/clk-provider.h>
16 #include <linux/clk/davinci.h>
17 #include <linux/clkdev.h>
18 #include <linux/cpufreq.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/mfd/da8xx-cfgchip.h>
22 #include <linux/platform_data/clk-da8xx-cfgchip.h>
23 #include <linux/platform_data/clk-davinci-pll.h>
24 #include <linux/platform_data/gpio-davinci.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28
29 #include <asm/mach/map.h>
30
31 #include <mach/common.h>
32 #include <mach/cpufreq.h>
33 #include <mach/cputype.h>
34 #include <mach/da8xx.h>
35 #include <mach/irqs.h>
36 #include <mach/pm.h>
37 #include <mach/time.h>
38
39 #include "mux.h"
40
41 #define DA850_PLL1_BASE 0x01e1a000
42 #define DA850_TIMER64P2_BASE 0x01f0c000
43 #define DA850_TIMER64P3_BASE 0x01f0d000
44
45 #define DA850_REF_FREQ 24000000
46
47 /*
48 * Device specific mux setup
49 *
50 * soc description mux mode mode mux dbg
51 * reg offset mask mode
52 */
53 static const struct mux_config da850_pins[] = {
54 #ifdef CONFIG_DAVINCI_MUX
55 /* UART0 function */
56 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
57 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
58 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
59 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
60 /* UART1 function */
61 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
62 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
63 /* UART2 function */
64 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
65 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
66 /* I2C1 function */
67 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
68 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
69 /* I2C0 function */
70 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
71 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
72 /* EMAC function */
73 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
74 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
75 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
76 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
77 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
78 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
79 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
80 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
81 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
82 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
83 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
84 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
85 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
86 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
87 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
88 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
89 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
90 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
91 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
92 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
93 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
94 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
95 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
96 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
97 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
98 /* McASP function */
99 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
100 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
101 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
102 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
103 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
104 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
105 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
106 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
107 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
108 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
109 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
110 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
111 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
112 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
113 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
114 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
115 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
116 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
117 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
118 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
119 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
120 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
121 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
122 /* LCD function */
123 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
124 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
125 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
126 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
127 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
128 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
129 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
130 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
131 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
132 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
133 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
134 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
135 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
136 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
137 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
138 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
139 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
140 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
141 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
142 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
143 /* MMC/SD0 function */
144 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
145 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
146 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
147 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
148 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
149 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
150 /* MMC/SD1 function */
151 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
152 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
153 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
154 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
155 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
156 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
157 /* EMIF2.5/EMIFA function */
158 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
159 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
160 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
161 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
162 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
163 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
164 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
165 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
166 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
167 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
168 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
169 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
170 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
171 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
172 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
173 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
174 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
175 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
176 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
177 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
178 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
179 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
180 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
181 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
182 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
183 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
184 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
185 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
186 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
187 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
188 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
189 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
190 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
191 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
192 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
193 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
194 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
195 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
196 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
197 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
198 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
199 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
200 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
201 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
202 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
203 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
204 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
205 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
206 /* GPIO function */
207 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
208 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
209 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
210 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
211 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
212 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
213 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
214 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
215 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
216 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
217 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
218 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
219 /* VPIF Capture */
220 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
221 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
222 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
223 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
224 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
225 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
226 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
227 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
228 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
229 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
230 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
231 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
232 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
233 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
234 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
235 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
236 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
237 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
238 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
239 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
240 /* VPIF Display */
241 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
242 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
243 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
244 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
245 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
246 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
247 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
248 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
249 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
250 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
251 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
252 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
253 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
254 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
255 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
256 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
257 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
258 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
259 #endif
260 };
261
262 const short da850_i2c0_pins[] __initconst = {
263 DA850_I2C0_SDA, DA850_I2C0_SCL,
264 -1
265 };
266
267 const short da850_i2c1_pins[] __initconst = {
268 DA850_I2C1_SCL, DA850_I2C1_SDA,
269 -1
270 };
271
272 const short da850_lcdcntl_pins[] __initconst = {
273 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
274 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
275 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
276 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
277 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
278 -1
279 };
280
281 const short da850_vpif_capture_pins[] __initconst = {
282 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
283 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
284 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
285 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
286 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
287 DA850_VPIF_CLKIN3,
288 -1
289 };
290
291 const short da850_vpif_display_pins[] __initconst = {
292 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
293 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
294 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
295 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
296 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
297 DA850_VPIF_CLKO3,
298 -1
299 };
300
301 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
302 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
303 [IRQ_DA8XX_COMMTX] = 7,
304 [IRQ_DA8XX_COMMRX] = 7,
305 [IRQ_DA8XX_NINT] = 7,
306 [IRQ_DA8XX_EVTOUT0] = 7,
307 [IRQ_DA8XX_EVTOUT1] = 7,
308 [IRQ_DA8XX_EVTOUT2] = 7,
309 [IRQ_DA8XX_EVTOUT3] = 7,
310 [IRQ_DA8XX_EVTOUT4] = 7,
311 [IRQ_DA8XX_EVTOUT5] = 7,
312 [IRQ_DA8XX_EVTOUT6] = 7,
313 [IRQ_DA8XX_EVTOUT7] = 7,
314 [IRQ_DA8XX_CCINT0] = 7,
315 [IRQ_DA8XX_CCERRINT] = 7,
316 [IRQ_DA8XX_TCERRINT0] = 7,
317 [IRQ_DA8XX_AEMIFINT] = 7,
318 [IRQ_DA8XX_I2CINT0] = 7,
319 [IRQ_DA8XX_MMCSDINT0] = 7,
320 [IRQ_DA8XX_MMCSDINT1] = 7,
321 [IRQ_DA8XX_ALLINT0] = 7,
322 [IRQ_DA8XX_RTC] = 7,
323 [IRQ_DA8XX_SPINT0] = 7,
324 [IRQ_DA8XX_TINT12_0] = 7,
325 [IRQ_DA8XX_TINT34_0] = 7,
326 [IRQ_DA8XX_TINT12_1] = 7,
327 [IRQ_DA8XX_TINT34_1] = 7,
328 [IRQ_DA8XX_UARTINT0] = 7,
329 [IRQ_DA8XX_KEYMGRINT] = 7,
330 [IRQ_DA850_MPUADDRERR0] = 7,
331 [IRQ_DA8XX_CHIPINT0] = 7,
332 [IRQ_DA8XX_CHIPINT1] = 7,
333 [IRQ_DA8XX_CHIPINT2] = 7,
334 [IRQ_DA8XX_CHIPINT3] = 7,
335 [IRQ_DA8XX_TCERRINT1] = 7,
336 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
337 [IRQ_DA8XX_C0_RX_PULSE] = 7,
338 [IRQ_DA8XX_C0_TX_PULSE] = 7,
339 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
340 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
341 [IRQ_DA8XX_C1_RX_PULSE] = 7,
342 [IRQ_DA8XX_C1_TX_PULSE] = 7,
343 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
344 [IRQ_DA8XX_MEMERR] = 7,
345 [IRQ_DA8XX_GPIO0] = 7,
346 [IRQ_DA8XX_GPIO1] = 7,
347 [IRQ_DA8XX_GPIO2] = 7,
348 [IRQ_DA8XX_GPIO3] = 7,
349 [IRQ_DA8XX_GPIO4] = 7,
350 [IRQ_DA8XX_GPIO5] = 7,
351 [IRQ_DA8XX_GPIO6] = 7,
352 [IRQ_DA8XX_GPIO7] = 7,
353 [IRQ_DA8XX_GPIO8] = 7,
354 [IRQ_DA8XX_I2CINT1] = 7,
355 [IRQ_DA8XX_LCDINT] = 7,
356 [IRQ_DA8XX_UARTINT1] = 7,
357 [IRQ_DA8XX_MCASPINT] = 7,
358 [IRQ_DA8XX_ALLINT1] = 7,
359 [IRQ_DA8XX_SPINT1] = 7,
360 [IRQ_DA8XX_UHPI_INT1] = 7,
361 [IRQ_DA8XX_USB_INT] = 7,
362 [IRQ_DA8XX_IRQN] = 7,
363 [IRQ_DA8XX_RWAKEUP] = 7,
364 [IRQ_DA8XX_UARTINT2] = 7,
365 [IRQ_DA8XX_DFTSSINT] = 7,
366 [IRQ_DA8XX_EHRPWM0] = 7,
367 [IRQ_DA8XX_EHRPWM0TZ] = 7,
368 [IRQ_DA8XX_EHRPWM1] = 7,
369 [IRQ_DA8XX_EHRPWM1TZ] = 7,
370 [IRQ_DA850_SATAINT] = 7,
371 [IRQ_DA850_TINTALL_2] = 7,
372 [IRQ_DA8XX_ECAP0] = 7,
373 [IRQ_DA8XX_ECAP1] = 7,
374 [IRQ_DA8XX_ECAP2] = 7,
375 [IRQ_DA850_MMCSDINT0_1] = 7,
376 [IRQ_DA850_MMCSDINT1_1] = 7,
377 [IRQ_DA850_T12CMPINT0_2] = 7,
378 [IRQ_DA850_T12CMPINT1_2] = 7,
379 [IRQ_DA850_T12CMPINT2_2] = 7,
380 [IRQ_DA850_T12CMPINT3_2] = 7,
381 [IRQ_DA850_T12CMPINT4_2] = 7,
382 [IRQ_DA850_T12CMPINT5_2] = 7,
383 [IRQ_DA850_T12CMPINT6_2] = 7,
384 [IRQ_DA850_T12CMPINT7_2] = 7,
385 [IRQ_DA850_T12CMPINT0_3] = 7,
386 [IRQ_DA850_T12CMPINT1_3] = 7,
387 [IRQ_DA850_T12CMPINT2_3] = 7,
388 [IRQ_DA850_T12CMPINT3_3] = 7,
389 [IRQ_DA850_T12CMPINT4_3] = 7,
390 [IRQ_DA850_T12CMPINT5_3] = 7,
391 [IRQ_DA850_T12CMPINT6_3] = 7,
392 [IRQ_DA850_T12CMPINT7_3] = 7,
393 [IRQ_DA850_RPIINT] = 7,
394 [IRQ_DA850_VPIFINT] = 7,
395 [IRQ_DA850_CCINT1] = 7,
396 [IRQ_DA850_CCERRINT1] = 7,
397 [IRQ_DA850_TCERRINT2] = 7,
398 [IRQ_DA850_TINTALL_3] = 7,
399 [IRQ_DA850_MCBSP0RINT] = 7,
400 [IRQ_DA850_MCBSP0XINT] = 7,
401 [IRQ_DA850_MCBSP1RINT] = 7,
402 [IRQ_DA850_MCBSP1XINT] = 7,
403 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
404 };
405
406 static struct map_desc da850_io_desc[] = {
407 {
408 .virtual = IO_VIRT,
409 .pfn = __phys_to_pfn(IO_PHYS),
410 .length = IO_SIZE,
411 .type = MT_DEVICE
412 },
413 {
414 .virtual = DA8XX_CP_INTC_VIRT,
415 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
416 .length = DA8XX_CP_INTC_SIZE,
417 .type = MT_DEVICE
418 },
419 };
420
421 /* Contents of JTAG ID register used to identify exact cpu type */
422 static struct davinci_id da850_ids[] = {
423 {
424 .variant = 0x0,
425 .part_no = 0xb7d1,
426 .manufacturer = 0x017, /* 0x02f >> 1 */
427 .cpu_id = DAVINCI_CPU_ID_DA850,
428 .name = "da850/omap-l138",
429 },
430 {
431 .variant = 0x1,
432 .part_no = 0xb7d1,
433 .manufacturer = 0x017, /* 0x02f >> 1 */
434 .cpu_id = DAVINCI_CPU_ID_DA850,
435 .name = "da850/omap-l138/am18x",
436 },
437 };
438
439 static struct davinci_timer_instance da850_timer_instance[4] = {
440 {
441 .base = DA8XX_TIMER64P0_BASE,
442 .bottom_irq = IRQ_DA8XX_TINT12_0,
443 .top_irq = IRQ_DA8XX_TINT34_0,
444 },
445 {
446 .base = DA8XX_TIMER64P1_BASE,
447 .bottom_irq = IRQ_DA8XX_TINT12_1,
448 .top_irq = IRQ_DA8XX_TINT34_1,
449 },
450 {
451 .base = DA850_TIMER64P2_BASE,
452 .bottom_irq = IRQ_DA850_TINT12_2,
453 .top_irq = IRQ_DA850_TINT34_2,
454 },
455 {
456 .base = DA850_TIMER64P3_BASE,
457 .bottom_irq = IRQ_DA850_TINT12_3,
458 .top_irq = IRQ_DA850_TINT34_3,
459 },
460 };
461
462 /*
463 * T0_BOT: Timer 0, bottom : Used for clock_event
464 * T0_TOP: Timer 0, top : Used for clocksource
465 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
466 */
467 static struct davinci_timer_info da850_timer_info = {
468 .timers = da850_timer_instance,
469 .clockevent_id = T0_BOT,
470 .clocksource_id = T0_TOP,
471 };
472
473 #ifdef CONFIG_CPU_FREQ
474 /*
475 * Notes:
476 * According to the TRM, minimum PLLM results in maximum power savings.
477 * The OPP definitions below should keep the PLLM as low as possible.
478 *
479 * The output of the PLLM must be between 300 to 600 MHz.
480 */
481 struct da850_opp {
482 unsigned int freq; /* in KHz */
483 unsigned int prediv;
484 unsigned int mult;
485 unsigned int postdiv;
486 unsigned int cvdd_min; /* in uV */
487 unsigned int cvdd_max; /* in uV */
488 };
489
490 static const struct da850_opp da850_opp_456 = {
491 .freq = 456000,
492 .prediv = 1,
493 .mult = 19,
494 .postdiv = 1,
495 .cvdd_min = 1300000,
496 .cvdd_max = 1350000,
497 };
498
499 static const struct da850_opp da850_opp_408 = {
500 .freq = 408000,
501 .prediv = 1,
502 .mult = 17,
503 .postdiv = 1,
504 .cvdd_min = 1300000,
505 .cvdd_max = 1350000,
506 };
507
508 static const struct da850_opp da850_opp_372 = {
509 .freq = 372000,
510 .prediv = 2,
511 .mult = 31,
512 .postdiv = 1,
513 .cvdd_min = 1200000,
514 .cvdd_max = 1320000,
515 };
516
517 static const struct da850_opp da850_opp_300 = {
518 .freq = 300000,
519 .prediv = 1,
520 .mult = 25,
521 .postdiv = 2,
522 .cvdd_min = 1200000,
523 .cvdd_max = 1320000,
524 };
525
526 static const struct da850_opp da850_opp_200 = {
527 .freq = 200000,
528 .prediv = 1,
529 .mult = 25,
530 .postdiv = 3,
531 .cvdd_min = 1100000,
532 .cvdd_max = 1160000,
533 };
534
535 static const struct da850_opp da850_opp_96 = {
536 .freq = 96000,
537 .prediv = 1,
538 .mult = 20,
539 .postdiv = 5,
540 .cvdd_min = 1000000,
541 .cvdd_max = 1050000,
542 };
543
544 #define OPP(freq) \
545 { \
546 .driver_data = (unsigned int) &da850_opp_##freq, \
547 .frequency = freq * 1000, \
548 }
549
550 static struct cpufreq_frequency_table da850_freq_table[] = {
551 OPP(456),
552 OPP(408),
553 OPP(372),
554 OPP(300),
555 OPP(200),
556 OPP(96),
557 {
558 .driver_data = 0,
559 .frequency = CPUFREQ_TABLE_END,
560 },
561 };
562
563 #ifdef CONFIG_REGULATOR
564 static int da850_set_voltage(unsigned int index);
565 static int da850_regulator_init(void);
566 #endif
567
568 static struct davinci_cpufreq_config cpufreq_info = {
569 .freq_table = da850_freq_table,
570 #ifdef CONFIG_REGULATOR
571 .init = da850_regulator_init,
572 .set_voltage = da850_set_voltage,
573 #endif
574 };
575
576 #ifdef CONFIG_REGULATOR
577 static struct regulator *cvdd;
578
579 static int da850_set_voltage(unsigned int index)
580 {
581 struct da850_opp *opp;
582
583 if (!cvdd)
584 return -ENODEV;
585
586 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
587
588 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
589 }
590
591 static int da850_regulator_init(void)
592 {
593 cvdd = regulator_get(NULL, "cvdd");
594 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
595 " voltage scaling unsupported\n")) {
596 return PTR_ERR(cvdd);
597 }
598
599 return 0;
600 }
601 #endif
602
603 static struct platform_device da850_cpufreq_device = {
604 .name = "cpufreq-davinci",
605 .dev = {
606 .platform_data = &cpufreq_info,
607 },
608 .id = -1,
609 };
610
611 unsigned int da850_max_speed = 300000;
612
613 int da850_register_cpufreq(char *async_clk)
614 {
615 int i;
616
617 /* cpufreq driver can help keep an "async" clock constant */
618 if (async_clk)
619 clk_add_alias("async", da850_cpufreq_device.name,
620 async_clk, NULL);
621 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
622 if (da850_freq_table[i].frequency <= da850_max_speed) {
623 cpufreq_info.freq_table = &da850_freq_table[i];
624 break;
625 }
626 }
627
628 return platform_device_register(&da850_cpufreq_device);
629 }
630 #else
631 int __init da850_register_cpufreq(char *async_clk)
632 {
633 return 0;
634 }
635 #endif
636
637 /* VPIF resource, platform data */
638 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
639
640 static struct resource da850_vpif_resource[] = {
641 {
642 .start = DA8XX_VPIF_BASE,
643 .end = DA8XX_VPIF_BASE + 0xfff,
644 .flags = IORESOURCE_MEM,
645 }
646 };
647
648 static struct platform_device da850_vpif_dev = {
649 .name = "vpif",
650 .id = -1,
651 .dev = {
652 .dma_mask = &da850_vpif_dma_mask,
653 .coherent_dma_mask = DMA_BIT_MASK(32),
654 },
655 .resource = da850_vpif_resource,
656 .num_resources = ARRAY_SIZE(da850_vpif_resource),
657 };
658
659 static struct resource da850_vpif_display_resource[] = {
660 {
661 .start = IRQ_DA850_VPIFINT,
662 .end = IRQ_DA850_VPIFINT,
663 .flags = IORESOURCE_IRQ,
664 },
665 };
666
667 static struct platform_device da850_vpif_display_dev = {
668 .name = "vpif_display",
669 .id = -1,
670 .dev = {
671 .dma_mask = &da850_vpif_dma_mask,
672 .coherent_dma_mask = DMA_BIT_MASK(32),
673 },
674 .resource = da850_vpif_display_resource,
675 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
676 };
677
678 static struct resource da850_vpif_capture_resource[] = {
679 {
680 .start = IRQ_DA850_VPIFINT,
681 .end = IRQ_DA850_VPIFINT,
682 .flags = IORESOURCE_IRQ,
683 },
684 {
685 .start = IRQ_DA850_VPIFINT,
686 .end = IRQ_DA850_VPIFINT,
687 .flags = IORESOURCE_IRQ,
688 },
689 };
690
691 static struct platform_device da850_vpif_capture_dev = {
692 .name = "vpif_capture",
693 .id = -1,
694 .dev = {
695 .dma_mask = &da850_vpif_dma_mask,
696 .coherent_dma_mask = DMA_BIT_MASK(32),
697 },
698 .resource = da850_vpif_capture_resource,
699 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
700 };
701
702 int __init da850_register_vpif(void)
703 {
704 return platform_device_register(&da850_vpif_dev);
705 }
706
707 int __init da850_register_vpif_display(struct vpif_display_config
708 *display_config)
709 {
710 da850_vpif_display_dev.dev.platform_data = display_config;
711 return platform_device_register(&da850_vpif_display_dev);
712 }
713
714 int __init da850_register_vpif_capture(struct vpif_capture_config
715 *capture_config)
716 {
717 da850_vpif_capture_dev.dev.platform_data = capture_config;
718 return platform_device_register(&da850_vpif_capture_dev);
719 }
720
721 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
722 .no_auto_base = true,
723 .base = 0,
724 .ngpio = 144,
725 };
726
727 int __init da850_register_gpio(void)
728 {
729 return da8xx_register_gpio(&da850_gpio_platform_data);
730 }
731
732 static const struct davinci_soc_info davinci_soc_info_da850 = {
733 .io_desc = da850_io_desc,
734 .io_desc_num = ARRAY_SIZE(da850_io_desc),
735 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
736 .ids = da850_ids,
737 .ids_num = ARRAY_SIZE(da850_ids),
738 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
739 .pinmux_pins = da850_pins,
740 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
741 .intc_base = DA8XX_CP_INTC_BASE,
742 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
743 .intc_irq_prios = da850_default_priorities,
744 .intc_irq_num = DA850_N_CP_INTC_IRQ,
745 .timer_info = &da850_timer_info,
746 .emac_pdata = &da8xx_emac_pdata,
747 .sram_dma = DA8XX_SHARED_RAM_BASE,
748 .sram_len = SZ_128K,
749 };
750
751 void __init da850_init(void)
752 {
753 davinci_common_init(&davinci_soc_info_da850);
754
755 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
756 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
757 return;
758
759 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
760 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
761 }
762
763 void __init da850_init_time(void)
764 {
765 void __iomem *pll0;
766 struct regmap *cfgchip;
767 struct clk *clk;
768
769 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
770
771 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
772 cfgchip = da8xx_get_cfgchip();
773
774 da850_pll0_init(NULL, pll0, cfgchip);
775
776 clk = clk_get(NULL, "timer0");
777
778 davinci_timer_init(clk);
779 }
780
781 static struct resource da850_pll1_resources[] = {
782 {
783 .start = DA850_PLL1_BASE,
784 .end = DA850_PLL1_BASE + SZ_4K - 1,
785 .flags = IORESOURCE_MEM,
786 },
787 };
788
789 static struct davinci_pll_platform_data da850_pll1_pdata;
790
791 static struct platform_device da850_pll1_device = {
792 .name = "da850-pll1",
793 .id = -1,
794 .resource = da850_pll1_resources,
795 .num_resources = ARRAY_SIZE(da850_pll1_resources),
796 .dev = {
797 .platform_data = &da850_pll1_pdata,
798 },
799 };
800
801 static struct resource da850_psc0_resources[] = {
802 {
803 .start = DA8XX_PSC0_BASE,
804 .end = DA8XX_PSC0_BASE + SZ_4K - 1,
805 .flags = IORESOURCE_MEM,
806 },
807 };
808
809 static struct platform_device da850_psc0_device = {
810 .name = "da850-psc0",
811 .id = -1,
812 .resource = da850_psc0_resources,
813 .num_resources = ARRAY_SIZE(da850_psc0_resources),
814 };
815
816 static struct resource da850_psc1_resources[] = {
817 {
818 .start = DA8XX_PSC1_BASE,
819 .end = DA8XX_PSC1_BASE + SZ_4K - 1,
820 .flags = IORESOURCE_MEM,
821 },
822 };
823
824 static struct platform_device da850_psc1_device = {
825 .name = "da850-psc1",
826 .id = -1,
827 .resource = da850_psc1_resources,
828 .num_resources = ARRAY_SIZE(da850_psc1_resources),
829 };
830
831 static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
832
833 static struct platform_device da850_async1_clksrc_device = {
834 .name = "da850-async1-clksrc",
835 .id = -1,
836 .dev = {
837 .platform_data = &da850_async1_pdata,
838 },
839 };
840
841 static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
842
843 static struct platform_device da850_async3_clksrc_device = {
844 .name = "da850-async3-clksrc",
845 .id = -1,
846 .dev = {
847 .platform_data = &da850_async3_pdata,
848 },
849 };
850
851 static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
852
853 static struct platform_device da850_tbclksync_device = {
854 .name = "da830-tbclksync",
855 .id = -1,
856 .dev = {
857 .platform_data = &da850_tbclksync_pdata,
858 },
859 };
860
861 void __init da850_register_clocks(void)
862 {
863 /* PLL0 is registered in da850_init_time() */
864
865 da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
866 platform_device_register(&da850_pll1_device);
867
868 da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
869 platform_device_register(&da850_async1_clksrc_device);
870
871 da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
872 platform_device_register(&da850_async3_clksrc_device);
873
874 platform_device_register(&da850_psc0_device);
875
876 platform_device_register(&da850_psc1_device);
877
878 da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
879 platform_device_register(&da850_tbclksync_device);
880 }
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