2 * Copyright 2015 Toradex, Inc.
5 * Copyright 2013 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux-vf610.h>
13 #include <asm/arch/ddrmc-vf610.h>
15 void ddrmc_setup_iomux(const iomux_v3_cfg_t
*pads
, int pads_count
)
17 static const iomux_v3_cfg_t default_pads
[] = {
18 VF610_PAD_DDR_A15__DDR_A_15
,
19 VF610_PAD_DDR_A14__DDR_A_14
,
20 VF610_PAD_DDR_A13__DDR_A_13
,
21 VF610_PAD_DDR_A12__DDR_A_12
,
22 VF610_PAD_DDR_A11__DDR_A_11
,
23 VF610_PAD_DDR_A10__DDR_A_10
,
24 VF610_PAD_DDR_A9__DDR_A_9
,
25 VF610_PAD_DDR_A8__DDR_A_8
,
26 VF610_PAD_DDR_A7__DDR_A_7
,
27 VF610_PAD_DDR_A6__DDR_A_6
,
28 VF610_PAD_DDR_A5__DDR_A_5
,
29 VF610_PAD_DDR_A4__DDR_A_4
,
30 VF610_PAD_DDR_A3__DDR_A_3
,
31 VF610_PAD_DDR_A2__DDR_A_2
,
32 VF610_PAD_DDR_A1__DDR_A_1
,
33 VF610_PAD_DDR_A0__DDR_A_0
,
34 VF610_PAD_DDR_BA2__DDR_BA_2
,
35 VF610_PAD_DDR_BA1__DDR_BA_1
,
36 VF610_PAD_DDR_BA0__DDR_BA_0
,
37 VF610_PAD_DDR_CAS__DDR_CAS_B
,
38 VF610_PAD_DDR_CKE__DDR_CKE_0
,
39 VF610_PAD_DDR_CLK__DDR_CLK_0
,
40 VF610_PAD_DDR_CS__DDR_CS_B_0
,
41 VF610_PAD_DDR_D15__DDR_D_15
,
42 VF610_PAD_DDR_D14__DDR_D_14
,
43 VF610_PAD_DDR_D13__DDR_D_13
,
44 VF610_PAD_DDR_D12__DDR_D_12
,
45 VF610_PAD_DDR_D11__DDR_D_11
,
46 VF610_PAD_DDR_D10__DDR_D_10
,
47 VF610_PAD_DDR_D9__DDR_D_9
,
48 VF610_PAD_DDR_D8__DDR_D_8
,
49 VF610_PAD_DDR_D7__DDR_D_7
,
50 VF610_PAD_DDR_D6__DDR_D_6
,
51 VF610_PAD_DDR_D5__DDR_D_5
,
52 VF610_PAD_DDR_D4__DDR_D_4
,
53 VF610_PAD_DDR_D3__DDR_D_3
,
54 VF610_PAD_DDR_D2__DDR_D_2
,
55 VF610_PAD_DDR_D1__DDR_D_1
,
56 VF610_PAD_DDR_D0__DDR_D_0
,
57 VF610_PAD_DDR_DQM1__DDR_DQM_1
,
58 VF610_PAD_DDR_DQM0__DDR_DQM_0
,
59 VF610_PAD_DDR_DQS1__DDR_DQS_1
,
60 VF610_PAD_DDR_DQS0__DDR_DQS_0
,
61 VF610_PAD_DDR_RAS__DDR_RAS_B
,
62 VF610_PAD_DDR_WE__DDR_WE_B
,
63 VF610_PAD_DDR_ODT1__DDR_ODT_0
,
64 VF610_PAD_DDR_ODT0__DDR_ODT_1
,
68 if ((pads
== NULL
) || (pads_count
== 0)) {
70 pads_count
= ARRAY_SIZE(default_pads
);
73 imx_iomux_v3_setup_multiple_pads(pads
, pads_count
);
76 static struct ddrmc_phy_setting default_phy_settings
[] = {
77 { DDRMC_PHY_DQ_TIMING
, 0 },
78 { DDRMC_PHY_DQ_TIMING
, 16 },
79 { DDRMC_PHY_DQ_TIMING
, 32 },
81 { DDRMC_PHY_DQS_TIMING
, 1 },
82 { DDRMC_PHY_DQS_TIMING
, 17 },
84 { DDRMC_PHY_CTRL
, 2 },
85 { DDRMC_PHY_CTRL
, 18 },
86 { DDRMC_PHY_CTRL
, 34 },
88 { DDRMC_PHY_MASTER_CTRL
, 3 },
89 { DDRMC_PHY_MASTER_CTRL
, 19 },
90 { DDRMC_PHY_MASTER_CTRL
, 35 },
92 { DDRMC_PHY_SLAVE_CTRL
, 4 },
93 { DDRMC_PHY_SLAVE_CTRL
, 20 },
94 { DDRMC_PHY_SLAVE_CTRL
, 36 },
96 /* LPDDR2 only parameter */
97 { DDRMC_PHY_OFF
, 49 },
99 { DDRMC_PHY50_DDR3_MODE
| DDRMC_PHY50_EN_SW_HALF_CYCLE
, 50 },
101 /* Processor Pad ODT settings */
102 { DDRMC_PHY_PROC_PAD_ODT
, 52 },
108 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings
const *timings
,
109 struct ddrmc_cr_setting
*board_cr_settings
,
110 struct ddrmc_phy_setting
*board_phy_settings
,
111 int col_diff
, int row_diff
)
113 struct ddrmr_regs
*ddrmr
= (struct ddrmr_regs
*)DDR_BASE_ADDR
;
114 struct ddrmc_cr_setting
*cr_setting
;
115 struct ddrmc_phy_setting
*phy_setting
;
117 writel(DDRMC_CR00_DRAM_CLASS_DDR3
, &ddrmr
->cr
[0]);
118 writel(DDRMC_CR02_DRAM_TINIT(timings
->tinit
), &ddrmr
->cr
[2]);
119 writel(DDRMC_CR10_TRST_PWRON(timings
->trst_pwron
), &ddrmr
->cr
[10]);
121 writel(DDRMC_CR11_CKE_INACTIVE(timings
->cke_inactive
), &ddrmr
->cr
[11]);
122 writel(DDRMC_CR12_WRLAT(timings
->wrlat
) |
123 DDRMC_CR12_CASLAT_LIN(timings
->caslat_lin
), &ddrmr
->cr
[12]);
124 writel(DDRMC_CR13_TRC(timings
->trc
) | DDRMC_CR13_TRRD(timings
->trrd
) |
125 DDRMC_CR13_TCCD(timings
->tccd
) |
126 DDRMC_CR13_TBST_INT_INTERVAL(timings
->tbst_int_interval
),
128 writel(DDRMC_CR14_TFAW(timings
->tfaw
) | DDRMC_CR14_TRP(timings
->trp
) |
129 DDRMC_CR14_TWTR(timings
->twtr
) |
130 DDRMC_CR14_TRAS_MIN(timings
->tras_min
), &ddrmr
->cr
[14]);
131 writel(DDRMC_CR16_TMRD(timings
->tmrd
) |
132 DDRMC_CR16_TRTP(timings
->trtp
), &ddrmr
->cr
[16]);
133 writel(DDRMC_CR17_TRAS_MAX(timings
->tras_max
) |
134 DDRMC_CR17_TMOD(timings
->tmod
), &ddrmr
->cr
[17]);
135 writel(DDRMC_CR18_TCKESR(timings
->tckesr
) |
136 DDRMC_CR18_TCKE(timings
->tcke
), &ddrmr
->cr
[18]);
138 writel(DDRMC_CR20_AP_EN
, &ddrmr
->cr
[20]);
139 writel(DDRMC_CR21_TRCD_INT(timings
->trcd_int
) | DDRMC_CR21_CCMAP_EN
|
140 DDRMC_CR21_TRAS_LOCKOUT(timings
->tras_lockout
),
143 writel(DDRMC_CR22_TDAL(timings
->tdal
), &ddrmr
->cr
[22]);
144 writel(DDRMC_CR23_BSTLEN(timings
->bstlen
) |
145 DDRMC_CR23_TDLL(timings
->tdll
), &ddrmr
->cr
[23]);
146 writel(DDRMC_CR24_TRP_AB(timings
->trp_ab
), &ddrmr
->cr
[24]);
148 writel(DDRMC_CR25_TREF_EN
, &ddrmr
->cr
[25]);
149 writel(DDRMC_CR26_TREF(timings
->tref
) |
150 DDRMC_CR26_TRFC(timings
->trfc
), &ddrmr
->cr
[26]);
151 writel(DDRMC_CR28_TREF_INT(timings
->tref_int
), &ddrmr
->cr
[28]);
152 writel(DDRMC_CR29_TPDEX(timings
->tpdex
), &ddrmr
->cr
[29]);
154 writel(DDRMC_CR30_TXPDLL(timings
->txpdll
), &ddrmr
->cr
[30]);
155 writel(DDRMC_CR31_TXSNR(timings
->txsnr
) |
156 DDRMC_CR31_TXSR(timings
->txsr
), &ddrmr
->cr
[31]);
157 writel(DDRMC_CR33_EN_QK_SREF
, &ddrmr
->cr
[33]);
158 writel(DDRMC_CR34_CKSRX(timings
->cksrx
) |
159 DDRMC_CR34_CKSRE(timings
->cksre
), &ddrmr
->cr
[34]);
161 writel(DDRMC_CR38_FREQ_CHG_EN(timings
->freq_chg_en
), &ddrmr
->cr
[38]);
162 writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
163 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr
->cr
[39]);
165 writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS
, &ddrmr
->cr
[41]);
166 writel(DDRMC_CR48_MR1_DA_0(70) |
167 DDRMC_CR48_MR0_DA_0(1056), &ddrmr
->cr
[48]);
169 writel(DDRMC_CR66_ZQCL(timings
->zqcl
) |
170 DDRMC_CR66_ZQINIT(timings
->zqinit
), &ddrmr
->cr
[66]);
171 writel(DDRMC_CR67_ZQCS(timings
->zqcs
), &ddrmr
->cr
[67]);
172 writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr
->cr
[69]);
174 writel(DDRMC_CR70_REF_PER_ZQ(timings
->ref_per_zq
), &ddrmr
->cr
[70]);
175 writel(DDRMC_CR72_ZQCS_ROTATE(timings
->zqcs_rotate
), &ddrmr
->cr
[72]);
177 writel(DDRMC_CR73_APREBIT(timings
->aprebit
) |
178 DDRMC_CR73_COL_DIFF(col_diff
) |
179 DDRMC_CR73_ROW_DIFF(row_diff
), &ddrmr
->cr
[73]);
180 writel(DDRMC_CR74_BANKSPLT_EN
| DDRMC_CR74_ADDR_CMP_EN
|
181 DDRMC_CR74_CMD_AGE_CNT(timings
->cmd_age_cnt
) |
182 DDRMC_CR74_AGE_CNT(timings
->age_cnt
),
184 writel(DDRMC_CR75_RW_PG_EN
| DDRMC_CR75_RW_EN
| DDRMC_CR75_PRI_EN
|
185 DDRMC_CR75_PLEN
, &ddrmr
->cr
[75]);
186 writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
187 DDRMC_CR76_W2R_SPLT_EN
, &ddrmr
->cr
[76]);
188 writel(DDRMC_CR77_CS_MAP
| DDRMC_CR77_DI_RD_INTLEAVE
|
189 DDRMC_CR77_SWAP_EN
, &ddrmr
->cr
[77]);
190 writel(DDRMC_CR78_Q_FULLNESS(timings
->q_fullness
) |
191 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr
->cr
[78]);
192 writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr
->cr
[79]);
194 writel(DDRMC_CR82_INT_MASK
, &ddrmr
->cr
[82]);
196 writel(DDRMC_CR87_ODT_RD_MAPCS0(timings
->odt_rd_mapcs0
) |
197 DDRMC_CR87_ODT_WR_MAPCS0(timings
->odt_wr_mapcs0
),
199 writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr
->cr
[88]);
200 writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr
->cr
[89]);
202 writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr
->cr
[91]);
203 writel(DDRMC_CR96_WLMRD(timings
->wlmrd
) |
204 DDRMC_CR96_WLDQSEN(timings
->wldqsen
), &ddrmr
->cr
[96]);
206 /* execute custom CR setting sequence (may be NULL) */
207 cr_setting
= board_cr_settings
;
208 if (cr_setting
!= NULL
)
209 while (cr_setting
->cr_rnum
>= 0) {
210 writel(cr_setting
->setting
,
211 &ddrmr
->cr
[cr_setting
->cr_rnum
]);
215 /* perform default PHY settings (may be overridden by custom settings */
216 phy_setting
= default_phy_settings
;
217 while (phy_setting
->phy_rnum
>= 0) {
218 writel(phy_setting
->setting
,
219 &ddrmr
->phy
[phy_setting
->phy_rnum
]);
223 /* execute custom PHY setting sequence (may be NULL) */
224 phy_setting
= board_phy_settings
;
225 if (phy_setting
!= NULL
)
226 while (phy_setting
->phy_rnum
>= 0) {
227 writel(phy_setting
->setting
,
228 &ddrmr
->phy
[phy_setting
->phy_rnum
]);
232 /* all inits done, start the DDR controller */
233 writel(DDRMC_CR00_DRAM_CLASS_DDR3
| DDRMC_CR00_START
, &ddrmr
->cr
[0]);
235 while (!(readl(&ddrmr
->cr
[80]) && 0x100))