2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/mach-imx/boot_mode.h>
12 #include <asm/arch/crm_regs.h>
16 struct aipstz_regs
*aips1
, *aips2
, *aips3
;
18 aips1
= (struct aipstz_regs
*)AIPS1_BASE_ADDR
;
19 aips2
= (struct aipstz_regs
*)AIPS2_BASE_ADDR
;
20 aips3
= (struct aipstz_regs
*)AIPS3_BASE_ADDR
;
23 * Set all MPROTx to be non-bufferable, trusted for R/W,
24 * not forced to user-mode.
26 writel(0x77777777, &aips1
->mprot0
);
27 writel(0x77777777, &aips1
->mprot1
);
28 writel(0x77777777, &aips2
->mprot0
);
29 writel(0x77777777, &aips2
->mprot1
);
32 * Set all OPACRx to be non-bufferable, not require
33 * supervisor privilege level for access,allow for
34 * write access and untrusted master access.
36 writel(0x00000000, &aips1
->opacr0
);
37 writel(0x00000000, &aips1
->opacr1
);
38 writel(0x00000000, &aips1
->opacr2
);
39 writel(0x00000000, &aips1
->opacr3
);
40 writel(0x00000000, &aips1
->opacr4
);
41 writel(0x00000000, &aips2
->opacr0
);
42 writel(0x00000000, &aips2
->opacr1
);
43 writel(0x00000000, &aips2
->opacr2
);
44 writel(0x00000000, &aips2
->opacr3
);
45 writel(0x00000000, &aips2
->opacr4
);
47 if (is_mx6ull() || is_mx6sx() || is_mx7()) {
49 * Set all MPROTx to be non-bufferable, trusted for R/W,
50 * not forced to user-mode.
52 writel(0x77777777, &aips3
->mprot0
);
53 writel(0x77777777, &aips3
->mprot1
);
56 * Set all OPACRx to be non-bufferable, not require
57 * supervisor privilege level for access,allow for
58 * write access and untrusted master access.
60 writel(0x00000000, &aips3
->opacr0
);
61 writel(0x00000000, &aips3
->opacr1
);
62 writel(0x00000000, &aips3
->opacr2
);
63 writel(0x00000000, &aips3
->opacr3
);
64 writel(0x00000000, &aips3
->opacr4
);
68 void imx_wdog_disable_powerdown(void)
70 struct wdog_regs
*wdog1
= (struct wdog_regs
*)WDOG1_BASE_ADDR
;
71 struct wdog_regs
*wdog2
= (struct wdog_regs
*)WDOG2_BASE_ADDR
;
72 struct wdog_regs
*wdog3
= (struct wdog_regs
*)WDOG3_BASE_ADDR
;
74 struct wdog_regs
*wdog4
= (struct wdog_regs
*)WDOG4_BASE_ADDR
;
77 /* Write to the PDE (Power Down Enable) bit */
78 writew(0, &wdog1
->wmcr
);
79 writew(0, &wdog2
->wmcr
);
81 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
82 writew(0, &wdog3
->wmcr
);
84 writew(0, &wdog4
->wmcr
);
88 #define SRC_SCR_WARM_RESET_ENABLE 0
92 struct src
*src_regs
= (struct src
*)SRC_BASE_ADDR
;
96 * force warm reset sources to generate cold reset
97 * for a more reliable restart
99 val
= readl(&src_regs
->scr
);
100 val
&= ~(1 << SRC_SCR_WARM_RESET_ENABLE
);
101 writel(val
, &src_regs
->scr
);
104 #ifdef CONFIG_CMD_BMODE
105 void boot_mode_apply(unsigned cfg_val
)
108 struct src
*psrc
= (struct src
*)SRC_BASE_ADDR
;
109 writel(cfg_val
, &psrc
->gpr9
);
110 reg
= readl(&psrc
->gpr10
);
115 writel(reg
, &psrc
->gpr10
);
119 #if defined(CONFIG_MX6)
120 u32
imx6_src_get_boot_mode(void)
122 if (imx6_is_bmode_from_gpr9())
123 return readl(&src_base
->gpr9
);
125 return readl(&src_base
->sbmr1
);