3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/bootm.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/dma.h>
19 #include <asm/mach-imx/hab.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
24 #include <imx_thermal.h>
41 #if defined(CONFIG_IMX_THERMAL)
42 static const struct imx_thermal_plat imx6_thermal_plat
= {
43 .regs
= (void *)ANATOP_BASE_ADDR
,
48 U_BOOT_DEVICE(imx6_thermal
) = {
49 .name
= "imx_thermal",
50 .platdata
= &imx6_thermal_plat
,
54 #if defined(CONFIG_SECURE_BOOT)
55 struct imx_sec_config_fuse_t
const imx_sec_config_fuse
= {
63 struct scu_regs
*scu
= (struct scu_regs
*)SCU_BASE_ADDR
;
64 return readl(&scu
->config
) & 3;
69 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
70 u32 reg
= readl(&anatop
->digprog_sololite
);
71 u32 type
= ((reg
>> 16) & 0xff);
74 if (type
!= MXC_CPU_MX6SL
) {
75 reg
= readl(&anatop
->digprog
);
76 struct scu_regs
*scu
= (struct scu_regs
*)SCU_BASE_ADDR
;
77 cfg
= readl(&scu
->config
) & 3;
78 type
= ((reg
>> 16) & 0xff);
79 if (type
== MXC_CPU_MX6DL
) {
81 type
= MXC_CPU_MX6SOLO
;
84 if (type
== MXC_CPU_MX6Q
) {
90 major
= ((reg
>> 8) & 0xff);
92 ((type
== MXC_CPU_MX6Q
) || (type
== MXC_CPU_MX6D
))) {
98 reg
&= 0xff; /* mx6 silicon revision */
99 return (type
<< 12) | (reg
+ (0x10 * (major
+ 1)));
103 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
104 * defines a 2-bit SPEED_GRADING
106 #define OCOTP_CFG3_SPEED_SHIFT 16
107 #define OCOTP_CFG3_SPEED_800MHZ 0
108 #define OCOTP_CFG3_SPEED_850MHZ 1
109 #define OCOTP_CFG3_SPEED_1GHZ 2
110 #define OCOTP_CFG3_SPEED_1P2GHZ 3
115 #define OCOTP_CFG3_SPEED_528MHZ 1
116 #define OCOTP_CFG3_SPEED_696MHZ 2
121 #define OCOTP_CFG3_SPEED_792MHZ 2
122 #define OCOTP_CFG3_SPEED_900MHZ 3
124 u32
get_cpu_speed_grade_hz(void)
126 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
127 struct fuse_bank
*bank
= &ocotp
->bank
[0];
128 struct fuse_bank0_regs
*fuse
=
129 (struct fuse_bank0_regs
*)bank
->fuse_regs
;
132 val
= readl(&fuse
->cfg3
);
133 val
>>= OCOTP_CFG3_SPEED_SHIFT
;
137 if (val
== OCOTP_CFG3_SPEED_528MHZ
)
139 else if (val
== OCOTP_CFG3_SPEED_696MHZ
)
146 if (val
== OCOTP_CFG3_SPEED_528MHZ
)
148 else if (val
== OCOTP_CFG3_SPEED_792MHZ
)
150 else if (val
== OCOTP_CFG3_SPEED_900MHZ
)
157 /* Valid for IMX6DQ */
158 case OCOTP_CFG3_SPEED_1P2GHZ
:
159 if (is_mx6dq() || is_mx6dqp())
161 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
162 case OCOTP_CFG3_SPEED_1GHZ
:
164 /* Valid for IMX6DQ */
165 case OCOTP_CFG3_SPEED_850MHZ
:
166 if (is_mx6dq() || is_mx6dqp())
168 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
169 case OCOTP_CFG3_SPEED_800MHZ
:
176 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
177 * defines a 2-bit Temperature Grade
179 * return temperature grade and min/max temperature in Celsius
181 #define OCOTP_MEM0_TEMP_SHIFT 6
183 u32
get_cpu_temp_grade(int *minc
, int *maxc
)
185 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
186 struct fuse_bank
*bank
= &ocotp
->bank
[1];
187 struct fuse_bank1_regs
*fuse
=
188 (struct fuse_bank1_regs
*)bank
->fuse_regs
;
191 val
= readl(&fuse
->mem0
);
192 val
>>= OCOTP_MEM0_TEMP_SHIFT
;
196 if (val
== TEMP_AUTOMOTIVE
) {
199 } else if (val
== TEMP_INDUSTRIAL
) {
202 } else if (val
== TEMP_EXTCOMMERCIAL
) {
213 #ifdef CONFIG_REVISION_TAG
214 u32 __weak
get_board_rev(void)
216 u32 cpurev
= get_cpu_rev();
217 u32 type
= ((cpurev
>> 12) & 0xff);
218 if (type
== MXC_CPU_MX6SOLO
)
219 cpurev
= (MXC_CPU_MX6DL
) << 12 | (cpurev
& 0xFFF);
221 if (type
== MXC_CPU_MX6D
)
222 cpurev
= (MXC_CPU_MX6Q
) << 12 | (cpurev
& 0xFFF);
228 static void clear_ldo_ramp(void)
230 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
233 /* ROM may modify LDO ramp up time according to fuse setting, so in
234 * order to be in the safe side we neeed to reset these settings to
235 * match the reset value: 0'b00
237 reg
= readl(&anatop
->ana_misc2
);
238 reg
&= ~(0x3f << 24);
239 writel(reg
, &anatop
->ana_misc2
);
243 * Set the PMU_REG_CORE register
245 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
246 * Possible values are from 0.725V to 1.450V in steps of
249 static int set_ldo_voltage(enum ldo_reg ldo
, u32 mv
)
251 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
252 u32 val
, step
, old
, reg
= readl(&anatop
->reg_core
);
255 /* No LDO_SOC/PU/ARM */
260 val
= 0x00; /* Power gated off */
262 val
= 0x1F; /* Power FET switched full on. No regulation */
264 val
= (mv
- 700) / 25;
282 old
= (reg
& (0x1F << shift
)) >> shift
;
283 step
= abs(val
- old
);
287 reg
= (reg
& ~(0x1F << shift
)) | (val
<< shift
);
288 writel(reg
, &anatop
->reg_core
);
291 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
299 static void set_ahb_rate(u32 val
)
301 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
304 div
= get_periph_clk() / val
- 1;
305 reg
= readl(&mxc_ccm
->cbcdr
);
307 writel((reg
& (~MXC_CCM_CBCDR_AHB_PODF_MASK
)) |
308 (div
<< MXC_CCM_CBCDR_AHB_PODF_OFFSET
), &mxc_ccm
->cbcdr
);
311 static void clear_mmdc_ch_mask(void)
313 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
315 reg
= readl(&mxc_ccm
->ccdr
);
317 /* Clear MMDC channel mask */
318 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
319 reg
&= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK
);
321 reg
&= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK
| MXC_CCM_CCDR_MMDC_CH0_HS_MASK
);
322 writel(reg
, &mxc_ccm
->ccdr
);
325 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
327 static void init_bandgap(void)
329 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
330 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
331 struct fuse_bank
*bank
= &ocotp
->bank
[1];
332 struct fuse_bank1_regs
*fuse
=
333 (struct fuse_bank1_regs
*)bank
->fuse_regs
;
337 * Ensure the bandgap has stabilized.
339 while (!(readl(&anatop
->ana_misc0
) & 0x80))
342 * For best noise performance of the analog blocks using the
343 * outputs of the bandgap, the reftop_selfbiasoff bit should
346 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF
, &anatop
->ana_misc0_set
);
348 * On i.MX6ULL,we need to set VBGADJ bits according to the
349 * REFTOP_TRIM[3:0] in fuse table
350 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
351 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
352 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
353 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
354 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
355 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
356 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
357 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
360 val
= readl(&fuse
->mem0
);
361 val
>>= OCOTP_MEM0_REFTOP_TRIM_SHIFT
;
364 writel(val
<< BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT
,
365 &anatop
->ana_misc0_set
);
369 int arch_cpu_init(void)
371 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
375 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
376 clear_mmdc_ch_mask();
379 * Disable self-bias circuit in the analog bandap.
380 * The self-bias circuit is used by the bandgap during startup.
381 * This bit should be set after the bandgap has initialized.
385 if (!is_mx6ul() && !is_mx6ull()) {
387 * When low freq boot is enabled, ROM will not set AHB
388 * freq, so we need to ensure AHB freq is 132MHz in such
391 * To i.MX6UL, when power up, default ARM core and
392 * AHB rate is 396M and 132M.
394 if (mxc_get_clock(MXC_ARM_CLK
) == 396000000)
395 set_ahb_rate(132000000);
399 if (is_soc_rev(CHIP_REV_1_0
) == 0) {
401 * According to the design team's requirement on
402 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
403 * as open drain 100K (0x0000b8a0).
404 * Only exists on TO1.0
406 writel(0x0000b8a0, IOMUXC_BASE_ADDR
+ 0x29c);
409 * From TO1.1, SNVS adds internal pull up control
410 * for POR_B, the register filed is GPBIT[1:0],
411 * after system boot up, it can be set to 2b'01
412 * to disable internal pull up.It can save about
413 * 30uA power in SNVS mode.
415 writel((readl(MX6UL_SNVS_LP_BASE_ADDR
+ 0x10) &
417 MX6UL_SNVS_LP_BASE_ADDR
+ 0x10);
423 * GPBIT[1:0] is suggested to set to 2'b11:
424 * 2'b00 : always PUP100K
425 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
426 * 2'b10 : always disable PUP100K
427 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
428 * register offset is different from i.MX6UL, since
429 * i.MX6UL is fixed by ECO.
431 writel(readl(MX6UL_SNVS_LP_BASE_ADDR
) |
432 0x3, MX6UL_SNVS_LP_BASE_ADDR
);
435 /* Set perclk to source from OSC 24MHz */
437 setbits_le32(&ccm
->cscmr1
, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK
);
439 imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
442 setbits_le32(&ccm
->cscdr1
, MXC_CCM_CSCDR1_UART_CLK_SEL
);
449 #ifdef CONFIG_ENV_IS_IN_MMC
450 __weak
int board_mmc_get_env_dev(int devno
)
452 return CONFIG_SYS_MMC_ENV_DEV
;
455 static int mmc_get_boot_dev(void)
457 struct src
*src_regs
= (struct src
*)SRC_BASE_ADDR
;
458 u32 soc_sbmr
= readl(&src_regs
->sbmr1
);
464 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
465 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
466 * i.MX6SL/SX/UL has same layout.
468 bootsel
= (soc_sbmr
& 0x000000FF) >> 6;
470 /* No boot from sd/mmc */
474 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
475 devno
= (soc_sbmr
& 0x00001800) >> 11;
480 int mmc_get_env_dev(void)
482 int devno
= mmc_get_boot_dev();
484 /* If not boot from sd/mmc, use default value */
486 return CONFIG_SYS_MMC_ENV_DEV
;
488 return board_mmc_get_env_dev(devno
);
491 #ifdef CONFIG_SYS_MMC_ENV_PART
492 __weak
int board_mmc_get_env_part(int devno
)
494 return CONFIG_SYS_MMC_ENV_PART
;
497 uint
mmc_get_env_part(struct mmc
*mmc
)
499 int devno
= mmc_get_boot_dev();
501 /* If not boot from sd/mmc, use default value */
503 return CONFIG_SYS_MMC_ENV_PART
;
505 return board_mmc_get_env_part(devno
);
510 int board_postclk_init(void)
512 /* NO LDO SOC on i.MX6SLL */
516 set_ldo_voltage(LDO_SOC
, 1175); /* Set VDDSOC to 1.175V */
521 #if defined(CONFIG_FEC_MXC)
522 void imx_get_mac_from_fuse(int dev_id
, unsigned char *mac
)
524 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
525 struct fuse_bank
*bank
= &ocotp
->bank
[4];
526 struct fuse_bank4_regs
*fuse
=
527 (struct fuse_bank4_regs
*)bank
->fuse_regs
;
529 if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id
== 1) {
530 u32 value
= readl(&fuse
->mac_addr2
);
531 mac
[0] = value
>> 24 ;
532 mac
[1] = value
>> 16 ;
533 mac
[2] = value
>> 8 ;
536 value
= readl(&fuse
->mac_addr1
);
537 mac
[4] = value
>> 24 ;
538 mac
[5] = value
>> 16 ;
541 u32 value
= readl(&fuse
->mac_addr1
);
542 mac
[0] = (value
>> 8);
545 value
= readl(&fuse
->mac_addr0
);
546 mac
[2] = value
>> 24 ;
547 mac
[3] = value
>> 16 ;
548 mac
[4] = value
>> 8 ;
555 #ifndef CONFIG_SPL_BUILD
557 * cfg_val will be used for
558 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
559 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
560 * instead of SBMR1 to determine the boot device.
562 const struct boot_mode soc_boot_modes
[] = {
563 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
564 /* reserved value should start rom usb */
565 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
566 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
568 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
570 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
571 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
572 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
573 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
574 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
575 /* 4 bit bus width */
576 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
577 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
578 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
579 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
584 void reset_misc(void)
586 #ifdef CONFIG_VIDEO_MXS
593 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
594 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
597 u32 reg
, periph1
, periph2
;
599 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
602 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
603 * to make sure PFD is working right, otherwise, PFDs may
604 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
605 * workaround in ROM code, as bus clock need it
608 mask480
= ANATOP_PFD_CLKGATE_MASK(0) |
609 ANATOP_PFD_CLKGATE_MASK(1) |
610 ANATOP_PFD_CLKGATE_MASK(2) |
611 ANATOP_PFD_CLKGATE_MASK(3);
612 mask528
= ANATOP_PFD_CLKGATE_MASK(1) |
613 ANATOP_PFD_CLKGATE_MASK(3);
615 reg
= readl(&ccm
->cbcmr
);
616 periph2
= ((reg
& MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
)
617 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
);
618 periph1
= ((reg
& MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
)
619 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
);
621 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
622 if ((periph2
!= 0x2) && (periph1
!= 0x2))
623 mask528
|= ANATOP_PFD_CLKGATE_MASK(0);
625 if ((periph2
!= 0x1) && (periph1
!= 0x1) &&
626 (periph2
!= 0x3) && (periph1
!= 0x3))
627 mask528
|= ANATOP_PFD_CLKGATE_MASK(2);
629 writel(mask480
, &anatop
->pfd_480_set
);
630 writel(mask528
, &anatop
->pfd_528_set
);
631 writel(mask480
, &anatop
->pfd_480_clr
);
632 writel(mask528
, &anatop
->pfd_528_clr
);
635 #ifdef CONFIG_IMX_HDMI
636 void imx_enable_hdmi_phy(void)
638 struct hdmi_regs
*hdmi
= (struct hdmi_regs
*)HDMI_ARB_BASE_ADDR
;
640 reg
= readb(&hdmi
->phy_conf0
);
641 reg
|= HDMI_PHY_CONF0_PDZ_MASK
;
642 writeb(reg
, &hdmi
->phy_conf0
);
644 reg
|= HDMI_PHY_CONF0_ENTMDS_MASK
;
645 writeb(reg
, &hdmi
->phy_conf0
);
647 reg
|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK
;
648 writeb(reg
, &hdmi
->phy_conf0
);
649 writeb(HDMI_MC_PHYRSTZ_ASSERT
, &hdmi
->mc_phyrstz
);
652 void imx_setup_hdmi(void)
654 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
655 struct hdmi_regs
*hdmi
= (struct hdmi_regs
*)HDMI_ARB_BASE_ADDR
;
659 /* Turn on HDMI PHY clock */
660 reg
= readl(&mxc_ccm
->CCGR2
);
661 reg
|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
|
662 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK
;
663 writel(reg
, &mxc_ccm
->CCGR2
);
664 writeb(HDMI_MC_PHYRSTZ_DEASSERT
, &hdmi
->mc_phyrstz
);
665 reg
= readl(&mxc_ccm
->chsccdr
);
666 reg
&= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|
667 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|
668 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK
);
669 reg
|= (CHSCCDR_PODF_DIVIDE_BY_3
670 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET
)
671 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
672 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET
);
673 writel(reg
, &mxc_ccm
->chsccdr
);
675 /* Clear the overflow condition */
676 if (readb(&hdmi
->ih_fc_stat2
) & HDMI_IH_FC_STAT2_OVERFLOW_MASK
) {
677 /* TMDS software reset */
678 writeb((u8
)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ
, &hdmi
->mc_swrstz
);
679 val
= readb(&hdmi
->fc_invidconf
);
680 /* Need minimum 3 times to write to clear the register */
681 for (count
= 0 ; count
< 5 ; count
++)
682 writeb(val
, &hdmi
->fc_invidconf
);
689 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
691 /* enable AXI cache for VDOA/VPU/IPU */
692 writel(0xF00000CF, &iomux
->gpr
[4]);
694 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
695 writel(0x77177717, &iomux
->gpr
[6]);
696 writel(0x77177717, &iomux
->gpr
[7]);
698 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
699 writel(0x007F007F, &iomux
->gpr
[6]);
700 writel(0x007F007F, &iomux
->gpr
[7]);
704 #ifdef CONFIG_IMX_BOOTAUX
705 int arch_auxiliary_core_up(u32 core_id
, u32 boot_private_data
)
710 if (!boot_private_data
)
713 stack
= *(u32
*)boot_private_data
;
714 pc
= *(u32
*)(boot_private_data
+ 4);
716 /* Set the stack and pc to M4 bootROM */
717 writel(stack
, M4_BOOTROM_BASE_ADDR
);
718 writel(pc
, M4_BOOTROM_BASE_ADDR
+ 4);
721 src_reg
= (struct src
*)SRC_BASE_ADDR
;
722 clrsetbits_le32(&src_reg
->scr
, SRC_SCR_M4C_NON_SCLR_RST_MASK
,
723 SRC_SCR_M4_ENABLE_MASK
);
728 int arch_auxiliary_core_check_up(u32 core_id
)
730 struct src
*src_reg
= (struct src
*)SRC_BASE_ADDR
;
733 val
= readl(&src_reg
->scr
);
735 if (val
& SRC_SCR_M4C_NON_SCLR_RST_MASK
)
736 return 0; /* assert in reset */