1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
11 #include <asm/secure.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/armv7.h>
15 #include <linux/bitops.h>
19 #define GPC_LPCR_A7_BSC 0x0
20 #define GPC_LPCR_A7_AD 0x4
21 #define GPC_SLPCR 0x14
22 #define GPC_PGC_ACK_SEL_A7 0x24
23 #define GPC_IMR1_CORE0 0x30
24 #define GPC_SLOT0_CFG 0xb0
25 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0
26 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc
27 #define GPC_PGC_C0 0x800
28 #define GPC_PGC_C0 0x800
29 #define GPC_PGC_C1 0x840
30 #define GPC_PGC_SCU 0x880
32 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
33 #define BM_LPCR_A7_BSC_LPM1 0xc
34 #define BM_LPCR_A7_BSC_LPM0 0x3
35 #define BP_LPCR_A7_BSC_LPM0 0
36 #define BM_SLPCR_EN_DSM 0x80000000
37 #define BM_SLPCR_RBC_EN 0x40000000
38 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
39 #define BM_SLPCR_VSTBY 0x4
40 #define BM_SLPCR_SBYOS 0x2
41 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
42 #define BM_LPCR_A7_AD_L2PGE 0x10000
43 #define BM_LPCR_A7_AD_EN_C1_PUP 0x800
44 #define BM_LPCR_A7_AD_EN_C0_PUP 0x200
45 #define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10
46 #define BM_LPCR_A7_AD_EN_C1_PDN 0x8
47 #define BM_LPCR_A7_AD_EN_C0_PDN 0x2
49 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1
50 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
52 #define BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK 0x8000
53 #define BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK 0x80000000
55 #define MAX_SLOT_NUMBER 10
56 #define A7_LPM_WAIT 0x5
57 #define A7_LPM_STOP 0xa
59 #define BM_SYS_COUNTER_CNTCR_FCR1 0x200
60 #define BM_SYS_COUNTER_CNTCR_FCR0 0x100
65 #define ANADIG_ARM_PLL 0x60
66 #define ANADIG_DDR_PLL 0x70
67 #define ANADIG_SYS_PLL 0xb0
68 #define ANADIG_ENET_PLL 0xe0
69 #define ANADIG_AUDIO_PLL 0xf0
70 #define ANADIG_VIDEO_PLL 0x130
71 #define BM_ANATOP_ARM_PLL_OVERRIDE BIT(20)
72 #define BM_ANATOP_DDR_PLL_OVERRIDE BIT(19)
73 #define BM_ANATOP_SYS_PLL_OVERRIDE (0x1ff << 17)
74 #define BM_ANATOP_ENET_PLL_OVERRIDE BIT(13)
75 #define BM_ANATOP_AUDIO_PLL_OVERRIDE BIT(24)
76 #define BM_ANATOP_VIDEO_PLL_OVERRIDE BIT(24)
79 #define DDRC_PWRCTL 0x30
80 #define DDRC_PSTAT 0x3fc
82 #define SRC_GPR1_MX7D 0x074
83 #define SRC_GPR2_MX7D 0x078
84 #define SRC_A7RCR0 0x004
85 #define SRC_A7RCR1 0x008
87 #define BP_SRC_A7RCR0_A7_CORE_RESET0 0
88 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
90 #define SNVS_LPCR 0x38
91 #define BP_SNVS_LPCR_DP_EN 0x20
92 #define BP_SNVS_LPCR_TOP 0x40
94 #define CCM_CCGR_SNVS 0x4250
96 #define CCM_ROOT_WDOG 0xbb80
97 #define CCM_CCGR_WDOG1 0x49c0
99 #define MPIDR_AFF0 GENMASK(7, 0)
101 #define IMX7D_PSCI_NR_CPUS 2
102 #if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
103 #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
106 #define imx_cpu_gpr_entry_offset(cpu) \
107 (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
108 #define imx_cpu_gpr_para_offset(cpu) \
109 (imx_cpu_gpr_entry_offset(cpu) + 4)
111 #define IMX_CPU_SYNC_OFF ~0
112 #define IMX_CPU_SYNC_ON 0
114 u8 psci_state
[IMX7D_PSCI_NR_CPUS
] __secure_data
= {
115 PSCI_AFFINITY_LEVEL_ON
,
116 PSCI_AFFINITY_LEVEL_OFF
};
131 enum mxc_cpu_pwr_mode
{
137 extern void psci_system_resume(void);
139 static inline void psci_set_state(int cpu
, u8 state
)
141 psci_state
[cpu
] = state
;
146 static inline void imx_gpcv2_set_m_core_pgc(bool enable
, u32 offset
)
148 writel(enable
, GPC_IPS_BASE_ADDR
+ offset
);
151 __secure
void imx_gpcv2_set_core_power(int cpu
, bool pdn
)
153 u32 reg
= pdn
? GPC_CPU_PGC_SW_PUP_REQ
: GPC_CPU_PGC_SW_PDN_REQ
;
154 u32 pgc
= cpu
? GPC_PGC_C1
: GPC_PGC_C0
;
155 u32 pdn_pup_req
= cpu
? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7
:
156 BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7
;
159 imx_gpcv2_set_m_core_pgc(true, pgc
);
161 val
= readl(GPC_IPS_BASE_ADDR
+ reg
);
163 writel(val
, GPC_IPS_BASE_ADDR
+ reg
);
165 while ((readl(GPC_IPS_BASE_ADDR
+ reg
) & pdn_pup_req
) != 0)
168 imx_gpcv2_set_m_core_pgc(false, pgc
);
171 __secure
void imx_enable_cpu_ca7(int cpu
, bool enable
)
175 mask
= 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE
+ cpu
- 1);
176 val
= readl(SRC_BASE_ADDR
+ SRC_A7RCR1
);
177 val
= enable
? val
| mask
: val
& ~mask
;
178 writel(val
, SRC_BASE_ADDR
+ SRC_A7RCR1
);
181 __secure
void psci_arch_cpu_entry(void)
183 u32 cpu
= psci_get_cpu_id();
185 psci_set_state(cpu
, PSCI_AFFINITY_LEVEL_ON
);
188 __secure s32
psci_cpu_on(u32 __always_unused function_id
, u32 mpidr
, u32 ep
,
191 u32 cpu
= mpidr
& MPIDR_AFF0
;
193 if (mpidr
& ~MPIDR_AFF0
)
194 return ARM_PSCI_RET_INVAL
;
196 if (cpu
>= IMX7D_PSCI_NR_CPUS
)
197 return ARM_PSCI_RET_INVAL
;
199 if (psci_state
[cpu
] == PSCI_AFFINITY_LEVEL_ON
)
200 return ARM_PSCI_RET_ALREADY_ON
;
202 if (psci_state
[cpu
] == PSCI_AFFINITY_LEVEL_ON_PENDING
)
203 return ARM_PSCI_RET_ON_PENDING
;
205 psci_save(cpu
, ep
, context_id
);
207 writel((u32
)psci_cpu_entry
, imx_cpu_gpr_entry_offset(cpu
));
209 psci_set_state(cpu
, PSCI_AFFINITY_LEVEL_ON_PENDING
);
211 imx_gpcv2_set_core_power(cpu
, true);
212 imx_enable_cpu_ca7(cpu
, true);
214 return ARM_PSCI_RET_SUCCESS
;
217 __secure s32
psci_cpu_off(void)
221 cpu
= psci_get_cpu_id();
223 psci_cpu_off_common();
224 psci_set_state(cpu
, PSCI_AFFINITY_LEVEL_OFF
);
226 imx_enable_cpu_ca7(cpu
, false);
227 imx_gpcv2_set_core_power(cpu
, false);
229 * We use the cpu jumping argument register to sync with
230 * psci_affinity_info() which is running on cpu0 to kill the cpu.
232 writel(IMX_CPU_SYNC_OFF
, imx_cpu_gpr_para_offset(cpu
));
238 __secure
void psci_system_reset(void)
240 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG1_BASE_ADDR
;
242 /* make sure WDOG1 clock is enabled */
243 writel(0x1 << 28, CCM_BASE_ADDR
+ CCM_ROOT_WDOG
);
244 writel(0x3, CCM_BASE_ADDR
+ CCM_CCGR_WDOG1
);
245 writew(WCR_WDE
, &wdog
->wcr
);
251 __secure
void psci_system_off(void)
255 /* make sure SNVS clock is enabled */
256 writel(0x3, CCM_BASE_ADDR
+ CCM_CCGR_SNVS
);
258 val
= readl(SNVS_BASE_ADDR
+ SNVS_LPCR
);
259 val
|= BP_SNVS_LPCR_DP_EN
| BP_SNVS_LPCR_TOP
;
260 writel(val
, SNVS_BASE_ADDR
+ SNVS_LPCR
);
266 __secure u32
psci_version(void)
268 return ARM_PSCI_VER_1_0
;
271 __secure s32
psci_cpu_suspend(u32 __always_unused function_id
, u32 power_state
,
272 u32 entry_point_address
,
275 return ARM_PSCI_RET_INVAL
;
278 __secure s32
psci_affinity_info(u32 __always_unused function_id
,
280 u32 lowest_affinity_level
)
282 u32 cpu
= target_affinity
& MPIDR_AFF0
;
284 if (lowest_affinity_level
> 0)
285 return ARM_PSCI_RET_INVAL
;
287 if (target_affinity
& ~MPIDR_AFF0
)
288 return ARM_PSCI_RET_INVAL
;
290 if (cpu
>= IMX7D_PSCI_NR_CPUS
)
291 return ARM_PSCI_RET_INVAL
;
293 /* CPU is waiting for killed */
294 if (readl(imx_cpu_gpr_para_offset(cpu
)) == IMX_CPU_SYNC_OFF
) {
295 imx_enable_cpu_ca7(cpu
, false);
296 imx_gpcv2_set_core_power(cpu
, false);
297 writel(IMX_CPU_SYNC_ON
, imx_cpu_gpr_para_offset(cpu
));
300 return psci_state
[cpu
];
303 __secure u32
psci_migrate_info_type(void)
305 /* Trusted OS is either not present or does not require migration */
309 __secure s32
psci_features(u32 __always_unused function_id
, u32 psci_fid
)
312 case ARM_PSCI_0_2_FN_PSCI_VERSION
:
313 case ARM_PSCI_0_2_FN_CPU_OFF
:
314 case ARM_PSCI_0_2_FN_CPU_ON
:
315 case ARM_PSCI_0_2_FN_AFFINITY_INFO
:
316 case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
:
317 case ARM_PSCI_0_2_FN_SYSTEM_OFF
:
318 case ARM_PSCI_0_2_FN_SYSTEM_RESET
:
319 case ARM_PSCI_1_0_FN_PSCI_FEATURES
:
320 case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
:
323 return ARM_PSCI_RET_NI
;
326 static __secure
void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode
)
328 u32 val1
, val2
, val3
;
330 val1
= readl(GPC_IPS_BASE_ADDR
+ GPC_LPCR_A7_BSC
);
331 val2
= readl(GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
333 /* all cores' LPM settings must be same */
334 val1
&= ~(BM_LPCR_A7_BSC_LPM0
| BM_LPCR_A7_BSC_LPM1
);
335 val1
|= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM
;
337 val2
&= ~(BM_SLPCR_EN_DSM
| BM_SLPCR_VSTBY
| BM_SLPCR_RBC_EN
|
338 BM_SLPCR_SBYOS
| BM_SLPCR_BYPASS_PMIC_READY
);
340 * GPC: When improper low-power sequence is used,
341 * the SoC enters low power mode before the ARM core executes WFI.
343 * Software workaround:
344 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
345 * by setting IOMUX_GPR1_IRQ.
346 * 2) Software should then unmask IRQ #32 in GPC before setting GPC
348 * 3) Software should mask IRQ #32 right after GPC Low-Power mode
353 val3
= readl(GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
);
355 writel(val3
, GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
);
358 val1
|= A7_LPM_WAIT
<< BP_LPCR_A7_BSC_LPM0
;
359 val1
&= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM
;
360 val3
= readl(GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
);
362 writel(val3
, GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
);
365 val1
|= A7_LPM_STOP
<< BP_LPCR_A7_BSC_LPM0
;
366 val1
&= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM
;
367 val2
|= BM_SLPCR_EN_DSM
;
368 val2
|= BM_SLPCR_SBYOS
;
369 val2
|= BM_SLPCR_VSTBY
;
370 val2
|= BM_SLPCR_BYPASS_PMIC_READY
;
371 val3
= readl(GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
);
373 writel(val3
, GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
);
378 writel(val1
, GPC_IPS_BASE_ADDR
+ GPC_LPCR_A7_BSC
);
379 writel(val2
, GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
382 static __secure
void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn
)
384 u32 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_LPCR_A7_AD
);
386 val
&= ~(BM_LPCR_A7_AD_EN_PLAT_PDN
| BM_LPCR_A7_AD_L2PGE
);
388 val
|= BM_LPCR_A7_AD_EN_PLAT_PDN
| BM_LPCR_A7_AD_L2PGE
;
390 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_LPCR_A7_AD
);
393 static __secure
void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu
, bool pdn
)
397 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_LPCR_A7_AD
);
400 val
|= BM_LPCR_A7_AD_EN_C0_PDN
|
401 BM_LPCR_A7_AD_EN_C0_PUP
;
403 val
&= ~(BM_LPCR_A7_AD_EN_C0_PDN
|
404 BM_LPCR_A7_AD_EN_C0_PUP
);
408 val
|= BM_LPCR_A7_AD_EN_C1_PDN
|
409 BM_LPCR_A7_AD_EN_C1_PUP
;
411 val
&= ~(BM_LPCR_A7_AD_EN_C1_PDN
|
412 BM_LPCR_A7_AD_EN_C1_PUP
);
414 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_LPCR_A7_AD
);
417 static __secure
void imx_gpcv2_set_slot_ack(u32 index
, enum imx_gpc_slot m_core
,
422 if (index
>= MAX_SLOT_NUMBER
)
426 writel(readl(GPC_IPS_BASE_ADDR
+ GPC_SLOT0_CFG
+ index
* 4) |
427 ((mode
+ 1) << (m_core
* 2)),
428 GPC_IPS_BASE_ADDR
+ GPC_SLOT0_CFG
+ index
* 4);
432 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_PGC_ACK_SEL_A7
);
433 /* clear dummy ack */
434 val
&= ~(mode
? BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK
:
435 BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK
);
436 val
|= 1 << (m_core
+ (mode
? 16 : 0));
437 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_PGC_ACK_SEL_A7
);
441 static __secure
void imx_system_counter_resume(void)
445 val
= readl(SYSCNT_CTRL_IPS_BASE_ADDR
);
446 val
&= ~BM_SYS_COUNTER_CNTCR_FCR1
;
447 val
|= BM_SYS_COUNTER_CNTCR_FCR0
;
448 writel(val
, SYSCNT_CTRL_IPS_BASE_ADDR
);
451 static __secure
void imx_system_counter_suspend(void)
455 val
= readl(SYSCNT_CTRL_IPS_BASE_ADDR
);
456 val
&= ~BM_SYS_COUNTER_CNTCR_FCR0
;
457 val
|= BM_SYS_COUNTER_CNTCR_FCR1
;
458 writel(val
, SYSCNT_CTRL_IPS_BASE_ADDR
);
461 static __secure
void gic_resume(void)
464 u32 gic_dist_addr
= GIC400_ARB_BASE_ADDR
+ GIC_DIST_OFFSET
;
466 /* enable the GIC distributor */
467 writel(readl(gic_dist_addr
+ GICD_CTLR
) | 0x03,
468 gic_dist_addr
+ GICD_CTLR
);
470 /* TYPER[4:0] contains an encoded number of available interrupts */
471 itlinesnr
= readl(gic_dist_addr
+ GICD_TYPER
) & 0x1f;
473 /* set all bits in the GIC group registers to one to allow access
474 * from non-secure state. The first 32 interrupts are private per
475 * CPU and will be set later when enabling the GIC for each core
477 for (i
= 1; i
<= itlinesnr
; i
++)
478 writel((u32
)-1, gic_dist_addr
+ GICD_IGROUPRn
+ 4 * i
);
481 static inline void imx_pll_suspend(void)
483 writel(BM_ANATOP_ARM_PLL_OVERRIDE
,
484 ANATOP_BASE_ADDR
+ ANADIG_ARM_PLL
+ REG_SET
);
485 writel(BM_ANATOP_DDR_PLL_OVERRIDE
,
486 ANATOP_BASE_ADDR
+ ANADIG_DDR_PLL
+ REG_SET
);
487 writel(BM_ANATOP_SYS_PLL_OVERRIDE
,
488 ANATOP_BASE_ADDR
+ ANADIG_SYS_PLL
+ REG_SET
);
489 writel(BM_ANATOP_ENET_PLL_OVERRIDE
,
490 ANATOP_BASE_ADDR
+ ANADIG_ENET_PLL
+ REG_SET
);
491 writel(BM_ANATOP_AUDIO_PLL_OVERRIDE
,
492 ANATOP_BASE_ADDR
+ ANADIG_AUDIO_PLL
+ REG_SET
);
493 writel(BM_ANATOP_VIDEO_PLL_OVERRIDE
,
494 ANATOP_BASE_ADDR
+ ANADIG_VIDEO_PLL
+ REG_SET
);
497 static inline void imx_pll_resume(void)
499 writel(BM_ANATOP_ARM_PLL_OVERRIDE
,
500 ANATOP_BASE_ADDR
+ ANADIG_ARM_PLL
+ REG_CLR
);
501 writel(BM_ANATOP_DDR_PLL_OVERRIDE
,
502 ANATOP_BASE_ADDR
+ ANADIG_DDR_PLL
+ REG_CLR
);
503 writel(BM_ANATOP_SYS_PLL_OVERRIDE
,
504 ANATOP_BASE_ADDR
+ ANADIG_SYS_PLL
+ REG_CLR
);
505 writel(BM_ANATOP_ENET_PLL_OVERRIDE
,
506 ANATOP_BASE_ADDR
+ ANADIG_ENET_PLL
+ REG_CLR
);
507 writel(BM_ANATOP_AUDIO_PLL_OVERRIDE
,
508 ANATOP_BASE_ADDR
+ ANADIG_AUDIO_PLL
+ REG_CLR
);
509 writel(BM_ANATOP_VIDEO_PLL_OVERRIDE
,
510 ANATOP_BASE_ADDR
+ ANADIG_VIDEO_PLL
+ REG_CLR
);
513 static inline void imx_udelay(u32 usec
)
518 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq
));
519 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start
));
521 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end
));
522 if ((end
- start
) > usec
* (freq
/ 1000000))
527 static inline void imx_ddrc_enter_self_refresh(void)
529 writel(0, DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
);
530 while (readl(DDRC_IPS_BASE_ADDR
+ DDRC_PSTAT
) & 0x10001)
533 writel(0x20, DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
);
534 while ((readl(DDRC_IPS_BASE_ADDR
+ DDRC_STAT
) & 0x23) != 0x23)
536 writel(readl(DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
) | 0x8,
537 DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
);
540 static inline void imx_ddrc_exit_self_refresh(void)
542 writel(0, DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
);
543 while ((readl(DDRC_IPS_BASE_ADDR
+ DDRC_STAT
) & 0x3) == 0x3)
545 writel(readl(DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
) | 0x1,
546 DDRC_IPS_BASE_ADDR
+ DDRC_PWRCTL
);
549 __secure
void imx_system_resume(void)
551 unsigned int i
, val
, imr
[4], entry
;
553 entry
= psci_get_target_pc(0);
554 imx_ddrc_exit_self_refresh();
555 imx_system_counter_resume();
556 imx_gpcv2_set_lpm_mode(RUN
);
557 imx_gpcv2_set_cpu_power_gate_by_lpm(0, false);
558 imx_gpcv2_set_plat_power_gate_by_lpm(false);
559 imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0
);
560 imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU
);
563 * need to mask all interrupts in GPC before
564 * operating RBC configurations
566 for (i
= 0; i
< 4; i
++) {
567 imr
[i
] = readl(GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
+ i
* 4);
568 writel(~0, GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
+ i
* 4);
571 /* configure RBC enable bit */
572 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
573 val
&= ~BM_SLPCR_RBC_EN
;
574 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
576 /* configure RBC count */
577 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
578 val
&= ~BM_SLPCR_REG_BYPASS_COUNT
;
579 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
582 * need to delay at least 2 cycles of CKIL(32K)
583 * due to hardware design requirement, which is
584 * ~61us, here we use 65us for safe
588 /* restore GPC interrupt mask settings */
589 for (i
= 0; i
< 4; i
++)
590 writel(imr
[i
], GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
+ i
* 4);
592 /* initialize gic distributor */
596 /* save cpu0 entry */
597 psci_save(0, entry
, 0);
601 __secure
void psci_system_suspend(u32 __always_unused function_id
,
602 u32 ep
, u32 context_id
)
607 psci_save(0, ep
, context_id
);
608 /* overwrite PLL to be controlled by low power mode */
610 imx_system_counter_suspend();
611 /* set CA7 platform to enter STOP mode */
612 imx_gpcv2_set_lpm_mode(STOP
);
613 /* enable core0/scu power down/up with low power mode */
614 imx_gpcv2_set_cpu_power_gate_by_lpm(0, true);
615 imx_gpcv2_set_plat_power_gate_by_lpm(true);
616 /* time slot settings for core0 and scu */
617 imx_gpcv2_set_slot_ack(0, CORE0_A7
, false, false);
618 imx_gpcv2_set_slot_ack(1, SCU_A7
, false, true);
619 imx_gpcv2_set_slot_ack(5, SCU_A7
, true, false);
620 imx_gpcv2_set_slot_ack(6, CORE0_A7
, true, true);
621 imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0
);
622 imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU
);
623 psci_v7_flush_dcache_all();
625 imx_ddrc_enter_self_refresh();
628 * e10133: ARM: Boot failure after A7 enters into
629 * low-power idle mode
632 * If both CPU0/CPU1 are IDLE, the last IDLE CPU should
633 * disable GIC first, then REG_BYPASS_COUNTER is used
634 * to mask wakeup INT, and then execute “wfi” is used to
635 * bring the system into power down processing safely.
636 * The counter must be enabled as close to the “wfi” state
637 * as possible. The following equation can be used to
638 * determine the RBC counter value:
639 * RBC_COUNT * (1/32K RTC frequency) >=
640 * (46 + PDNSCR_SW + PDNSCR_SW2ISO ) ( 1/IPG_CLK frequency ).
643 /* disable GIC distributor */
644 writel(0, GIC400_ARB_BASE_ADDR
+ GIC_DIST_OFFSET
);
646 for (i
= 0; i
< 4; i
++)
647 gpc_mask
[i
] = readl(GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
+ i
* 4);
650 * enable the RBC bypass counter here
651 * to hold off the interrupts. RBC counter
652 * = 8 (240us). With this setting, the latency
653 * from wakeup interrupt to ARM power up
656 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
657 val
&= ~(0x3f << 24);
659 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
661 /* enable the counter. */
662 val
= readl(GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
664 writel(val
, GPC_IPS_BASE_ADDR
+ GPC_SLPCR
);
666 /* unmask all the GPC interrupts. */
667 for (i
= 0; i
< 4; i
++)
668 writel(gpc_mask
[i
], GPC_IPS_BASE_ADDR
+ GPC_IMR1_CORE0
+ i
* 4);
671 * now delay for a short while (3usec)
672 * ARM is at 1GHz at this point
673 * so a short loop should be enough.
674 * this delay is required to ensure that
675 * the RBC counter can start counting in
676 * case an interrupt is already pending
677 * or in case an interrupt arrives just
678 * as ARM is about to assert DSM_request.
682 /* save resume entry and sp in CPU0 GPR registers */
683 asm volatile("mov %0, sp" : "=r" (val
));
684 writel((u32
)psci_system_resume
, SRC_BASE_ADDR
+ SRC_GPR1_MX7D
);
685 writel(val
, SRC_BASE_ADDR
+ SRC_GPR2_MX7D
);