2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/clocksource.h>
28 #include <linux/clockchips.h>
30 #include <linux/export.h>
31 #include <linux/gpio.h>
34 #include <mach/hardware.h>
36 #include <asm/uaccess.h>
37 #include <asm/pgtable.h>
40 #include <asm/sched_clock.h>
41 #include <asm/system_misc.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
47 static void __init
ixp4xx_clocksource_init(void);
48 static void __init
ixp4xx_clockevent_init(void);
49 static struct clock_event_device clockevent_ixp4xx
;
51 /*************************************************************************
52 * IXP4xx chipset I/O mapping
53 *************************************************************************/
54 static struct map_desc ixp4xx_io_desc
[] __initdata
= {
55 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
56 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT
,
57 .pfn
= __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS
),
58 .length
= IXP4XX_PERIPHERAL_REGION_SIZE
,
60 }, { /* Expansion Bus Config Registers */
61 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT
,
62 .pfn
= __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS
),
63 .length
= IXP4XX_EXP_CFG_REGION_SIZE
,
65 }, { /* PCI Registers */
66 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT
,
67 .pfn
= __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS
),
68 .length
= IXP4XX_PCI_CFG_REGION_SIZE
,
70 }, { /* Queue Manager */
71 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT
,
72 .pfn
= __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS
),
73 .length
= IXP4XX_QMGR_REGION_SIZE
,
78 void __init
ixp4xx_map_io(void)
80 iotable_init(ixp4xx_io_desc
, ARRAY_SIZE(ixp4xx_io_desc
));
84 /*************************************************************************
85 * IXP4xx chipset IRQ handling
87 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
88 * (be it PCI or something else) configures that GPIO line
90 **************************************************************************/
91 enum ixp4xx_irq_type
{
92 IXP4XX_IRQ_LEVEL
, IXP4XX_IRQ_EDGE
95 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
96 static unsigned long long ixp4xx_irq_edge
= 0;
99 * IRQ -> GPIO mapping table
101 static signed char irq2gpio
[32] = {
102 -1, -1, -1, -1, -1, -1, 0, 1,
103 -1, -1, -1, -1, -1, -1, -1, -1,
104 -1, -1, -1, 2, 3, 4, 5, 6,
105 7, 8, 9, 10, 11, 12, -1, -1,
108 static int ixp4xx_gpio_to_irq(struct gpio_chip
*chip
, unsigned gpio
)
112 for (irq
= 0; irq
< 32; irq
++) {
113 if (irq2gpio
[irq
] == gpio
)
119 int irq_to_gpio(unsigned int irq
)
121 int gpio
= (irq
< 32) ? irq2gpio
[irq
] : -EINVAL
;
128 EXPORT_SYMBOL(irq_to_gpio
);
130 static int ixp4xx_set_irq_type(struct irq_data
*d
, unsigned int type
)
132 int line
= irq2gpio
[d
->irq
];
134 enum ixp4xx_irq_type irq_type
;
135 volatile u32
*int_reg
;
144 case IRQ_TYPE_EDGE_BOTH
:
145 int_style
= IXP4XX_GPIO_STYLE_TRANSITIONAL
;
146 irq_type
= IXP4XX_IRQ_EDGE
;
148 case IRQ_TYPE_EDGE_RISING
:
149 int_style
= IXP4XX_GPIO_STYLE_RISING_EDGE
;
150 irq_type
= IXP4XX_IRQ_EDGE
;
152 case IRQ_TYPE_EDGE_FALLING
:
153 int_style
= IXP4XX_GPIO_STYLE_FALLING_EDGE
;
154 irq_type
= IXP4XX_IRQ_EDGE
;
156 case IRQ_TYPE_LEVEL_HIGH
:
157 int_style
= IXP4XX_GPIO_STYLE_ACTIVE_HIGH
;
158 irq_type
= IXP4XX_IRQ_LEVEL
;
160 case IRQ_TYPE_LEVEL_LOW
:
161 int_style
= IXP4XX_GPIO_STYLE_ACTIVE_LOW
;
162 irq_type
= IXP4XX_IRQ_LEVEL
;
168 if (irq_type
== IXP4XX_IRQ_EDGE
)
169 ixp4xx_irq_edge
|= (1 << d
->irq
);
171 ixp4xx_irq_edge
&= ~(1 << d
->irq
);
173 if (line
>= 8) { /* pins 8-15 */
175 int_reg
= IXP4XX_GPIO_GPIT2R
;
176 } else { /* pins 0-7 */
177 int_reg
= IXP4XX_GPIO_GPIT1R
;
180 /* Clear the style for the appropriate pin */
181 *int_reg
&= ~(IXP4XX_GPIO_STYLE_CLEAR
<<
182 (line
* IXP4XX_GPIO_STYLE_SIZE
));
184 *IXP4XX_GPIO_GPISR
= (1 << line
);
186 /* Set the new style */
187 *int_reg
|= (int_style
<< (line
* IXP4XX_GPIO_STYLE_SIZE
));
189 /* Configure the line as an input */
190 gpio_line_config(irq2gpio
[d
->irq
], IXP4XX_GPIO_IN
);
195 static void ixp4xx_irq_mask(struct irq_data
*d
)
197 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d
->irq
>= 32)
198 *IXP4XX_ICMR2
&= ~(1 << (d
->irq
- 32));
200 *IXP4XX_ICMR
&= ~(1 << d
->irq
);
203 static void ixp4xx_irq_ack(struct irq_data
*d
)
205 int line
= (d
->irq
< 32) ? irq2gpio
[d
->irq
] : -1;
208 *IXP4XX_GPIO_GPISR
= (1 << line
);
212 * Level triggered interrupts on GPIO lines can only be cleared when the
213 * interrupt condition disappears.
215 static void ixp4xx_irq_unmask(struct irq_data
*d
)
217 if (!(ixp4xx_irq_edge
& (1 << d
->irq
)))
220 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d
->irq
>= 32)
221 *IXP4XX_ICMR2
|= (1 << (d
->irq
- 32));
223 *IXP4XX_ICMR
|= (1 << d
->irq
);
226 static struct irq_chip ixp4xx_irq_chip
= {
228 .irq_ack
= ixp4xx_irq_ack
,
229 .irq_mask
= ixp4xx_irq_mask
,
230 .irq_unmask
= ixp4xx_irq_unmask
,
231 .irq_set_type
= ixp4xx_set_irq_type
,
234 void __init
ixp4xx_init_irq(void)
239 * ixp4xx does not implement the XScale PWRMODE register
240 * so it must not call cpu_do_idle().
244 /* Route all sources to IRQ instead of FIQ */
247 /* Disable all interrupt */
250 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
251 /* Route upper 32 sources to IRQ instead of FIQ */
252 *IXP4XX_ICLR2
= 0x00;
254 /* Disable upper 32 interrupts */
255 *IXP4XX_ICMR2
= 0x00;
258 /* Default to all level triggered */
259 for(i
= 0; i
< NR_IRQS
; i
++) {
260 irq_set_chip_and_handler(i
, &ixp4xx_irq_chip
,
262 set_irq_flags(i
, IRQF_VALID
);
267 /*************************************************************************
269 * We use OS timer1 on the CPU for the timer tick and the timestamp
270 * counter as a source of real clock ticks to account for missed jiffies.
271 *************************************************************************/
273 static irqreturn_t
ixp4xx_timer_interrupt(int irq
, void *dev_id
)
275 struct clock_event_device
*evt
= dev_id
;
277 /* Clear Pending Interrupt by writing '1' to it */
278 *IXP4XX_OSST
= IXP4XX_OSST_TIMER_1_PEND
;
280 evt
->event_handler(evt
);
285 static struct irqaction ixp4xx_timer_irq
= {
287 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
288 .handler
= ixp4xx_timer_interrupt
,
289 .dev_id
= &clockevent_ixp4xx
,
292 void __init
ixp4xx_timer_init(void)
294 /* Reset/disable counter */
297 /* Clear Pending Interrupt by writing '1' to it */
298 *IXP4XX_OSST
= IXP4XX_OSST_TIMER_1_PEND
;
300 /* Reset time-stamp counter */
303 /* Connect the interrupt handler and enable the interrupt */
304 setup_irq(IRQ_IXP4XX_TIMER1
, &ixp4xx_timer_irq
);
306 ixp4xx_clocksource_init();
307 ixp4xx_clockevent_init();
310 static struct pxa2xx_udc_mach_info ixp4xx_udc_info
;
312 void __init
ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info
*info
)
314 memcpy(&ixp4xx_udc_info
, info
, sizeof *info
);
317 static struct resource ixp4xx_udc_resources
[] = {
321 .flags
= IORESOURCE_MEM
,
324 .start
= IRQ_IXP4XX_USB
,
325 .end
= IRQ_IXP4XX_USB
,
326 .flags
= IORESOURCE_IRQ
,
331 * USB device controller. The IXP4xx uses the same controller as PXA25X,
332 * so we just use the same device.
334 static struct platform_device ixp4xx_udc_device
= {
335 .name
= "pxa25x-udc",
338 .resource
= ixp4xx_udc_resources
,
340 .platform_data
= &ixp4xx_udc_info
,
344 static struct platform_device
*ixp4xx_devices
[] __initdata
= {
348 static struct resource ixp46x_i2c_resources
[] = {
352 .flags
= IORESOURCE_MEM
,
355 .start
= IRQ_IXP4XX_I2C
,
356 .end
= IRQ_IXP4XX_I2C
,
357 .flags
= IORESOURCE_IRQ
362 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
363 * we just use the same device name.
365 static struct platform_device ixp46x_i2c_controller
= {
366 .name
= "IOP3xx-I2C",
369 .resource
= ixp46x_i2c_resources
372 static struct platform_device
*ixp46x_devices
[] __initdata
= {
373 &ixp46x_i2c_controller
376 unsigned long ixp4xx_exp_bus_size
;
377 EXPORT_SYMBOL(ixp4xx_exp_bus_size
);
379 static int ixp4xx_gpio_direction_input(struct gpio_chip
*chip
, unsigned gpio
)
381 gpio_line_config(gpio
, IXP4XX_GPIO_IN
);
386 static int ixp4xx_gpio_direction_output(struct gpio_chip
*chip
, unsigned gpio
,
389 gpio_line_set(gpio
, level
);
390 gpio_line_config(gpio
, IXP4XX_GPIO_OUT
);
395 static int ixp4xx_gpio_get_value(struct gpio_chip
*chip
, unsigned gpio
)
399 gpio_line_get(gpio
, &value
);
404 static void ixp4xx_gpio_set_value(struct gpio_chip
*chip
, unsigned gpio
,
407 gpio_line_set(gpio
, value
);
410 static struct gpio_chip ixp4xx_gpio_chip
= {
411 .label
= "IXP4XX_GPIO_CHIP",
412 .direction_input
= ixp4xx_gpio_direction_input
,
413 .direction_output
= ixp4xx_gpio_direction_output
,
414 .get
= ixp4xx_gpio_get_value
,
415 .set
= ixp4xx_gpio_set_value
,
416 .to_irq
= ixp4xx_gpio_to_irq
,
421 void __init
ixp4xx_sys_init(void)
423 ixp4xx_exp_bus_size
= SZ_16M
;
425 platform_add_devices(ixp4xx_devices
, ARRAY_SIZE(ixp4xx_devices
));
427 gpiochip_add(&ixp4xx_gpio_chip
);
429 if (cpu_is_ixp46x()) {
432 platform_add_devices(ixp46x_devices
,
433 ARRAY_SIZE(ixp46x_devices
));
435 for (region
= 0; region
< 7; region
++) {
436 if((*(IXP4XX_EXP_REG(0x4 * region
)) & 0x200)) {
437 ixp4xx_exp_bus_size
= SZ_32M
;
443 printk("IXP4xx: Using %luMiB expansion bus window size\n",
444 ixp4xx_exp_bus_size
>> 20);
450 static u32 notrace
ixp4xx_read_sched_clock(void)
459 static cycle_t
ixp4xx_clocksource_read(struct clocksource
*c
)
464 unsigned long ixp4xx_timer_freq
= IXP4XX_TIMER_FREQ
;
465 EXPORT_SYMBOL(ixp4xx_timer_freq
);
466 static void __init
ixp4xx_clocksource_init(void)
468 setup_sched_clock(ixp4xx_read_sched_clock
, 32, ixp4xx_timer_freq
);
470 clocksource_mmio_init(NULL
, "OSTS", ixp4xx_timer_freq
, 200, 32,
471 ixp4xx_clocksource_read
);
477 static int ixp4xx_set_next_event(unsigned long evt
,
478 struct clock_event_device
*unused
)
480 unsigned long opts
= *IXP4XX_OSRT1
& IXP4XX_OST_RELOAD_MASK
;
482 *IXP4XX_OSRT1
= (evt
& ~IXP4XX_OST_RELOAD_MASK
) | opts
;
487 static void ixp4xx_set_mode(enum clock_event_mode mode
,
488 struct clock_event_device
*evt
)
490 unsigned long opts
= *IXP4XX_OSRT1
& IXP4XX_OST_RELOAD_MASK
;
491 unsigned long osrt
= *IXP4XX_OSRT1
& ~IXP4XX_OST_RELOAD_MASK
;
494 case CLOCK_EVT_MODE_PERIODIC
:
495 osrt
= LATCH
& ~IXP4XX_OST_RELOAD_MASK
;
496 opts
= IXP4XX_OST_ENABLE
;
498 case CLOCK_EVT_MODE_ONESHOT
:
499 /* period set by 'set next_event' */
501 opts
= IXP4XX_OST_ENABLE
| IXP4XX_OST_ONE_SHOT
;
503 case CLOCK_EVT_MODE_SHUTDOWN
:
504 opts
&= ~IXP4XX_OST_ENABLE
;
506 case CLOCK_EVT_MODE_RESUME
:
507 opts
|= IXP4XX_OST_ENABLE
;
509 case CLOCK_EVT_MODE_UNUSED
:
515 *IXP4XX_OSRT1
= osrt
| opts
;
518 static struct clock_event_device clockevent_ixp4xx
= {
519 .name
= "ixp4xx timer1",
520 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
523 .set_mode
= ixp4xx_set_mode
,
524 .set_next_event
= ixp4xx_set_next_event
,
527 static void __init
ixp4xx_clockevent_init(void)
529 clockevent_ixp4xx
.mult
= div_sc(IXP4XX_TIMER_FREQ
, NSEC_PER_SEC
,
530 clockevent_ixp4xx
.shift
);
531 clockevent_ixp4xx
.max_delta_ns
=
532 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx
);
533 clockevent_ixp4xx
.min_delta_ns
=
534 clockevent_delta2ns(0xf, &clockevent_ixp4xx
);
535 clockevent_ixp4xx
.cpumask
= cpumask_of(0);
537 clockevents_register_device(&clockevent_ixp4xx
);
540 void ixp4xx_restart(char mode
, const char *cmd
)
542 if ( 1 && mode
== 's') {
543 /* Jump into ROM at address 0 */
546 /* Use on-chip reset capability */
548 /* set the "key" register to enable access to
549 * "timer" and "enable" registers
551 *IXP4XX_OSWK
= IXP4XX_WDT_KEY
;
553 /* write 0 to the timer register for an immediate reset */
556 *IXP4XX_OSWE
= IXP4XX_WDT_RESET_ENABLE
| IXP4XX_WDT_COUNT_ENABLE
;
560 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
562 * In the case of using indirect PCI, we simply return the actual PCI
563 * address and our read/write implementation use that to drive the
564 * access registers. If something outside of PCI is ioremap'd, we
565 * fallback to the default.
568 static void __iomem
*ixp4xx_ioremap_caller(unsigned long addr
, size_t size
,
569 unsigned int mtype
, void *caller
)
571 if (!is_pci_memory(addr
))
572 return __arm_ioremap_caller(addr
, size
, mtype
, caller
);
574 return (void __iomem
*)addr
;
577 static void ixp4xx_iounmap(void __iomem
*addr
)
579 if (!is_pci_memory((__force u32
)addr
))
583 void __init
ixp4xx_init_early(void)
585 arch_ioremap_caller
= ixp4xx_ioremap_caller
;
586 arch_iounmap
= ixp4xx_iounmap
;
589 void __init
ixp4xx_init_early(void) {}