arch/arm/mach-k3/r5/j784s4/clk-data.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * J784S4 specific clock platform data
   4  *
   5  * This file is auto generated. Please do not hand edit and report any issues
   6  * to Bryan Brattlof <bb@ti.com>.
   7  *
   8  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include "k3-clk.h"
  13
  14 static const char * const gluelogic_hfosc0_clkout_parents[] = {
  15         "osc_19_2_mhz",
  16         "osc_20_mhz",
  17         "osc_24_mhz",
  18         "osc_25_mhz",
  19         "osc_26_mhz",
  20         "osc_27_mhz",
  21 };
  22
  23 static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
  24         "board_0_mcu_ospi0_dqs_out",
  25         "fss_mcu_0_ospi_0_ospi_oclk_clk",
  26 };
  27
  28 static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
  29         "board_0_mcu_ospi1_dqs_out",
  30         "fss_mcu_0_ospi_1_ospi_oclk_clk",
  31 };
  32
  33 static const char * const wkup_fref_clksel_out0_parents[] = {
  34         "gluelogic_hfosc0_clkout",
  35         "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
  36 };
  37
  38 static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
  39         "wkup_fref_clksel_out0",
  40         "hsdiv1_16fft_mcu_0_hsdivout0_clk",
  41 };
  42
  43 static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
  44         "hsdiv4_16fft_mcu_1_hsdivout4_clk",
  45         "hsdiv4_16fft_mcu_2_hsdivout4_clk",
  46 };
  47
  48 static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
  49         "hsdiv4_16fft_mcu_1_hsdivout4_clk",
  50         "hsdiv4_16fft_mcu_2_hsdivout4_clk",
  51 };
  52
  53 static const char * const wkup_gpio0_clksel_out0_parents[] = {
  54         "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
  55         "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
  56         "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
  57         "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
  58 };
  59
  60 static const char * const mcu_usart_clksel_out0_parents[] = {
  61         "hsdiv4_16fft_mcu_1_hsdivout3_clk",
  62         "postdiv3_16fft_main_1_hsdivout5_clk",
  63 };
  64
  65 static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
  66         "hsdiv4_16fft_mcu_1_hsdivout3_clk",
  67         "gluelogic_hfosc0_clkout",
  68 };
  69
  70 static const char * const main_pll_hfosc_sel_out0_parents[] = {
  71         "gluelogic_hfosc0_clkout",
  72         "board_0_hfosc1_clk_out",
  73 };
  74
  75 static const char * const main_pll_hfosc_sel_out1_parents[] = {
  76         "gluelogic_hfosc0_clkout",
  77         "board_0_hfosc1_clk_out",
  78 };
  79
  80 static const char * const main_pll_hfosc_sel_out12_parents[] = {
  81         "gluelogic_hfosc0_clkout",
  82         "board_0_hfosc1_clk_out",
  83 };
  84
  85 static const char * const main_pll_hfosc_sel_out19_parents[] = {
  86         "gluelogic_hfosc0_clkout",
  87         "board_0_hfosc1_clk_out",
  88 };
  89
  90 static const char * const main_pll_hfosc_sel_out2_parents[] = {
  91         "gluelogic_hfosc0_clkout",
  92         "board_0_hfosc1_clk_out",
  93 };
  94
  95 static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
  96         "gluelogic_hfosc0_clkout",
  97         "board_0_hfosc1_clk_out",
  98 };
  99
 100 static const char * const main_pll_hfosc_sel_out27_0_parents[] = {
 101         "gluelogic_hfosc0_clkout",
 102         "board_0_hfosc1_clk_out",
 103 };
 104
 105 static const char * const main_pll_hfosc_sel_out28_parents[] = {
 106         "gluelogic_hfosc0_clkout",
 107         "board_0_hfosc1_clk_out",
 108 };
 109
 110 static const char * const main_pll_hfosc_sel_out3_parents[] = {
 111         "gluelogic_hfosc0_clkout",
 112         "board_0_hfosc1_clk_out",
 113 };
 114
 115 static const char * const main_pll_hfosc_sel_out7_parents[] = {
 116         "gluelogic_hfosc0_clkout",
 117         "board_0_hfosc1_clk_out",
 118 };
 119
 120 static const char * const main_pll_hfosc_sel_out8_parents[] = {
 121         "gluelogic_hfosc0_clkout",
 122         "board_0_hfosc1_clk_out",
 123 };
 124
 125 static const char * const usb0_refclk_sel_out0_parents[] = {
 126         "gluelogic_hfosc0_clkout",
 127         "board_0_hfosc1_clk_out",
 128 };
 129
 130 static const char * const emmcsd1_lb_clksel_out0_parents[] = {
 131         "board_0_mmc1_clklb_out",
 132         "board_0_mmc1_clk_out",
 133 };
 134
 135 static const char * const mcu_clkout_mux_out0_parents[] = {
 136         "hsdiv4_16fft_mcu_2_hsdivout0_clk",
 137         "hsdiv4_16fft_mcu_2_hsdivout0_clk",
 138 };
 139
 140 static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
 141         "main_pll_hfosc_sel_out0",
 142         "hsdiv4_16fft_main_0_hsdivout0_clk",
 143 };
 144
 145 static const char * const dpi0_ext_clksel_out0_parents[] = {
 146         "hsdiv1_16fft_main_19_hsdivout0_clk",
 147         "board_0_vout0_extpclkin_out",
 148 };
 149
 150 static const char * const emmcsd_refclk_sel_out0_parents[] = {
 151         "hsdiv4_16fft_main_0_hsdivout2_clk",
 152         "hsdiv4_16fft_main_1_hsdivout2_clk",
 153         "hsdiv4_16fft_main_2_hsdivout2_clk",
 154         "hsdiv4_16fft_main_3_hsdivout2_clk",
 155 };
 156
 157 static const char * const emmcsd_refclk_sel_out1_parents[] = {
 158         "hsdiv4_16fft_main_0_hsdivout2_clk",
 159         "hsdiv4_16fft_main_1_hsdivout2_clk",
 160         "hsdiv4_16fft_main_2_hsdivout2_clk",
 161         "hsdiv4_16fft_main_3_hsdivout2_clk",
 162 };
 163
 164 static const char * const gtc_clk_mux_out0_parents[] = {
 165         "hsdiv4_16fft_main_3_hsdivout1_clk",
 166         "postdiv3_16fft_main_0_hsdivout6_clk",
 167         "board_0_mcu_cpts0_rft_clk_out",
 168         "board_0_cpts0_rft_clk_out",
 169         "board_0_mcu_ext_refclk0_out",
 170         "board_0_ext_refclk1_out",
 171         NULL,
 172         NULL,
 173         NULL,
 174         NULL,
 175         NULL,
 176         NULL,
 177         NULL,
 178         NULL,
 179         "hsdiv4_16fft_mcu_2_hsdivout1_clk",
 180         "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
 181 };
 182
 183 static const struct clk_data clk_list[] = {
 184         CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
 185         CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
 186         CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
 187         CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
 188         CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
 189         CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
 190         CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
 191         CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
 192         CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
 193         CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
 194         CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
 195         CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
 196         CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
 197         CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
 198         CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
 199         CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
 200         CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
 201         CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
 202         CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
 203         CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
 204         CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
 205         CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
 206         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
 207         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
 208         CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
 209         CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
 210         CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
 211         CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
 212         CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
 213         CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
 214         CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
 215         CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
 216         CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
 217         CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 218         CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 219         CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
 220         CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
 221         CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
 222         CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
 223         CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
 224         CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
 225         CLK_MUX("main_pll_hfosc_sel_out27_0", main_pll_hfosc_sel_out27_0_parents, 2, 0x430080ec, 0, 1, 0),
 226         CLK_MUX("main_pll_hfosc_sel_out28", main_pll_hfosc_sel_out28_parents, 2, 0x430080f0, 0, 1, 0),
 227         CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
 228         CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
 229         CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
 230         CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
 231         CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
 232         CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
 233         CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
 234         CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
 235         CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
 236         CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 237         CLK_FIXED_RATE("board_0_tck_out", 0, 0),
 238         CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
 239         CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 240         CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
 241         CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
 242         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000),
 243         CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
 244         CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
 245         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
 246         CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
 247         CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
 248         CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
 249         CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
 250         CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
 251         CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
 252         CLK_PLL("pllfracf2_ssmod_16fft_main_27_foutvcop_clk", "main_pll_hfosc_sel_out27_0", 0x69b000, 0),
 253         CLK_PLL("pllfracf2_ssmod_16fft_main_28_foutvcop_clk", "main_pll_hfosc_sel_out28", 0x69c000, 0),
 254         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0, 2000000000),
 255         CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
 256         CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
 257         CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
 258         CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
 259         CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
 260         CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
 261         CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
 262         CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
 263         CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
 264         CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
 265         CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0),
 266         CLK_DIV("hsdiv0_16fft_main_28_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_28_foutvcop_clk", 0x69c080, 0, 7, 0, 0),
 267         CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
 268         CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
 269         CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
 270         CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
 271         CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
 272         CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
 273         CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
 274         CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
 275         CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
 276         CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
 277         CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
 278         CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
 279         CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
 280         CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
 281         CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
 282         CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
 283         CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
 284         CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
 285         CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
 286         CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
 287         CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 288         CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 289         CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
 290 };
 291
 292 static const struct dev_clk soc_dev_clk_data[] = {
 293         DEV_CLK(198, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 294         DEV_CLK(198, 3, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 295         DEV_CLK(198, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 296         DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 297         DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 298         DEV_CLK(61, 0, "gtc_clk_mux_out0"),
 299         DEV_CLK(61, 1, "hsdiv4_16fft_main_3_hsdivout1_clk"),
 300         DEV_CLK(61, 2, "postdiv3_16fft_main_0_hsdivout6_clk"),
 301         DEV_CLK(61, 3, "board_0_mcu_cpts0_rft_clk_out"),
 302         DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"),
 303         DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
 304         DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
 305         DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
 306         DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 307         DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 308         DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
 309         DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 310         DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
 311         DEV_CLK(78, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
 312         DEV_CLK(78, 4, "gluelogic_hfosc0_clkout"),
 313         DEV_CLK(78, 5, "board_0_hfosc1_clk_out"),
 314         DEV_CLK(78, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 315         DEV_CLK(78, 8, "gluelogic_hfosc0_clkout"),
 316         DEV_CLK(78, 9, "board_0_hfosc1_clk_out"),
 317         DEV_CLK(78, 10, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
 318         DEV_CLK(78, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 319         DEV_CLK(78, 12, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 320         DEV_CLK(140, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 321         DEV_CLK(140, 2, "emmcsd_refclk_sel_out0"),
 322         DEV_CLK(140, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 323         DEV_CLK(140, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
 324         DEV_CLK(140, 5, "hsdiv4_16fft_main_2_hsdivout2_clk"),
 325         DEV_CLK(140, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
 326         DEV_CLK(141, 0, "emmcsd1_lb_clksel_out0"),
 327         DEV_CLK(141, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 328         DEV_CLK(141, 4, "emmcsd_refclk_sel_out1"),
 329         DEV_CLK(141, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 330         DEV_CLK(141, 6, "hsdiv4_16fft_main_1_hsdivout2_clk"),
 331         DEV_CLK(141, 7, "hsdiv4_16fft_main_2_hsdivout2_clk"),
 332         DEV_CLK(141, 8, "hsdiv4_16fft_main_3_hsdivout2_clk"),
 333         DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
 334         DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 335         DEV_CLK(149, 0, "mcu_usart_clksel_out0"),
 336         DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
 337         DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
 338         DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 339         DEV_CLK(157, 174, "mcu_clkout_mux_out0"),
 340         DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 341         DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 342         DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
 343         DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
 344         DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 345         DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 346         DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 347         DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 348         DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 349         DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 350         DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 351         DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 352         DEV_CLK(157, 359, "dpi0_ext_clksel_out0"),
 353         DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"),
 354         DEV_CLK(160, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 355         DEV_CLK(160, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 356         DEV_CLK(160, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 357         DEV_CLK(160, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 358         DEV_CLK(160, 8, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 359         DEV_CLK(161, 0, "board_0_mcu_ospi0_dqs_out"),
 360         DEV_CLK(161, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 361         DEV_CLK(161, 2, "mcu_ospi0_iclk_sel_out0"),
 362         DEV_CLK(161, 3, "board_0_mcu_ospi0_dqs_out"),
 363         DEV_CLK(161, 4, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 364         DEV_CLK(161, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 365         DEV_CLK(161, 7, "mcu_ospi_ref_clk_sel_out0"),
 366         DEV_CLK(161, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
 367         DEV_CLK(161, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 368         DEV_CLK(162, 0, "board_0_mcu_ospi1_dqs_out"),
 369         DEV_CLK(162, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 370         DEV_CLK(162, 2, "mcu_ospi1_iclk_sel_out0"),
 371         DEV_CLK(162, 3, "board_0_mcu_ospi1_dqs_out"),
 372         DEV_CLK(162, 4, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 373         DEV_CLK(162, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 374         DEV_CLK(162, 7, "mcu_ospi_ref_clk_sel_out1"),
 375         DEV_CLK(162, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
 376         DEV_CLK(162, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 377         DEV_CLK(167, 0, "wkup_gpio0_clksel_out0"),
 378         DEV_CLK(178, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 379         DEV_CLK(178, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 380         DEV_CLK(188, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 381         DEV_CLK(188, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 382         DEV_CLK(191, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 383         DEV_CLK(191, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
 384         DEV_CLK(191, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 385         DEV_CLK(191, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 386         DEV_CLK(192, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 387         DEV_CLK(192, 1, "hsdiv0_16fft_main_26_hsdivout0_clk"),
 388         DEV_CLK(192, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 389         DEV_CLK(192, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 390         DEV_CLK(193, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 391         DEV_CLK(193, 1, "hsdiv0_16fft_main_27_hsdivout0_clk"),
 392         DEV_CLK(193, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 393         DEV_CLK(193, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 394         DEV_CLK(194, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 395         DEV_CLK(194, 1, "hsdiv0_16fft_main_28_hsdivout0_clk"),
 396         DEV_CLK(194, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 397         DEV_CLK(194, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 398         DEV_CLK(201, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 399         DEV_CLK(201, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 400         DEV_CLK(243, 0, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
 401         DEV_CLK(243, 1, "gluelogic_hfosc0_clkout"),
 402         DEV_CLK(243, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 403         DEV_CLK(279, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 404         DEV_CLK(279, 1, "board_0_wkup_i2c0_scl_out"),
 405         DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"),
 406         DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
 407         DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"),
 408         DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"),
 409         DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 410         DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"),
 411         DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 412         DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 413         DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 414         DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"),
 415         DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 416         DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 417         DEV_CLK(398, 21, "usb0_refclk_sel_out0"),
 418         DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"),
 419         DEV_CLK(398, 23, "board_0_hfosc1_clk_out"),
 420         DEV_CLK(398, 28, "board_0_tck_out"),
 421 };
 422
 423 const struct ti_k3_clk_platdata j784s4_clk_platdata = {
 424         .clk_list = clk_list,
 425         .clk_list_cnt = ARRAY_SIZE(clk_list),
 426         .soc_dev_clk_data = soc_dev_clk_data,
 427         .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
 428 };