arch/arm/mach-keystone/init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone2: Architecture initialization
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <ns16550.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/msmc.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/psc_defs.h>
  17
  18 #define MAX_PCI_PORTS           2
  19 enum pci_mode   {
  20         ENDPOINT,
  21         LEGACY_ENDPOINT,
  22         ROOTCOMPLEX,
  23 };
  24
  25 #define DEVCFG_MODE_MASK                (BIT(2) | BIT(1))
  26 #define DEVCFG_MODE_SHIFT               1
  27
  28 void chip_configuration_unlock(void)
  29 {
  30         __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  31         __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  32 }
  33
  34 #ifdef CONFIG_SOC_K2L
  35 void osr_init(void)
  36 {
  37         u32 i;
  38         u32 j;
  39         u32 val;
  40         u32 base = KS2_OSR_CFG_BASE;
  41         u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  42
  43         /* Enable the OSR clock domain */
  44         psc_enable_module(KS2_LPSC_OSR);
  45
  46         /* Disable OSR ECC check for all the ram banks */
  47         for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  48                 val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  49                         (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  50
  51                 writel(val , base + KS2_OSR_ECC_VEC);
  52
  53                 /**
  54                  * wait till read is done.
  55                  * Print should be added after earlyprintk support is added.
  56                  */
  57                 for (j = 0; j < 10000; j++) {
  58                         val = readl(base + KS2_OSR_ECC_VEC);
  59                         if (val & KS2_OSR_ECC_VEC_RD_DONE)
  60                                 break;
  61                 }
  62
  63                 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  64                                                 KS2_OSR_ECC_CTRL_CHK;
  65
  66                 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  67                 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  68         }
  69
  70         /* Reset OSR memory to all zeros */
  71         for (i = 0; i < KS2_OSR_SIZE; i += 4)
  72                 writel(0, KS2_OSR_DATA_BASE + i);
  73
  74         /* Enable OSR ECC check for all the ram banks */
  75         for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  76                 writel(ecc_ctrl[i] |
  77                        KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  78 }
  79 #endif
  80
  81 /* Function to set up PCIe mode */
  82 static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
  83 {
  84         u32 val = __raw_readl(KS2_DEVCFG);
  85
  86         if (pcie_port >= MAX_PCI_PORTS)
  87                 return;
  88
  89         /**
  90          * each pci port has two bits for mode and it starts at
  91          * bit 1. So use port number to get the right bit position.
  92          */
  93         pcie_port <<= 1;
  94         val &= ~(DEVCFG_MODE_MASK << pcie_port);
  95         val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  96         __raw_writel(val, KS2_DEVCFG);
  97 }
  98
  99 static void msmc_k2hkle_common_setup(void)
 100 {
 101         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 102         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
 103         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
 104         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
 105         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
 106         msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 107 }
 108
 109 static void msmc_k2hk_setup(void)
 110 {
 111         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
 112         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
 113         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 114         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
 115         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
 116         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
 117         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
 118         msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 119 }
 120
 121 static inline void msmc_k2l_setup(void)
 122 {
 123         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
 124         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
 125         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 126         msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
 127 }
 128
 129 static inline void msmc_k2e_setup(void)
 130 {
 131         msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
 132         msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 133         msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
 134 }
 135
 136 static void msmc_k2g_setup(void)
 137 {
 138         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 139         msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
 140         msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
 141         msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
 142         msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
 143         msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
 144         msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
 145         msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
 146         msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
 147         msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
 148         msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
 149         msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 150 }
 151
 152 int arch_cpu_init(void)
 153 {
 154         chip_configuration_unlock();
 155         icache_enable();
 156
 157         if (cpu_is_k2g()) {
 158                 msmc_k2g_setup();
 159         } else {
 160                 msmc_k2hkle_common_setup();
 161                 if (cpu_is_k2e())
 162                         msmc_k2e_setup();
 163                 else if (cpu_is_k2l())
 164                         msmc_k2l_setup();
 165                 else
 166                         msmc_k2hk_setup();
 167         }
 168
 169         /* Initialize the PCIe-0 to work as Root Complex */
 170         config_pcie_mode(0, ROOTCOMPLEX);
 171 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 172         /* Initialize the PCIe-1 to work as Root Complex */
 173         config_pcie_mode(1, ROOTCOMPLEX);
 174 #endif
 175 #ifdef CONFIG_SOC_K2L
 176         osr_init();
 177 #endif
 178
 179         /*
 180          * just initialise the COM2 port so that TI specific
 181          * UART register PWREMU_MGMT is initialized. Linux UART
 182          * driver doesn't handle this.
 183          */
 184 #ifndef CONFIG_DM_SERIAL
 185         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
 186                      CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 187 #endif
 188
 189         return 0;
 190 }
 191
 192 void reset_cpu(ulong addr)
 193 {
 194         volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
 195         u32 tmp;
 196
 197         tmp = *rstctrl & KS2_RSTCTRL_MASK;
 198         *rstctrl = tmp | KS2_RSTCTRL_KEY;
 199
 200         *rstctrl &= KS2_RSTCTRL_SWRST;
 201
 202         for (;;)
 203                 ;
 204 }
 205
 206 void enable_caches(void)
 207 {
 208 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 209         /* Enable D-cache. I-cache is already enabled in start.S */
 210         dcache_enable();
 211 #endif
 212 }
 213
 214 #if defined(CONFIG_DISPLAY_CPUINFO)
 215 int print_cpuinfo(void)
 216 {
 217         u16 cpu = get_part_number();
 218         u8 rev = cpu_revision();
 219
 220         puts("CPU: ");
 221         switch (cpu) {
 222         case CPU_66AK2Hx:
 223                 puts("66AK2Hx SR");
 224                 break;
 225         case CPU_66AK2Lx:
 226                 puts("66AK2Lx SR");
 227                 break;
 228         case CPU_66AK2Ex:
 229                 puts("66AK2Ex SR");
 230                 break;
 231         case CPU_66AK2Gx:
 232                 puts("66AK2Gx");
 233 #ifdef CONFIG_SOC_K2G
 234                 {
 235                         int speed = get_max_arm_speed(speeds);
 236                         if (speed == SPD1000)
 237                                 puts("-100 ");
 238                         else if (speed == SPD600)
 239                                 puts("-60 ");
 240                         else
 241                                 puts("-xx ");
 242                 }
 243 #endif
 244                 puts("SR");
 245                 break;
 246         default:
 247                 puts("Unknown\n");
 248         }
 249
 250         if (rev == 2)
 251                 puts("2.0\n");
 252         else if (rev == 1)
 253                 puts("1.1\n");
 254         else if (rev == 0)
 255                 puts("1.0\n");
 256         else if (rev == 8)
 257                 puts("1.0\n");
 258         return 0;
 259 }
 260 #endif