arch/arm/mach-kirkwood/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <cpu_func.h>
  11 #include <env.h>
  12 #include <netdev.h>
  13 #include <asm/cache.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/soc.h>
  17 #include <mvebu_mmc.h>
  18
  19 void reset_cpu(unsigned long ignored)
  20 {
  21         struct kwcpu_registers *cpureg =
  22             (struct kwcpu_registers *)KW_CPU_REG_BASE;
  23
  24         writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  25                 &cpureg->rstoutn_mask);
  26         writel(readl(&cpureg->sys_soft_rst) | 1,
  27                 &cpureg->sys_soft_rst);
  28         while (1) ;
  29 }
  30
  31 /*
  32  * Window Size
  33  * Used with the Base register to set the address window size and location.
  34  * Must be programmed from LSB to MSB as sequence of ones followed by
  35  * sequence of zeros. The number of ones specifies the size of the window in
  36  * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  37  * NOTE: A value of 0x0 specifies 64-KByte size.
  38  */
  39 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
  40 {
  41         int i;
  42         unsigned int j = 0;
  43         u32 val = sizeval >> 1;
  44
  45         for (i = 0; val >= 0x10000; i++) {
  46                 j |= (1 << i);
  47                 val = val >> 1;
  48         }
  49         return (0x0000ffff & j);
  50 }
  51
  52 static struct mbus_win windows[] = {
  53         /* Window 0: PCIE MEM address space */
  54         { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
  55           KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
  56
  57         /* Window 1: PCIE IO address space */
  58         { KW_DEFADR_PCI_IO, 1024 * 64,
  59           KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
  60
  61         /* Window 2: NAND Flash address space */
  62         { KW_DEFADR_NANDF, 1024 * 1024 * 128,
  63           KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
  64
  65         /* Window 3: SPI Flash address space */
  66         { KW_DEFADR_SPIF, 1024 * 1024 * 128,
  67           KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
  68
  69         /* Window 4: BOOT Memory address space */
  70         { KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
  71           KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
  72
  73         /* Window 5: Security SRAM address space */
  74         { KW_DEFADR_SASRAM, 1024 * 64,
  75           KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
  76 };
  77
  78 /*
  79  * SYSRSTn Duration Counter Support
  80  *
  81  * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
  82  * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
  83  * The SYSRSTn duration counter is useful for implementing a manufacturer
  84  * or factory reset. Upon a long reset assertion that is greater than a
  85  * pre-configured environment variable value for sysrstdelay,
  86  * The counter value is stored in the SYSRSTn Length Counter Register
  87  * The counter is based on the 25-MHz reference clock (40ns)
  88  * It is a 29-bit counter, yielding a maximum counting duration of
  89  * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
  90  * it remains at this value until counter reset is triggered by setting
  91  * bit 31 of KW_REG_SYSRST_CNT
  92  */
  93 static void kw_sysrst_action(void)
  94 {
  95         int ret;
  96         char *s = env_get("sysrstcmd");
  97
  98         if (!s) {
  99                 debug("Error.. %s failed, check sysrstcmd\n",
 100                         __FUNCTION__);
 101                 return;
 102         }
 103
 104         debug("Starting %s process...\n", __FUNCTION__);
 105         ret = run_command(s, 0);
 106         if (ret != 0)
 107                 debug("Error.. %s failed\n", __FUNCTION__);
 108         else
 109                 debug("%s process finished\n", __FUNCTION__);
 110 }
 111
 112 static void kw_sysrst_check(void)
 113 {
 114         u32 sysrst_cnt, sysrst_dly;
 115         char *s;
 116
 117         /*
 118          * no action if sysrstdelay environment variable is not defined
 119          */
 120         s = env_get("sysrstdelay");
 121         if (s == NULL)
 122                 return;
 123
 124         /* read sysrstdelay value */
 125         sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
 126
 127         /* read SysRst Length counter register (bits 28:0) */
 128         sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
 129         debug("H/w Rst hold time: %d.%d secs\n",
 130                 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
 131                 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
 132
 133         /* clear the counter for next valid read*/
 134         writel(1 << 31, KW_REG_SYSRST_CNT);
 135
 136         /*
 137          * sysrst_action:
 138          * if H/w Reset key is pressed and hold for time
 139          * more than sysrst_dly in seconds
 140          */
 141         if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
 142                 kw_sysrst_action();
 143 }
 144
 145 #if defined(CONFIG_DISPLAY_CPUINFO)
 146 int print_cpuinfo(void)
 147 {
 148         char *rev = "??";
 149         u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
 150         u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
 151
 152         if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
 153                 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
 154                 return -1;
 155         }
 156
 157         switch (revid) {
 158         case 0:
 159                 if (devid == 0x6281)
 160                         rev = "Z0";
 161                 else if (devid == 0x6282)
 162                         rev = "A0";
 163                 break;
 164         case 1:
 165                 rev = "A1";
 166                 break;
 167         case 2:
 168                 rev = "A0";
 169                 break;
 170         case 3:
 171                 rev = "A1";
 172                 break;
 173         default:
 174                 break;
 175         }
 176
 177         printf("SoC:   Kirkwood 88F%04x_%s\n", devid, rev);
 178         return 0;
 179 }
 180 #endif /* CONFIG_DISPLAY_CPUINFO */
 181
 182 #ifdef CONFIG_ARCH_CPU_INIT
 183 int arch_cpu_init(void)
 184 {
 185         u32 reg;
 186         struct kwcpu_registers *cpureg =
 187                 (struct kwcpu_registers *)KW_CPU_REG_BASE;
 188
 189         /* Linux expects the internal registers to be at 0xf1000000 */
 190         writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
 191
 192         /* Enable and invalidate L2 cache in write through mode */
 193         writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
 194         invalidate_l2_cache();
 195
 196 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
 197         /*
 198          * Configures the I/O voltage of the pads connected to Egigabit
 199          * Ethernet interface to 1.8V
 200          * By default it is set to 3.3V
 201          */
 202         reg = readl(KW_REG_MPP_OUT_DRV_REG);
 203         reg |= (1 << 7);
 204         writel(reg, KW_REG_MPP_OUT_DRV_REG);
 205 #endif
 206 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
 207         /*
 208          * Set egiga port0/1 in normal functional mode
 209          * This is required becasue on kirkwood by default ports are in reset mode
 210          * OS egiga driver may not have provision to set them in normal mode
 211          * and if u-boot is build without network support, network may fail at OS level
 212          */
 213         reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
 214         reg &= ~(1 << 4);       /* Clear PortReset Bit */
 215         writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
 216         reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
 217         reg &= ~(1 << 4);       /* Clear PortReset Bit */
 218         writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
 219 #endif
 220 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
 221         /*
 222          * Enable PCI Express Port0
 223          */
 224         reg = readl(&cpureg->ctrl_stat);
 225         reg |= (1 << 0);        /* Set PEX0En Bit */
 226         writel(reg, &cpureg->ctrl_stat);
 227 #endif
 228         return 0;
 229 }
 230 #endif /* CONFIG_ARCH_CPU_INIT */
 231
 232 /*
 233  * SOC specific misc init
 234  */
 235 #if defined(CONFIG_ARCH_MISC_INIT)
 236 int arch_misc_init(void)
 237 {
 238         volatile u32 temp;
 239
 240         /*CPU streaming & write allocate */
 241         temp = readfr_extra_feature_reg();
 242         temp &= ~(1 << 28);     /* disable wr alloc */
 243         writefr_extra_feature_reg(temp);
 244
 245         temp = readfr_extra_feature_reg();
 246         temp &= ~(1 << 29);     /* streaming disabled */
 247         writefr_extra_feature_reg(temp);
 248
 249         /* L2Cache settings */
 250         temp = readfr_extra_feature_reg();
 251         /* Disable L2C pre fetch - Set bit 24 */
 252         temp |= (1 << 24);
 253         /* enable L2C - Set bit 22 */
 254         temp |= (1 << 22);
 255         writefr_extra_feature_reg(temp);
 256
 257         /* Change reset vector to address 0x0 */
 258         temp = get_cr();
 259         set_cr(temp & ~CR_V);
 260
 261         /* Configure mbus windows */
 262         mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
 263
 264         /* checks and execute resset to factory event */
 265         kw_sysrst_check();
 266
 267         return 0;
 268 }
 269 #endif /* CONFIG_ARCH_MISC_INIT */
 270
 271 #ifdef CONFIG_MVGBE
 272 int cpu_eth_init(bd_t *bis)
 273 {
 274         mvgbe_initialize(bis);
 275         return 0;
 276 }
 277 #endif
 278
 279 #ifdef CONFIG_MVEBU_MMC
 280 int board_mmc_init(bd_t *bis)
 281 {
 282         mvebu_mmc_init(bis);
 283         return 0;
 284 }
 285 #endif /* CONFIG_MVEBU_MMC */