arch/arm/mach-meson/board-gx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
   4  * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/boot.h>
  11 #include <asm/arch/eth.h>
  12 #include <asm/arch/gx.h>
  13 #include <asm/arch/mem.h>
  14 #include <asm/arch/meson-vpu.h>
  15 #include <asm/io.h>
  16 #include <asm/armv8/mmu.h>
  17 #include <linux/sizes.h>
  18 #include <usb.h>
  19 #include <linux/usb/otg.h>
  20 #include <asm/arch/usb-gx.h>
  21 #include <usb/dwc2_udc.h>
  22 #include <clk.h>
  23 #include <phy.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int meson_get_boot_device(void)
  28 {
  29         return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
  30 }
  31
  32 /* Configure the reserved memory zones exported by the secure registers
  33  * into EFI and DTB reserved memory entries.
  34  */
  35 void meson_init_reserved_memory(void *fdt)
  36 {
  37         u64 bl31_size, bl31_start;
  38         u64 bl32_size, bl32_start;
  39         u32 reg;
  40
  41         /*
  42          * Get ARM Trusted Firmware reserved memory zones in :
  43          * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  44          * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  45          * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  46          */
  47         reg = readl(GX_AO_SEC_GP_CFG3);
  48
  49         bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
  50                         >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  51         bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  52
  53         bl31_start = readl(GX_AO_SEC_GP_CFG5);
  54         bl32_start = readl(GX_AO_SEC_GP_CFG4);
  55
  56         /*
  57          * Early Meson GX Firmware revisions did not provide the reserved
  58          * memory zones in the registers, keep fixed memory zone handling.
  59          */
  60         if (IS_ENABLED(CONFIG_MESON_GX) &&
  61             !reg && !bl31_start && !bl32_start) {
  62                 bl31_start = 0x10000000;
  63                 bl31_size = 0x200000;
  64         }
  65
  66         /* Add first 16MiB reserved zone */
  67         meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
  68
  69         /* Add BL31 reserved zone */
  70         if (bl31_start && bl31_size)
  71                 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  72
  73         /* Add BL32 reserved zone */
  74         if (bl32_start && bl32_size)
  75                 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  76
  77 #if defined(CONFIG_VIDEO_MESON)
  78         meson_vpu_rsv_fb(fdt);
  79 #endif
  80 }
  81
  82 phys_size_t get_effective_memsize(void)
  83 {
  84         /* Size is reported in MiB, convert it in bytes */
  85         return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
  86                         >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
  87 }
  88
  89 static struct mm_region gx_mem_map[] = {
  90         {
  91                 .virt = 0x0UL,
  92                 .phys = 0x0UL,
  93                 .size = 0xc0000000UL,
  94                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  95                          PTE_BLOCK_INNER_SHARE
  96         }, {
  97                 .virt = 0xc0000000UL,
  98                 .phys = 0xc0000000UL,
  99                 .size = 0x30000000UL,
 100                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 101                          PTE_BLOCK_NON_SHARE |
 102                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 103         }, {
 104                 /* List terminator */
 105                 0,
 106         }
 107 };
 108
 109 struct mm_region *mem_map = gx_mem_map;
 110
 111 /* Configure the Ethernet MAC with the requested interface mode
 112  * with some optional flags.
 113  */
 114 void meson_eth_init(phy_interface_t mode, unsigned int flags)
 115 {
 116         switch (mode) {
 117         case PHY_INTERFACE_MODE_RGMII:
 118         case PHY_INTERFACE_MODE_RGMII_ID:
 119         case PHY_INTERFACE_MODE_RGMII_RXID:
 120         case PHY_INTERFACE_MODE_RGMII_TXID:
 121                 /* Set RGMII mode */
 122                 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
 123                              GX_ETH_REG_0_TX_PHASE(1) |
 124                              GX_ETH_REG_0_TX_RATIO(4) |
 125                              GX_ETH_REG_0_PHY_CLK_EN |
 126                              GX_ETH_REG_0_CLK_EN);
 127
 128                 /* Reset to external PHY */
 129                 if(!IS_ENABLED(CONFIG_MESON_GXBB))
 130                         writel(0x2009087f, GX_ETH_REG_3);
 131
 132                 break;
 133
 134         case PHY_INTERFACE_MODE_RMII:
 135                 /* Set RMII mode */
 136                 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
 137                                          GX_ETH_REG_0_CLK_EN);
 138
 139                 /* Use GXL RMII Internal PHY (also on GXM) */
 140                 if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
 141                         if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
 142                                 writel(0x10110181, GX_ETH_REG_2);
 143                                 writel(0xe40908ff, GX_ETH_REG_3);
 144                         } else
 145                                 writel(0x2009087f, GX_ETH_REG_3);
 146                 }
 147
 148                 break;
 149
 150         default:
 151                 printf("Invalid Ethernet interface mode\n");
 152                 return;
 153         }
 154
 155         /* Enable power gate */
 156         clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
 157 }
 158
 159 #if CONFIG_IS_ENABLED(USB_XHCI_DWC3_OF_SIMPLE) && \
 160         CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
 161 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
 162 static struct phy usb_phys[2];
 163
 164 int board_usb_init(int index, enum usb_init_type init)
 165 {
 166         struct ofnode_phandle_args args;
 167         struct udevice *clk_dev;
 168         ofnode dwc2_node;
 169         struct clk clk;
 170         int ret, i;
 171         u32 val;
 172
 173         /* find the dwc2 node */
 174         dwc2_node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
 175         if (!ofnode_valid(dwc2_node)) {
 176                 debug("Not found dwc2 node\n");
 177                 return -ENODEV;
 178         }
 179
 180         if (!ofnode_is_available(dwc2_node)) {
 181                 debug("dwc2 is disabled in the device tree\n");
 182                 return -ENODEV;
 183         }
 184
 185         /* get the PHYs */
 186         for (i = 0; i < 2; i++) {
 187                 ret = generic_phy_get_by_index_nodev(dwc2_node, i,
 188                                                      &usb_phys[i]);
 189                 if (ret && ret != -ENOENT) {
 190                         pr_err("Failed to get USB PHY%d for %s\n",
 191                                i, ofnode_get_name(dwc2_node));
 192                         return ret;
 193                 }
 194         }
 195
 196         for (i = 0; i < 2; i++) {
 197                 ret = generic_phy_init(&usb_phys[i]);
 198                 if (ret) {
 199                         pr_err("Can't init USB PHY%d for %s\n",
 200                                i, ofnode_get_name(dwc2_node));
 201                         return ret;
 202                 }
 203         }
 204
 205         for (i = 0; i < 2; i++) {
 206                 ret = generic_phy_power_on(&usb_phys[i]);
 207                 if (ret) {
 208                         pr_err("Can't power USB PHY%d for %s\n",
 209                                i, ofnode_get_name(dwc2_node));
 210                         return ret;
 211                 }
 212         }
 213
 214         phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_PERIPHERAL);
 215         phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_PERIPHERAL);
 216
 217         meson_gx_dwc2_data.regs_otg = ofnode_get_addr(dwc2_node);
 218         if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
 219                 debug("usbotg: can't get base address\n");
 220                 return -ENODATA;
 221         }
 222
 223         /* Enable clock */
 224         ret = ofnode_parse_phandle_with_args(dwc2_node, "clocks",
 225                                              "#clock-cells", 0, 0, &args);
 226         if (ret) {
 227                 debug("usbotg has no clocks defined in the device tree\n");
 228                 return ret;
 229         }
 230
 231         ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &clk_dev);
 232         if (ret)
 233                 return ret;
 234
 235         if (args.args_count != 1) {
 236                 debug("Can't find clock ID in the device tree\n");
 237                 return -ENODATA;
 238         }
 239
 240         clk.dev = clk_dev;
 241         clk.id = args.args[0];
 242
 243         ret = clk_enable(&clk);
 244         if (ret) {
 245                 debug("Failed to enable usbotg clock\n");
 246                 return ret;
 247         }
 248
 249         ofnode_read_u32(dwc2_node, "g-rx-fifo-size", &val);
 250         meson_gx_dwc2_data.rx_fifo_sz = val;
 251         ofnode_read_u32(dwc2_node, "g-np-tx-fifo-size", &val);
 252         meson_gx_dwc2_data.np_tx_fifo_sz = val;
 253         ofnode_read_u32(dwc2_node, "g-tx-fifo-size", &val);
 254         meson_gx_dwc2_data.tx_fifo_sz = val;
 255
 256         return dwc2_udc_probe(&meson_gx_dwc2_data);
 257 }
 258
 259 int board_usb_cleanup(int index, enum usb_init_type init)
 260 {
 261         int i;
 262
 263         phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_HOST);
 264         phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_HOST);
 265
 266         for (i = 0; i < 2; i++)
 267                 usb_phys[i].dev = NULL;
 268
 269         return 0;
 270 }
 271 #endif