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Prepare v2023.04
[thirdparty/u-boot.git] / arch / arm / mach-mvebu / cpu.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <ahci.h>
8 #include <cpu_func.h>
9 #include <init.h>
10 #include <linux/bitops.h>
11 #include <linux/delay.h>
12 #include <linux/mbus.h>
13 #include <asm/io.h>
14 #include <asm/pl310.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17 #include <asm/spl.h>
18 #include <sdhci.h>
19
20 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
21 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
22
23 static const struct mbus_win windows[] = {
24 /* SPI */
25 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
27
28 /* NOR */
29 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
30 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
31
32 #ifdef CONFIG_ARMADA_MSYS
33 /* DFX */
34 { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
35 #endif
36 };
37
38 void lowlevel_init(void)
39 {
40 /*
41 * Dummy implementation, we only need LOWLEVEL_INIT
42 * on Armada to configure CP15 in start.S / cpu_init_cp15()
43 */
44 }
45
46 void reset_cpu(void)
47 {
48 struct mvebu_system_registers *reg =
49 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
50
51 writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
52 writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
53 while (1)
54 ;
55 }
56
57 u32 get_boot_device(void)
58 {
59 u32 val;
60 u32 boot_device;
61
62 /*
63 * First check, if UART boot-mode is active. This can only
64 * be done, via the bootrom error register. Here the
65 * MSB marks if the UART mode is active.
66 */
67 val = readl(BOOTROM_ERR_REG);
68 boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
69 debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
70 if (boot_device == BOOTROM_ERR_MODE_UART)
71 return BOOT_DEVICE_UART;
72
73 #ifdef CONFIG_ARMADA_38X
74 /*
75 * If the bootrom error code contains any other than zeros it's an
76 * error condition and the bootROM has fallen back to UART boot
77 */
78 boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
79 if (boot_device)
80 return BOOT_DEVICE_UART;
81 #endif
82
83 /*
84 * Now check the SAR register for the strapped boot-device
85 */
86 val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */
87 boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
88 debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
89 switch (boot_device) {
90 #ifdef BOOT_FROM_NAND
91 case BOOT_FROM_NAND:
92 return BOOT_DEVICE_NAND;
93 #endif
94 #ifdef BOOT_FROM_MMC
95 case BOOT_FROM_MMC:
96 case BOOT_FROM_MMC_ALT:
97 return BOOT_DEVICE_MMC1;
98 #endif
99 case BOOT_FROM_UART:
100 #ifdef BOOT_FROM_UART_ALT
101 case BOOT_FROM_UART_ALT:
102 #endif
103 return BOOT_DEVICE_UART;
104 #ifdef BOOT_FROM_SATA
105 case BOOT_FROM_SATA:
106 case BOOT_FROM_SATA_ALT:
107 return BOOT_DEVICE_SATA;
108 #endif
109 case BOOT_FROM_SPI:
110 return BOOT_DEVICE_SPI;
111 default:
112 return BOOT_DEVICE_BOOTROM;
113 };
114 }
115
116 #if defined(CONFIG_DISPLAY_CPUINFO)
117
118 #if defined(CONFIG_ARMADA_375)
119 /* SAR frequency values for Armada 375 */
120 static const struct sar_freq_modes sar_freq_tab[] = {
121 { 0, 0x0, 266, 133, 266 },
122 { 1, 0x0, 333, 167, 167 },
123 { 2, 0x0, 333, 167, 222 },
124 { 3, 0x0, 333, 167, 333 },
125 { 4, 0x0, 400, 200, 200 },
126 { 5, 0x0, 400, 200, 267 },
127 { 6, 0x0, 400, 200, 400 },
128 { 7, 0x0, 500, 250, 250 },
129 { 8, 0x0, 500, 250, 334 },
130 { 9, 0x0, 500, 250, 500 },
131 { 10, 0x0, 533, 267, 267 },
132 { 11, 0x0, 533, 267, 356 },
133 { 12, 0x0, 533, 267, 533 },
134 { 13, 0x0, 600, 300, 300 },
135 { 14, 0x0, 600, 300, 400 },
136 { 15, 0x0, 600, 300, 600 },
137 { 16, 0x0, 666, 333, 333 },
138 { 17, 0x0, 666, 333, 444 },
139 { 18, 0x0, 666, 333, 666 },
140 { 19, 0x0, 800, 400, 267 },
141 { 20, 0x0, 800, 400, 400 },
142 { 21, 0x0, 800, 400, 534 },
143 { 22, 0x0, 900, 450, 300 },
144 { 23, 0x0, 900, 450, 450 },
145 { 24, 0x0, 900, 450, 600 },
146 { 25, 0x0, 1000, 500, 500 },
147 { 26, 0x0, 1000, 500, 667 },
148 { 27, 0x0, 1000, 333, 500 },
149 { 28, 0x0, 400, 400, 400 },
150 { 29, 0x0, 1100, 550, 550 },
151 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
152 };
153 #elif defined(CONFIG_ARMADA_38X)
154 /* SAR frequency values for Armada 38x */
155 static const struct sar_freq_modes sar_freq_tab[] = {
156 { 0x0, 0x0, 666, 333, 333 },
157 { 0x2, 0x0, 800, 400, 400 },
158 { 0x4, 0x0, 1066, 533, 533 },
159 { 0x6, 0x0, 1200, 600, 600 },
160 { 0x8, 0x0, 1332, 666, 666 },
161 { 0xc, 0x0, 1600, 800, 800 },
162 { 0x10, 0x0, 1866, 933, 933 },
163 { 0x13, 0x0, 2000, 1000, 933 },
164 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
165 };
166 #elif defined(CONFIG_ARMADA_MSYS)
167 static const struct sar_freq_modes sar_freq_tab[] = {
168 { 0x0, 0x0, 400, 400, 400 },
169 { 0x2, 0x0, 667, 333, 667 },
170 { 0x3, 0x0, 800, 400, 800 },
171 { 0x5, 0x0, 800, 400, 800 },
172 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
173 };
174 #else
175 /* SAR frequency values for Armada XP */
176 static const struct sar_freq_modes sar_freq_tab[] = {
177 { 0xa, 0x5, 800, 400, 400 },
178 { 0x1, 0x5, 1066, 533, 533 },
179 { 0x2, 0x5, 1200, 600, 600 },
180 { 0x2, 0x9, 1200, 600, 400 },
181 { 0x3, 0x5, 1333, 667, 667 },
182 { 0x4, 0x5, 1500, 750, 750 },
183 { 0x4, 0x9, 1500, 750, 500 },
184 { 0xb, 0x9, 1600, 800, 533 },
185 { 0xb, 0xa, 1600, 800, 640 },
186 { 0xb, 0x5, 1600, 800, 800 },
187 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
188 };
189 #endif
190
191 void get_sar_freq(struct sar_freq_modes *sar_freq)
192 {
193 u32 val;
194 u32 freq;
195 int i;
196
197 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
198 val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */
199 #else
200 val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */
201 #endif
202 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
203 #if defined(SAR2_CPU_FREQ_MASK)
204 /*
205 * Shift CPU0 clock frequency select bit from SAR2 register
206 * into correct position
207 */
208 freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
209 >> SAR2_CPU_FREQ_OFFS) << 3;
210 #endif
211 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
212 if (sar_freq_tab[i].val == freq) {
213 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
214 *sar_freq = sar_freq_tab[i];
215 return;
216 #else
217 int k;
218 u8 ffc;
219
220 ffc = (val & SAR_FFC_FREQ_MASK) >>
221 SAR_FFC_FREQ_OFFS;
222 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
223 if (sar_freq_tab[k].ffc == ffc) {
224 *sar_freq = sar_freq_tab[k];
225 return;
226 }
227 }
228 i = k;
229 #endif
230 }
231 }
232
233 /* SAR value not found, return 0 for frequencies */
234 *sar_freq = sar_freq_tab[i - 1];
235 }
236
237 int print_cpuinfo(void)
238 {
239 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
240 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
241 struct sar_freq_modes sar_freq;
242
243 puts("SoC: ");
244
245 switch (devid) {
246 case SOC_MV78230_ID:
247 puts("MV78230-");
248 break;
249 case SOC_MV78260_ID:
250 puts("MV78260-");
251 break;
252 case SOC_MV78460_ID:
253 puts("MV78460-");
254 break;
255 case SOC_88F6720_ID:
256 puts("MV88F6720-");
257 break;
258 case SOC_88F6810_ID:
259 puts("MV88F6810-");
260 break;
261 case SOC_88F6820_ID:
262 puts("MV88F6820-");
263 break;
264 case SOC_88F6828_ID:
265 puts("MV88F6828-");
266 break;
267 case SOC_98DX3236_ID:
268 puts("98DX3236-");
269 break;
270 case SOC_98DX3336_ID:
271 puts("98DX3336-");
272 break;
273 case SOC_98DX4251_ID:
274 puts("98DX4251-");
275 break;
276 default:
277 puts("Unknown-");
278 break;
279 }
280
281 switch (devid) {
282 case SOC_MV78230_ID:
283 case SOC_MV78260_ID:
284 case SOC_MV78460_ID:
285 switch (revid) {
286 case 1:
287 puts("A0");
288 break;
289 case 2:
290 puts("B0");
291 break;
292 default:
293 printf("?? (%x)", revid);
294 break;
295 }
296 break;
297
298 case SOC_88F6720_ID:
299 switch (revid) {
300 case MV_88F67XX_A0_ID:
301 puts("A0");
302 break;
303 default:
304 printf("?? (%x)", revid);
305 break;
306 }
307 break;
308
309 case SOC_88F6810_ID:
310 case SOC_88F6820_ID:
311 case SOC_88F6828_ID:
312 switch (revid) {
313 case MV_88F68XX_Z1_ID:
314 puts("Z1");
315 break;
316 case MV_88F68XX_A0_ID:
317 puts("A0");
318 break;
319 case MV_88F68XX_B0_ID:
320 puts("B0");
321 break;
322 default:
323 printf("?? (%x)", revid);
324 break;
325 }
326 break;
327
328 case SOC_98DX3236_ID:
329 case SOC_98DX3336_ID:
330 case SOC_98DX4251_ID:
331 switch (revid) {
332 case 3:
333 puts("A0");
334 break;
335 case 4:
336 puts("A1");
337 break;
338 default:
339 printf("?? (%x)", revid);
340 break;
341 }
342 break;
343
344 default:
345 printf("?? (%x)", revid);
346 break;
347 }
348
349 get_sar_freq(&sar_freq);
350 printf(" at %d MHz\n", sar_freq.p_clk);
351
352 return 0;
353 }
354 #endif /* CONFIG_DISPLAY_CPUINFO */
355
356 /*
357 * This function initialize Controller DRAM Fastpath windows.
358 * It takes the CS size information from the 0x1500 scratch registers
359 * and sets the correct windows sizes and base addresses accordingly.
360 *
361 * These values are set in the scratch registers by the Marvell
362 * DDR3 training code, which is executed by the SPL before the
363 * main payload (U-Boot) is executed.
364 */
365 static void update_sdram_window_sizes(void)
366 {
367 u64 base = 0;
368 u32 size, temp;
369 int i;
370
371 for (i = 0; i < SDRAM_MAX_CS; i++) {
372 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
373 if (size != 0) {
374 size |= ~(SDRAM_ADDR_MASK);
375
376 /* Set Base Address */
377 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
378 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
379
380 /*
381 * Check if out of max window size and resize
382 * the window
383 */
384 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
385 ~(SDRAM_ADDR_MASK)) | 1;
386 temp |= (size & SDRAM_ADDR_MASK);
387 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
388
389 base += ((u64)size + 1);
390 } else {
391 /*
392 * Disable window if not used, otherwise this
393 * leads to overlapping enabled windows with
394 * pretty strange results
395 */
396 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
397 }
398 }
399 }
400
401 #ifdef CONFIG_ARCH_CPU_INIT
402 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
403 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
404 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
405 (((addr) & 0xF) << 6))
406 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
407 (((reg) & 0xF) << 2))
408
409 static void setup_usb_phys(void)
410 {
411 int dev;
412
413 /*
414 * USB PLL init
415 */
416
417 /* Setup PLL frequency */
418 /* USB REF frequency = 25 MHz */
419 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
420
421 /* Power up PLL and PHY channel */
422 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
423
424 /* Assert VCOCAL_START */
425 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
426
427 mdelay(1);
428
429 /*
430 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
431 */
432
433 for (dev = 0; dev < 3; dev++) {
434 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
435
436 /* Assert REG_RCAL_START in channel REG 1 */
437 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
438 udelay(40);
439 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
440 }
441 }
442
443 /*
444 * This function is not called from the SPL U-Boot version
445 */
446 int arch_cpu_init(void)
447 {
448 /*
449 * We need to call mvebu_mbus_probe() before calling
450 * update_sdram_window_sizes() as it disables all previously
451 * configured mbus windows and then configures them as
452 * required for U-Boot. Calling update_sdram_window_sizes()
453 * without this configuration will not work, as the internal
454 * registers can't be accessed reliably because of potenial
455 * double mapping.
456 * After updating the SDRAM access windows we need to call
457 * mvebu_mbus_probe() again, as this now correctly configures
458 * the SDRAM areas that are later used by the MVEBU drivers
459 * (e.g. USB, NETA).
460 */
461
462 /*
463 * First disable all windows
464 */
465 mvebu_mbus_probe(NULL, 0);
466
467 if (IS_ENABLED(CONFIG_ARMADA_XP)) {
468 /*
469 * Now the SDRAM access windows can be reconfigured using
470 * the information in the SDRAM scratch pad registers
471 */
472 update_sdram_window_sizes();
473 }
474
475 /*
476 * Finally the mbus windows can be configured with the
477 * updated SDRAM sizes
478 */
479 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
480
481 if (IS_ENABLED(CONFIG_ARMADA_XP)) {
482 /* Enable GBE0, GBE1, LCD and NFC PUP */
483 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
484 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
485 NAND_PUP_EN | SPI_PUP_EN);
486
487 /* Configure USB PLL and PHYs on AXP */
488 setup_usb_phys();
489 }
490
491 /* Enable NAND and NAND arbiter */
492 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
493
494 /* Disable MBUS error propagation */
495 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
496
497 return 0;
498 }
499 #endif /* CONFIG_ARCH_CPU_INIT */
500
501 u32 mvebu_get_nand_clock(void)
502 {
503 u32 reg;
504
505 if (IS_ENABLED(CONFIG_ARMADA_38X))
506 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
507 else if (IS_ENABLED(CONFIG_ARMADA_MSYS))
508 reg = MVEBU_DFX_DIV_CLK_CTRL(8);
509 else
510 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
511
512 return CONFIG_SYS_MVEBU_PLL_CLOCK /
513 ((readl(reg) &
514 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
515 }
516
517 /*
518 * SOC specific misc init
519 */
520 #if defined(CONFIG_ARCH_MISC_INIT)
521 int arch_misc_init(void)
522 {
523 /* Nothing yet, perhaps we need something here later */
524 return 0;
525 }
526 #endif /* CONFIG_ARCH_MISC_INIT */
527
528 #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
529 int board_mmc_init(struct bd_info *bis)
530 {
531 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
532 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
533
534 return 0;
535 }
536 #endif
537
538 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
539 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
540
541 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
542 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
543 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
544
545 static void ahci_mvebu_mbus_config(void __iomem *base)
546 {
547 const struct mbus_dram_target_info *dram;
548 int i;
549
550 /* mbus is not initialized in SPL; keep the ROM settings */
551 if (IS_ENABLED(CONFIG_SPL_BUILD))
552 return;
553
554 dram = mvebu_mbus_dram_info();
555
556 for (i = 0; i < 4; i++) {
557 writel(0, base + AHCI_WINDOW_CTRL(i));
558 writel(0, base + AHCI_WINDOW_BASE(i));
559 writel(0, base + AHCI_WINDOW_SIZE(i));
560 }
561
562 for (i = 0; i < dram->num_cs; i++) {
563 const struct mbus_dram_window *cs = dram->cs + i;
564
565 writel((cs->mbus_attr << 8) |
566 (dram->mbus_dram_target_id << 4) | 1,
567 base + AHCI_WINDOW_CTRL(i));
568 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
569 writel(((cs->size - 1) & 0xffff0000),
570 base + AHCI_WINDOW_SIZE(i));
571 }
572 }
573
574 static void ahci_mvebu_regret_option(void __iomem *base)
575 {
576 /*
577 * Enable the regret bit to allow the SATA unit to regret a
578 * request that didn't receive an acknowlegde and avoid a
579 * deadlock
580 */
581 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
582 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
583 }
584
585 int board_ahci_enable(void)
586 {
587 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
588 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
589
590 return 0;
591 }
592
593 #ifdef CONFIG_SCSI_AHCI_PLAT
594 void scsi_init(void)
595 {
596 printf("MVEBU SATA INIT\n");
597 board_ahci_enable();
598 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
599 }
600 #endif
601
602 #ifdef CONFIG_USB_XHCI_MVEBU
603 #define USB3_MAX_WINDOWS 4
604 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
605 #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
606
607 static void xhci_mvebu_mbus_config(void __iomem *base,
608 const struct mbus_dram_target_info *dram)
609 {
610 int i;
611
612 for (i = 0; i < USB3_MAX_WINDOWS; i++) {
613 writel(0, base + USB3_WIN_CTRL(i));
614 writel(0, base + USB3_WIN_BASE(i));
615 }
616
617 for (i = 0; i < dram->num_cs; i++) {
618 const struct mbus_dram_window *cs = dram->cs + i;
619
620 /* Write size, attributes and target id to control register */
621 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
622 (dram->mbus_dram_target_id << 4) | 1,
623 base + USB3_WIN_CTRL(i));
624
625 /* Write base address to base register */
626 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
627 }
628 }
629
630 int board_xhci_enable(fdt_addr_t base)
631 {
632 const struct mbus_dram_target_info *dram;
633
634 printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
635
636 dram = mvebu_mbus_dram_info();
637 xhci_mvebu_mbus_config((void __iomem *)base, dram);
638
639 return 0;
640 }
641 #endif
642
643 void enable_caches(void)
644 {
645 /* Avoid problem with e.g. neta ethernet driver */
646 invalidate_dcache_all();
647
648 /*
649 * Armada 375 still has some problems with d-cache enabled in the
650 * ethernet driver (mvpp2). So lets keep the d-cache disabled
651 * until this is solved.
652 */
653 if (!IS_ENABLED(CONFIG_ARMADA_375)) {
654 /* Enable D-cache. I-cache is already enabled in start.S */
655 dcache_enable();
656 }
657 }
658
659 void v7_outer_cache_enable(void)
660 {
661 struct pl310_regs *const pl310 =
662 (struct pl310_regs *)CFG_SYS_PL310_BASE;
663
664 /* The L2 cache is already disabled at this point */
665
666 /*
667 * For now L2 cache will be enabled only for Armada XP and Armada 38x.
668 * It can be enabled also for other SoCs after testing that it works fine.
669 */
670 if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X))
671 return;
672
673 if (IS_ENABLED(CONFIG_ARMADA_XP)) {
674 u32 u;
675
676 /*
677 * For Aurora cache in no outer mode, enable via the CP15
678 * coprocessor broadcasting of cache commands to L2.
679 */
680 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
681 u |= BIT(8); /* Set the FW bit */
682 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
683
684 isb();
685 }
686
687 /* Enable the L2 cache */
688 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
689 }
690
691 void v7_outer_cache_disable(void)
692 {
693 struct pl310_regs *const pl310 =
694 (struct pl310_regs *)CFG_SYS_PL310_BASE;
695
696 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
697 }
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