arch/arm/mach-mvebu/cpu.c

   1 /*
   2  * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <ahci.h>
   9 #include <linux/mbus.h>
  10 #include <asm/io.h>
  11 #include <asm/pl310.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14 #include <sdhci.h>
  15
  16 #define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  17 #define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  18
  19 static struct mbus_win windows[] = {
  20         /* SPI */
  21         { MBUS_SPI_BASE, MBUS_SPI_SIZE,
  22           CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
  23
  24         /* NOR */
  25         { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
  26           CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
  27 };
  28
  29 void lowlevel_init(void)
  30 {
  31         /*
  32          * Dummy implementation, we only need LOWLEVEL_INIT
  33          * on Armada to configure CP15 in start.S / cpu_init_cp15()
  34          */
  35 }
  36
  37 void reset_cpu(unsigned long ignored)
  38 {
  39         struct mvebu_system_registers *reg =
  40                 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  41
  42         writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  43         writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  44         while (1)
  45                 ;
  46 }
  47
  48 int mvebu_soc_family(void)
  49 {
  50         u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  51
  52         switch (devid) {
  53         case SOC_MV78230_ID:
  54         case SOC_MV78260_ID:
  55         case SOC_MV78460_ID:
  56                 return MVEBU_SOC_AXP;
  57
  58         case SOC_88F6720_ID:
  59                 return MVEBU_SOC_A375;
  60
  61         case SOC_88F6810_ID:
  62         case SOC_88F6820_ID:
  63         case SOC_88F6828_ID:
  64                 return MVEBU_SOC_A38X;
  65
  66         case SOC_98DX3236_ID:
  67         case SOC_98DX3336_ID:
  68         case SOC_98DX4251_ID:
  69                 return MVEBU_SOC_MSYS;
  70         }
  71
  72         return MVEBU_SOC_UNKNOWN;
  73 }
  74
  75 #if defined(CONFIG_DISPLAY_CPUINFO)
  76
  77 #if defined(CONFIG_ARMADA_375)
  78 /* SAR frequency values for Armada 375 */
  79 static const struct sar_freq_modes sar_freq_tab[] = {
  80         {  0,  0x0,  266,  133,  266 },
  81         {  1,  0x0,  333,  167,  167 },
  82         {  2,  0x0,  333,  167,  222 },
  83         {  3,  0x0,  333,  167,  333 },
  84         {  4,  0x0,  400,  200,  200 },
  85         {  5,  0x0,  400,  200,  267 },
  86         {  6,  0x0,  400,  200,  400 },
  87         {  7,  0x0,  500,  250,  250 },
  88         {  8,  0x0,  500,  250,  334 },
  89         {  9,  0x0,  500,  250,  500 },
  90         { 10,  0x0,  533,  267,  267 },
  91         { 11,  0x0,  533,  267,  356 },
  92         { 12,  0x0,  533,  267,  533 },
  93         { 13,  0x0,  600,  300,  300 },
  94         { 14,  0x0,  600,  300,  400 },
  95         { 15,  0x0,  600,  300,  600 },
  96         { 16,  0x0,  666,  333,  333 },
  97         { 17,  0x0,  666,  333,  444 },
  98         { 18,  0x0,  666,  333,  666 },
  99         { 19,  0x0,  800,  400,  267 },
 100         { 20,  0x0,  800,  400,  400 },
 101         { 21,  0x0,  800,  400,  534 },
 102         { 22,  0x0,  900,  450,  300 },
 103         { 23,  0x0,  900,  450,  450 },
 104         { 24,  0x0,  900,  450,  600 },
 105         { 25,  0x0, 1000,  500,  500 },
 106         { 26,  0x0, 1000,  500,  667 },
 107         { 27,  0x0, 1000,  333,  500 },
 108         { 28,  0x0,  400,  400,  400 },
 109         { 29,  0x0, 1100,  550,  550 },
 110         { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
 111 };
 112 #elif defined(CONFIG_ARMADA_38X)
 113 /* SAR frequency values for Armada 38x */
 114 static const struct sar_freq_modes sar_freq_tab[] = {
 115         {  0x0,  0x0,  666, 333, 333 },
 116         {  0x2,  0x0,  800, 400, 400 },
 117         {  0x4,  0x0, 1066, 533, 533 },
 118         {  0x6,  0x0, 1200, 600, 600 },
 119         {  0x8,  0x0, 1332, 666, 666 },
 120         {  0xc,  0x0, 1600, 800, 800 },
 121         { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
 122 };
 123 #else
 124 /* SAR frequency values for Armada XP */
 125 static const struct sar_freq_modes sar_freq_tab[] = {
 126         {  0xa,  0x5,  800, 400, 400 },
 127         {  0x1,  0x5, 1066, 533, 533 },
 128         {  0x2,  0x5, 1200, 600, 600 },
 129         {  0x2,  0x9, 1200, 600, 400 },
 130         {  0x3,  0x5, 1333, 667, 667 },
 131         {  0x4,  0x5, 1500, 750, 750 },
 132         {  0x4,  0x9, 1500, 750, 500 },
 133         {  0xb,  0x9, 1600, 800, 533 },
 134         {  0xb,  0xa, 1600, 800, 640 },
 135         {  0xb,  0x5, 1600, 800, 800 },
 136         { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
 137 };
 138 #endif
 139
 140 void get_sar_freq(struct sar_freq_modes *sar_freq)
 141 {
 142         u32 val;
 143         u32 freq;
 144         int i;
 145
 146 #if defined(CONFIG_ARMADA_375)
 147         val = readl(CONFIG_SAR2_REG);   /* SAR - Sample At Reset */
 148 #else
 149         val = readl(CONFIG_SAR_REG);    /* SAR - Sample At Reset */
 150 #endif
 151         freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
 152 #if defined(SAR2_CPU_FREQ_MASK)
 153         /*
 154          * Shift CPU0 clock frequency select bit from SAR2 register
 155          * into correct position
 156          */
 157         freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
 158                  >> SAR2_CPU_FREQ_OFFS) << 3;
 159 #endif
 160         for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
 161                 if (sar_freq_tab[i].val == freq) {
 162 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
 163                         *sar_freq = sar_freq_tab[i];
 164                         return;
 165 #else
 166                         int k;
 167                         u8 ffc;
 168
 169                         ffc = (val & SAR_FFC_FREQ_MASK) >>
 170                                 SAR_FFC_FREQ_OFFS;
 171                         for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
 172                                 if (sar_freq_tab[k].ffc == ffc) {
 173                                         *sar_freq = sar_freq_tab[k];
 174                                         return;
 175                                 }
 176                         }
 177                         i = k;
 178 #endif
 179                 }
 180         }
 181
 182         /* SAR value not found, return 0 for frequencies */
 183         *sar_freq = sar_freq_tab[i - 1];
 184 }
 185
 186 int print_cpuinfo(void)
 187 {
 188         u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
 189         u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
 190         struct sar_freq_modes sar_freq;
 191
 192         puts("SoC:   ");
 193
 194         switch (devid) {
 195         case SOC_MV78230_ID:
 196                 puts("MV78230-");
 197                 break;
 198         case SOC_MV78260_ID:
 199                 puts("MV78260-");
 200                 break;
 201         case SOC_MV78460_ID:
 202                 puts("MV78460-");
 203                 break;
 204         case SOC_88F6720_ID:
 205                 puts("MV88F6720-");
 206                 break;
 207         case SOC_88F6810_ID:
 208                 puts("MV88F6810-");
 209                 break;
 210         case SOC_88F6820_ID:
 211                 puts("MV88F6820-");
 212                 break;
 213         case SOC_88F6828_ID:
 214                 puts("MV88F6828-");
 215                 break;
 216         case SOC_98DX3236_ID:
 217                 puts("98DX3236-");
 218                 break;
 219         case SOC_98DX3336_ID:
 220                 puts("98DX3336-");
 221                 break;
 222         case SOC_98DX4251_ID:
 223                 puts("98DX4251-");
 224                 break;
 225         default:
 226                 puts("Unknown-");
 227                 break;
 228         }
 229
 230         if (mvebu_soc_family() == MVEBU_SOC_AXP) {
 231                 switch (revid) {
 232                 case 1:
 233                         puts("A0");
 234                         break;
 235                 case 2:
 236                         puts("B0");
 237                         break;
 238                 default:
 239                         printf("?? (%x)", revid);
 240                         break;
 241                 }
 242         }
 243
 244         if (mvebu_soc_family() == MVEBU_SOC_A375) {
 245                 switch (revid) {
 246                 case MV_88F67XX_A0_ID:
 247                         puts("A0");
 248                         break;
 249                 default:
 250                         printf("?? (%x)", revid);
 251                         break;
 252                 }
 253         }
 254
 255         if (mvebu_soc_family() == MVEBU_SOC_A38X) {
 256                 switch (revid) {
 257                 case MV_88F68XX_Z1_ID:
 258                         puts("Z1");
 259                         break;
 260                 case MV_88F68XX_A0_ID:
 261                         puts("A0");
 262                         break;
 263                 default:
 264                         printf("?? (%x)", revid);
 265                         break;
 266                 }
 267         }
 268
 269         get_sar_freq(&sar_freq);
 270         printf(" at %d MHz\n", sar_freq.p_clk);
 271
 272         return 0;
 273 }
 274 #endif /* CONFIG_DISPLAY_CPUINFO */
 275
 276 /*
 277  * This function initialize Controller DRAM Fastpath windows.
 278  * It takes the CS size information from the 0x1500 scratch registers
 279  * and sets the correct windows sizes and base addresses accordingly.
 280  *
 281  * These values are set in the scratch registers by the Marvell
 282  * DDR3 training code, which is executed by the BootROM before the
 283  * main payload (U-Boot) is executed. This training code is currently
 284  * only available in the Marvell U-Boot version. It needs to be
 285  * ported to mainline U-Boot SPL at some point.
 286  */
 287 static void update_sdram_window_sizes(void)
 288 {
 289         u64 base = 0;
 290         u32 size, temp;
 291         int i;
 292
 293         for (i = 0; i < SDRAM_MAX_CS; i++) {
 294                 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
 295                 if (size != 0) {
 296                         size |= ~(SDRAM_ADDR_MASK);
 297
 298                         /* Set Base Address */
 299                         temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
 300                         writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
 301
 302                         /*
 303                          * Check if out of max window size and resize
 304                          * the window
 305                          */
 306                         temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
 307                                 ~(SDRAM_ADDR_MASK)) | 1;
 308                         temp |= (size & SDRAM_ADDR_MASK);
 309                         writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
 310
 311                         base += ((u64)size + 1);
 312                 } else {
 313                         /*
 314                          * Disable window if not used, otherwise this
 315                          * leads to overlapping enabled windows with
 316                          * pretty strange results
 317                          */
 318                         clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
 319                 }
 320         }
 321 }
 322
 323 void mmu_disable(void)
 324 {
 325         asm volatile(
 326                 "mrc p15, 0, r0, c1, c0, 0\n"
 327                 "bic r0, #1\n"
 328                 "mcr p15, 0, r0, c1, c0, 0\n");
 329 }
 330
 331 #ifdef CONFIG_ARCH_CPU_INIT
 332 static void set_cbar(u32 addr)
 333 {
 334         asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
 335 }
 336
 337 #define MV_USB_PHY_BASE                 (MVEBU_AXP_USB_BASE + 0x800)
 338 #define MV_USB_PHY_PLL_REG(reg)         (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
 339 #define MV_USB_X3_BASE(addr)            (MVEBU_AXP_USB_BASE | BIT(11) | \
 340                                          (((addr) & 0xF) << 6))
 341 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) |    \
 342                                          (((reg) & 0xF) << 2))
 343
 344 static void setup_usb_phys(void)
 345 {
 346         int dev;
 347
 348         /*
 349          * USB PLL init
 350          */
 351
 352         /* Setup PLL frequency */
 353         /* USB REF frequency = 25 MHz */
 354         clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
 355
 356         /* Power up PLL and PHY channel */
 357         setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
 358
 359         /* Assert VCOCAL_START */
 360         setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
 361
 362         mdelay(1);
 363
 364         /*
 365          * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
 366          */
 367
 368         for (dev = 0; dev < 3; dev++) {
 369                 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
 370
 371                 /* Assert REG_RCAL_START in channel REG 1 */
 372                 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
 373                 udelay(40);
 374                 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
 375         }
 376 }
 377
 378 /*
 379  * This function is not called from the SPL U-Boot version
 380  */
 381 int arch_cpu_init(void)
 382 {
 383         struct pl310_regs *const pl310 =
 384                 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 385
 386         /*
 387          * Only with disabled MMU its possible to switch the base
 388          * register address on Armada 38x. Without this the SDRAM
 389          * located at >= 0x4000.0000 is also not accessible, as its
 390          * still locked to cache.
 391          */
 392         mmu_disable();
 393
 394         /* Linux expects the internal registers to be at 0xf1000000 */
 395         writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
 396         set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 397
 398         /*
 399          * From this stage on, the SoC detection is working. As we have
 400          * configured the internal register base to the value used
 401          * in the macros / defines in the U-Boot header (soc.h).
 402          */
 403
 404         if (mvebu_soc_family() == MVEBU_SOC_A38X) {
 405                 /*
 406                  * To fully release / unlock this area from cache, we need
 407                  * to flush all caches and disable the L2 cache.
 408                  */
 409                 icache_disable();
 410                 dcache_disable();
 411                 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 412         }
 413
 414         /*
 415          * We need to call mvebu_mbus_probe() before calling
 416          * update_sdram_window_sizes() as it disables all previously
 417          * configured mbus windows and then configures them as
 418          * required for U-Boot. Calling update_sdram_window_sizes()
 419          * without this configuration will not work, as the internal
 420          * registers can't be accessed reliably because of potenial
 421          * double mapping.
 422          * After updating the SDRAM access windows we need to call
 423          * mvebu_mbus_probe() again, as this now correctly configures
 424          * the SDRAM areas that are later used by the MVEBU drivers
 425          * (e.g. USB, NETA).
 426          */
 427
 428         /*
 429          * First disable all windows
 430          */
 431         mvebu_mbus_probe(NULL, 0);
 432
 433         if (mvebu_soc_family() == MVEBU_SOC_AXP) {
 434                 /*
 435                  * Now the SDRAM access windows can be reconfigured using
 436                  * the information in the SDRAM scratch pad registers
 437                  */
 438                 update_sdram_window_sizes();
 439         }
 440
 441         /*
 442          * Finally the mbus windows can be configured with the
 443          * updated SDRAM sizes
 444          */
 445         mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
 446
 447         if (mvebu_soc_family() == MVEBU_SOC_AXP) {
 448                 /* Enable GBE0, GBE1, LCD and NFC PUP */
 449                 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
 450                                 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
 451                                 NAND_PUP_EN | SPI_PUP_EN);
 452
 453                 /* Configure USB PLL and PHYs on AXP */
 454                 setup_usb_phys();
 455         }
 456
 457         /* Enable NAND and NAND arbiter */
 458         clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
 459
 460         /* Disable MBUS error propagation */
 461         clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
 462
 463         return 0;
 464 }
 465 #endif /* CONFIG_ARCH_CPU_INIT */
 466
 467 u32 mvebu_get_nand_clock(void)
 468 {
 469         u32 reg;
 470
 471         if (mvebu_soc_family() == MVEBU_SOC_A38X)
 472                 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
 473         else
 474                 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
 475
 476         return CONFIG_SYS_MVEBU_PLL_CLOCK /
 477                 ((readl(reg) &
 478                   NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
 479 }
 480
 481 /*
 482  * SOC specific misc init
 483  */
 484 #if defined(CONFIG_ARCH_MISC_INIT)
 485 int arch_misc_init(void)
 486 {
 487         /* Nothing yet, perhaps we need something here later */
 488         return 0;
 489 }
 490 #endif /* CONFIG_ARCH_MISC_INIT */
 491
 492 #ifdef CONFIG_MMC_SDHCI_MV
 493 int board_mmc_init(bd_t *bis)
 494 {
 495         mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
 496                     SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
 497
 498         return 0;
 499 }
 500 #endif
 501
 502 #ifdef CONFIG_SCSI_AHCI_PLAT
 503 #define AHCI_VENDOR_SPECIFIC_0_ADDR     0xa0
 504 #define AHCI_VENDOR_SPECIFIC_0_DATA     0xa4
 505
 506 #define AHCI_WINDOW_CTRL(win)           (0x60 + ((win) << 4))
 507 #define AHCI_WINDOW_BASE(win)           (0x64 + ((win) << 4))
 508 #define AHCI_WINDOW_SIZE(win)           (0x68 + ((win) << 4))
 509
 510 static void ahci_mvebu_mbus_config(void __iomem *base)
 511 {
 512         const struct mbus_dram_target_info *dram;
 513         int i;
 514
 515         dram = mvebu_mbus_dram_info();
 516
 517         for (i = 0; i < 4; i++) {
 518                 writel(0, base + AHCI_WINDOW_CTRL(i));
 519                 writel(0, base + AHCI_WINDOW_BASE(i));
 520                 writel(0, base + AHCI_WINDOW_SIZE(i));
 521         }
 522
 523         for (i = 0; i < dram->num_cs; i++) {
 524                 const struct mbus_dram_window *cs = dram->cs + i;
 525
 526                 writel((cs->mbus_attr << 8) |
 527                        (dram->mbus_dram_target_id << 4) | 1,
 528                        base + AHCI_WINDOW_CTRL(i));
 529                 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
 530                 writel(((cs->size - 1) & 0xffff0000),
 531                        base + AHCI_WINDOW_SIZE(i));
 532         }
 533 }
 534
 535 static void ahci_mvebu_regret_option(void __iomem *base)
 536 {
 537         /*
 538          * Enable the regret bit to allow the SATA unit to regret a
 539          * request that didn't receive an acknowlegde and avoid a
 540          * deadlock
 541          */
 542         writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
 543         writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
 544 }
 545
 546 void scsi_init(void)
 547 {
 548         printf("MVEBU SATA INIT\n");
 549         ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
 550         ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
 551         ahci_init((void __iomem *)MVEBU_SATA0_BASE);
 552 }
 553 #endif
 554
 555 void enable_caches(void)
 556 {
 557         /* Avoid problem with e.g. neta ethernet driver */
 558         invalidate_dcache_all();
 559
 560         /*
 561          * Armada 375 still has some problems with d-cache enabled in the
 562          * ethernet driver (mvpp2). So lets keep the d-cache disabled
 563          * until this is solved.
 564          */
 565         if (mvebu_soc_family() != MVEBU_SOC_A375) {
 566                 /* Enable D-cache. I-cache is already enabled in start.S */
 567                 dcache_enable();
 568         }
 569 }
 570
 571 void v7_outer_cache_enable(void)
 572 {
 573         if (mvebu_soc_family() == MVEBU_SOC_AXP) {
 574                 struct pl310_regs *const pl310 =
 575                         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 576                 u32 u;
 577
 578                 /* The L2 cache is already disabled at this point */
 579
 580                 /*
 581                  * For Aurora cache in no outer mode, enable via the CP15
 582                  * coprocessor broadcasting of cache commands to L2.
 583                  */
 584                 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
 585                 u |= BIT(8);            /* Set the FW bit */
 586                 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
 587
 588                 isb();
 589
 590                 /* Enable the L2 cache */
 591                 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 592         }
 593 }
 594
 595 void v7_outer_cache_disable(void)
 596 {
 597         struct pl310_regs *const pl310 =
 598                 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 599
 600         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 601 }