2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/mbus.h>
12 #include <asm/pl310.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
20 static struct mbus_win windows
[] = {
21 /* PCIE MEM address space */
22 { MBUS_PCI_MEM_BASE
, MBUS_PCI_MEM_SIZE
,
23 CPU_TARGET_PCIE13
, CPU_ATTR_PCIE_MEM
},
25 /* PCIE IO address space */
26 { MBUS_PCI_IO_BASE
, MBUS_PCI_IO_SIZE
,
27 CPU_TARGET_PCIE13
, CPU_ATTR_PCIE_IO
},
30 { MBUS_SPI_BASE
, MBUS_SPI_SIZE
,
31 CPU_TARGET_DEVICEBUS_BOOTROM_SPI
, CPU_ATTR_SPIFLASH
},
34 { MBUS_BOOTROM_BASE
, MBUS_BOOTROM_SIZE
,
35 CPU_TARGET_DEVICEBUS_BOOTROM_SPI
, CPU_ATTR_BOOTROM
},
38 void reset_cpu(unsigned long ignored
)
40 struct mvebu_system_registers
*reg
=
41 (struct mvebu_system_registers
*)MVEBU_SYSTEM_REG_BASE
;
43 writel(readl(®
->rstoutn_mask
) | 1, ®
->rstoutn_mask
);
44 writel(readl(®
->sys_soft_rst
) | 1, ®
->sys_soft_rst
);
49 int mvebu_soc_family(void)
51 u16 devid
= (readl(MVEBU_REG_PCIE_DEVID
) >> 16) & 0xffff;
53 if (devid
== SOC_MV78460_ID
)
56 if (devid
== SOC_88F6810_ID
|| devid
== SOC_88F6820_ID
||
57 devid
== SOC_88F6828_ID
)
58 return MVEBU_SOC_A38X
;
60 return MVEBU_SOC_UNKNOWN
;
63 #if defined(CONFIG_DISPLAY_CPUINFO)
64 int print_cpuinfo(void)
66 u16 devid
= (readl(MVEBU_REG_PCIE_DEVID
) >> 16) & 0xffff;
67 u8 revid
= readl(MVEBU_REG_PCIE_REVID
) & 0xff;
89 if (mvebu_soc_family() == MVEBU_SOC_AXP
) {
98 printf("?? (%x)\n", revid
);
103 if (mvebu_soc_family() == MVEBU_SOC_A38X
) {
105 case MV_88F68XX_Z1_ID
:
108 case MV_88F68XX_A0_ID
:
112 printf("?? (%x)\n", revid
);
119 #endif /* CONFIG_DISPLAY_CPUINFO */
122 * This function initialize Controller DRAM Fastpath windows.
123 * It takes the CS size information from the 0x1500 scratch registers
124 * and sets the correct windows sizes and base addresses accordingly.
126 * These values are set in the scratch registers by the Marvell
127 * DDR3 training code, which is executed by the BootROM before the
128 * main payload (U-Boot) is executed. This training code is currently
129 * only available in the Marvell U-Boot version. It needs to be
130 * ported to mainline U-Boot SPL at some point.
132 static void update_sdram_window_sizes(void)
138 for (i
= 0; i
< SDRAM_MAX_CS
; i
++) {
139 size
= readl((MVEBU_SDRAM_SCRATCH
+ (i
* 8))) & SDRAM_ADDR_MASK
;
141 size
|= ~(SDRAM_ADDR_MASK
);
143 /* Set Base Address */
144 temp
= (base
& 0xFF000000ll
) | ((base
>> 32) & 0xF);
145 writel(temp
, MVEBU_SDRAM_BASE
+ DDR_BASE_CS_OFF(i
));
148 * Check if out of max window size and resize
151 temp
= (readl(MVEBU_SDRAM_BASE
+ DDR_SIZE_CS_OFF(i
)) &
152 ~(SDRAM_ADDR_MASK
)) | 1;
153 temp
|= (size
& SDRAM_ADDR_MASK
);
154 writel(temp
, MVEBU_SDRAM_BASE
+ DDR_SIZE_CS_OFF(i
));
156 base
+= ((u64
)size
+ 1);
159 * Disable window if not used, otherwise this
160 * leads to overlapping enabled windows with
161 * pretty strange results
163 clrbits_le32(MVEBU_SDRAM_BASE
+ DDR_SIZE_CS_OFF(i
), 1);
168 void mmu_disable(void)
171 "mrc p15, 0, r0, c1, c0, 0\n"
173 "mcr p15, 0, r0, c1, c0, 0\n");
176 #ifdef CONFIG_ARCH_CPU_INIT
177 static void set_cbar(u32 addr
)
179 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr
));
183 int arch_cpu_init(void)
185 #ifndef CONFIG_SPL_BUILD
186 if (mvebu_soc_family() == MVEBU_SOC_A38X
) {
187 struct pl310_regs
*const pl310
=
188 (struct pl310_regs
*)CONFIG_SYS_PL310_BASE
;
191 * Only with disabled MMU its possible to switch the base
192 * register address on Armada 38x. Without this the SDRAM
193 * located at >= 0x4000.0000 is also not accessible, as its
194 * still locked to cache.
196 * So to fully release / unlock this area from cache, we need
197 * to first flush all caches, then disable the MMU and
198 * disable the L2 cache.
203 clrbits_le32(&pl310
->pl310_ctrl
, L2X0_CTRL_EN
);
207 /* Linux expects the internal registers to be at 0xf1000000 */
208 writel(SOC_REGS_PHY_BASE
, INTREG_BASE_ADDR_REG
);
209 set_cbar(SOC_REGS_PHY_BASE
+ 0xC000);
212 * We need to call mvebu_mbus_probe() before calling
213 * update_sdram_window_sizes() as it disables all previously
214 * configured mbus windows and then configures them as
215 * required for U-Boot. Calling update_sdram_window_sizes()
216 * without this configuration will not work, as the internal
217 * registers can't be accessed reliably because of potenial
219 * After updating the SDRAM access windows we need to call
220 * mvebu_mbus_probe() again, as this now correctly configures
221 * the SDRAM areas that are later used by the MVEBU drivers
226 * First disable all windows
228 mvebu_mbus_probe(NULL
, 0);
230 if (mvebu_soc_family() == MVEBU_SOC_AXP
) {
232 * Now the SDRAM access windows can be reconfigured using
233 * the information in the SDRAM scratch pad registers
235 update_sdram_window_sizes();
239 * Finally the mbus windows can be configured with the
240 * updated SDRAM sizes
242 mvebu_mbus_probe(windows
, ARRAY_SIZE(windows
));
244 if (mvebu_soc_family() == MVEBU_SOC_AXP
) {
245 /* Enable GBE0, GBE1, LCD and NFC PUP */
246 clrsetbits_le32(ARMADA_XP_PUP_ENABLE
, 0,
247 GE0_PUP_EN
| GE1_PUP_EN
| LCD_PUP_EN
|
248 NAND_PUP_EN
| SPI_PUP_EN
);
251 /* Enable NAND and NAND arbiter */
252 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG
, 0, NAND_EN
| NAND_ARBITER_EN
);
254 /* Disable MBUS error propagation */
255 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG
, MBUS_ERR_PROP_EN
, 0);
259 #endif /* CONFIG_ARCH_CPU_INIT */
261 u32
mvebu_get_nand_clock(void)
263 return CONFIG_SYS_MVEBU_PLL_CLOCK
/
264 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
265 NAND_ECC_DIVCKL_RATIO_MASK
) >> NAND_ECC_DIVCKL_RATIO_OFFS
);
269 * SOC specific misc init
271 #if defined(CONFIG_ARCH_MISC_INIT)
272 int arch_misc_init(void)
274 /* Nothing yet, perhaps we need something here later */
277 #endif /* CONFIG_ARCH_MISC_INIT */
280 int cpu_eth_init(bd_t
*bis
)
282 u32 enet_base
[] = { MVEBU_EGIGA0_BASE
, MVEBU_EGIGA1_BASE
,
283 MVEBU_EGIGA2_BASE
, MVEBU_EGIGA3_BASE
};
284 u8 phy_addr
[] = CONFIG_PHY_ADDR
;
288 * Only Armada XP supports all 4 ethernet interfaces. A38x has
289 * slightly different base addresses for its 2-3 interfaces.
291 if (mvebu_soc_family() != MVEBU_SOC_AXP
) {
292 enet_base
[1] = MVEBU_EGIGA2_BASE
;
293 enet_base
[2] = MVEBU_EGIGA3_BASE
;
296 for (i
= 0; i
< ARRAY_SIZE(phy_addr
); i
++)
297 mvneta_initialize(bis
, enet_base
[i
], i
, phy_addr
[i
]);
303 #ifdef CONFIG_MV_SDHCI
304 int board_mmc_init(bd_t
*bis
)
306 mv_sdh_init(MVEBU_SDIO_BASE
, 0, 0,
307 SDHCI_QUIRK_32BIT_DMA_ADDR
| SDHCI_QUIRK_WAIT_SEND_CMD
);
313 #ifdef CONFIG_SCSI_AHCI_PLAT
314 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
315 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
317 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
318 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
319 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
321 static void ahci_mvebu_mbus_config(void __iomem
*base
)
323 const struct mbus_dram_target_info
*dram
;
326 dram
= mvebu_mbus_dram_info();
328 for (i
= 0; i
< 4; i
++) {
329 writel(0, base
+ AHCI_WINDOW_CTRL(i
));
330 writel(0, base
+ AHCI_WINDOW_BASE(i
));
331 writel(0, base
+ AHCI_WINDOW_SIZE(i
));
334 for (i
= 0; i
< dram
->num_cs
; i
++) {
335 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
337 writel((cs
->mbus_attr
<< 8) |
338 (dram
->mbus_dram_target_id
<< 4) | 1,
339 base
+ AHCI_WINDOW_CTRL(i
));
340 writel(cs
->base
>> 16, base
+ AHCI_WINDOW_BASE(i
));
341 writel(((cs
->size
- 1) & 0xffff0000),
342 base
+ AHCI_WINDOW_SIZE(i
));
346 static void ahci_mvebu_regret_option(void __iomem
*base
)
349 * Enable the regret bit to allow the SATA unit to regret a
350 * request that didn't receive an acknowlegde and avoid a
353 writel(0x4, base
+ AHCI_VENDOR_SPECIFIC_0_ADDR
);
354 writel(0x80, base
+ AHCI_VENDOR_SPECIFIC_0_DATA
);
359 printf("MVEBU SATA INIT\n");
360 ahci_mvebu_mbus_config((void __iomem
*)MVEBU_SATA0_BASE
);
361 ahci_mvebu_regret_option((void __iomem
*)MVEBU_SATA0_BASE
);
362 ahci_init((void __iomem
*)MVEBU_SATA0_BASE
);
366 #ifndef CONFIG_SYS_DCACHE_OFF
367 void enable_caches(void)
369 struct pl310_regs
*const pl310
=
370 (struct pl310_regs
*)CONFIG_SYS_PL310_BASE
;
372 /* First disable L2 cache - may still be enable from BootROM */
373 if (mvebu_soc_family() == MVEBU_SOC_A38X
)
374 clrbits_le32(&pl310
->pl310_ctrl
, L2X0_CTRL_EN
);
376 /* Avoid problem with e.g. neta ethernet driver */
377 invalidate_dcache_all();
379 /* Enable D-cache. I-cache is already enabled in start.S */