arch/arm/mach-mvebu/cpu.c

   1 /*
   2  * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <netdev.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/soc.h>
  12
  13 #define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  14 #define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  15
  16 static struct mbus_win windows[] = {
  17         /* PCIE MEM address space */
  18         { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
  19
  20         /* PCIE IO address space */
  21         { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
  22
  23         /* SPI */
  24         { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
  25           CPU_ATTR_SPIFLASH },
  26
  27         /* NOR */
  28         { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
  29           CPU_ATTR_BOOTROM },
  30 };
  31
  32 void reset_cpu(unsigned long ignored)
  33 {
  34         struct mvebu_system_registers *reg =
  35                 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  36
  37         writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  38         writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  39         while (1)
  40                 ;
  41 }
  42
  43 int mvebu_soc_family(void)
  44 {
  45         u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  46
  47         if (devid == SOC_MV78460_ID)
  48                 return MVEBU_SOC_AXP;
  49
  50         if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
  51             devid == SOC_88F6828_ID)
  52                 return MVEBU_SOC_A38X;
  53
  54         return MVEBU_SOC_UNKNOWN;
  55 }
  56
  57 #if defined(CONFIG_DISPLAY_CPUINFO)
  58 int print_cpuinfo(void)
  59 {
  60         u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  61         u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
  62
  63         puts("SoC:   ");
  64
  65         switch (devid) {
  66         case SOC_MV78460_ID:
  67                 puts("MV78460-");
  68                 break;
  69         case SOC_88F6810_ID:
  70                 puts("MV88F6810-");
  71                 break;
  72         case SOC_88F6820_ID:
  73                 puts("MV88F6820-");
  74                 break;
  75         case SOC_88F6828_ID:
  76                 puts("MV88F6828-");
  77                 break;
  78         default:
  79                 puts("Unknown-");
  80                 break;
  81         }
  82
  83         if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  84                 switch (revid) {
  85                 case 1:
  86                         puts("A0\n");
  87                         break;
  88                 case 2:
  89                         puts("B0\n");
  90                         break;
  91                 default:
  92                         printf("?? (%x)\n", revid);
  93                         break;
  94                 }
  95         }
  96
  97         if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  98                 switch (revid) {
  99                 case MV_88F68XX_Z1_ID:
 100                         puts("Z1\n");
 101                         break;
 102                 case MV_88F68XX_A0_ID:
 103                         puts("A0\n");
 104                         break;
 105                 default:
 106                         printf("?? (%x)\n", revid);
 107                         break;
 108                 }
 109         }
 110
 111         return 0;
 112 }
 113 #endif /* CONFIG_DISPLAY_CPUINFO */
 114
 115 /*
 116  * This function initialize Controller DRAM Fastpath windows.
 117  * It takes the CS size information from the 0x1500 scratch registers
 118  * and sets the correct windows sizes and base addresses accordingly.
 119  *
 120  * These values are set in the scratch registers by the Marvell
 121  * DDR3 training code, which is executed by the BootROM before the
 122  * main payload (U-Boot) is executed. This training code is currently
 123  * only available in the Marvell U-Boot version. It needs to be
 124  * ported to mainline U-Boot SPL at some point.
 125  */
 126 static void update_sdram_window_sizes(void)
 127 {
 128         u64 base = 0;
 129         u32 size, temp;
 130         int i;
 131
 132         for (i = 0; i < SDRAM_MAX_CS; i++) {
 133                 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
 134                 if (size != 0) {
 135                         size |= ~(SDRAM_ADDR_MASK);
 136
 137                         /* Set Base Address */
 138                         temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
 139                         writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
 140
 141                         /*
 142                          * Check if out of max window size and resize
 143                          * the window
 144                          */
 145                         temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
 146                                 ~(SDRAM_ADDR_MASK)) | 1;
 147                         temp |= (size & SDRAM_ADDR_MASK);
 148                         writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
 149
 150                         base += ((u64)size + 1);
 151                 } else {
 152                         /*
 153                          * Disable window if not used, otherwise this
 154                          * leads to overlapping enabled windows with
 155                          * pretty strange results
 156                          */
 157                         clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
 158                 }
 159         }
 160 }
 161
 162 #ifdef CONFIG_ARCH_CPU_INIT
 163 int arch_cpu_init(void)
 164 {
 165         /* Linux expects the internal registers to be at 0xf1000000 */
 166         writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
 167
 168         /*
 169          * We need to call mvebu_mbus_probe() before calling
 170          * update_sdram_window_sizes() as it disables all previously
 171          * configured mbus windows and then configures them as
 172          * required for U-Boot. Calling update_sdram_window_sizes()
 173          * without this configuration will not work, as the internal
 174          * registers can't be accessed reliably because of potenial
 175          * double mapping.
 176          * After updating the SDRAM access windows we need to call
 177          * mvebu_mbus_probe() again, as this now correctly configures
 178          * the SDRAM areas that are later used by the MVEBU drivers
 179          * (e.g. USB, NETA).
 180          */
 181
 182         /*
 183          * First disable all windows
 184          */
 185         mvebu_mbus_probe(NULL, 0);
 186
 187         if (mvebu_soc_family() == MVEBU_SOC_AXP) {
 188                 /*
 189                  * Now the SDRAM access windows can be reconfigured using
 190                  * the information in the SDRAM scratch pad registers
 191                  */
 192                 update_sdram_window_sizes();
 193         }
 194
 195         /*
 196          * Finally the mbus windows can be configured with the
 197          * updated SDRAM sizes
 198          */
 199         mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
 200
 201         return 0;
 202 }
 203 #endif /* CONFIG_ARCH_CPU_INIT */
 204
 205 /*
 206  * SOC specific misc init
 207  */
 208 #if defined(CONFIG_ARCH_MISC_INIT)
 209 int arch_misc_init(void)
 210 {
 211         /* Nothing yet, perhaps we need something here later */
 212         return 0;
 213 }
 214 #endif /* CONFIG_ARCH_MISC_INIT */
 215
 216 #ifdef CONFIG_MVNETA
 217 int cpu_eth_init(bd_t *bis)
 218 {
 219         u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
 220                             MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
 221         u8 phy_addr[] = CONFIG_PHY_ADDR;
 222         int i;
 223
 224         /*
 225          * Only Armada XP supports all 4 ethernet interfaces. A38x has
 226          * slightly different base addresses for its 2-3 interfaces.
 227          */
 228         if (mvebu_soc_family() != MVEBU_SOC_AXP) {
 229                 enet_base[1] = MVEBU_EGIGA2_BASE;
 230                 enet_base[2] = MVEBU_EGIGA3_BASE;
 231         }
 232
 233         for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
 234                 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
 235
 236         return 0;
 237 }
 238 #endif
 239
 240 #ifndef CONFIG_SYS_DCACHE_OFF
 241 void enable_caches(void)
 242 {
 243         /* Avoid problem with e.g. neta ethernet driver */
 244         invalidate_dcache_all();
 245
 246         /* Enable D-cache. I-cache is already enabled in start.S */
 247         dcache_enable();
 248 }
 249 #endif