3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 #if defined(CONFIG_ARCH_MVEBU)
16 /* Use common XOR definitions for A3x and AXP */
17 #include "../../../drivers/ddr/marvell/axp/xor.h"
18 #include "../../../drivers/ddr/marvell/axp/xor_regs.h"
21 DECLARE_GLOBAL_DATA_PTR
;
28 struct sdram_addr_dec
{
29 struct sdram_bank sdram_bank
[4];
32 #define REG_CPUCS_WIN_ENABLE (1 << 0)
33 #define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
34 #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
35 #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
37 #define SDRAM_SIZE_MAX 0xc0000000
39 #define SCRUB_MAGIC 0xbeefdead
41 #define SCRB_XOR_UNIT 0
42 #define SCRB_XOR_CHAN 1
43 #define SCRB_XOR_WIN 0
45 #define XEBARX_BASE_OFFS 16
48 * mvebu_sdram_bar - reads SDRAM Base Address Register
50 u32
mvebu_sdram_bar(enum memory_bank bank
)
52 struct sdram_addr_dec
*base
=
53 (struct sdram_addr_dec
*)MVEBU_SDRAM_BASE
;
55 u32 enable
= 0x01 & readl(&base
->sdram_bank
[bank
].win_sz
);
57 if ((!enable
) || (bank
> BANK3
))
60 result
= readl(&base
->sdram_bank
[bank
].win_bar
);
65 * mvebu_sdram_bs_set - writes SDRAM Bank size
67 static void mvebu_sdram_bs_set(enum memory_bank bank
, u32 size
)
69 struct sdram_addr_dec
*base
=
70 (struct sdram_addr_dec
*)MVEBU_SDRAM_BASE
;
71 /* Read current register value */
72 u32 reg
= readl(&base
->sdram_bank
[bank
].win_sz
);
74 /* Clear window size */
75 reg
&= ~REG_CPUCS_WIN_SIZE(0xFF);
77 /* Set new window size */
78 reg
|= REG_CPUCS_WIN_SIZE((size
- 1) >> 24);
80 writel(reg
, &base
->sdram_bank
[bank
].win_sz
);
84 * mvebu_sdram_bs - reads SDRAM Bank size
86 u32
mvebu_sdram_bs(enum memory_bank bank
)
88 struct sdram_addr_dec
*base
=
89 (struct sdram_addr_dec
*)MVEBU_SDRAM_BASE
;
91 u32 enable
= 0x01 & readl(&base
->sdram_bank
[bank
].win_sz
);
93 if ((!enable
) || (bank
> BANK3
))
95 result
= 0xff000000 & readl(&base
->sdram_bank
[bank
].win_sz
);
100 void mvebu_sdram_size_adjust(enum memory_bank bank
)
104 /* probe currently equipped RAM size */
105 size
= get_ram_size((void *)mvebu_sdram_bar(bank
),
106 mvebu_sdram_bs(bank
));
108 /* adjust SDRAM window size accordingly */
109 mvebu_sdram_bs_set(bank
, size
);
112 #if defined(CONFIG_ARCH_MVEBU)
113 static u32 xor_ctrl_save
;
114 static u32 xor_base_save
;
115 static u32 xor_mask_save
;
117 static void mv_xor_init2(u32 cs
)
119 u32 reg
, base
, size
, base2
;
120 u32 bank_attr
[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
122 xor_ctrl_save
= reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT
,
124 xor_base_save
= reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT
,
126 xor_mask_save
= reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT
,
129 /* Enable Window x for each CS */
132 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT
, SCRB_XOR_CHAN
), reg
);
135 size
= mvebu_sdram_bs(cs
) - 1;
137 base2
= ((base
/ (64 << 10)) << XEBARX_BASE_OFFS
) |
139 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT
, SCRB_XOR_WIN
),
143 size
= (size
/ (64 << 10)) << 16;
144 /* Window x - size - 256 MB */
145 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT
, SCRB_XOR_WIN
), size
);
153 static void mv_xor_finish2(void)
155 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT
, SCRB_XOR_CHAN
),
157 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT
, SCRB_XOR_WIN
),
159 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT
, SCRB_XOR_WIN
),
163 static void dram_ecc_scrubbing(void)
172 * The DDR training code from the bin_hdr / SPL already
173 * scrubbed the DDR till 0x1000000. And the main U-Boot
174 * is loaded to an address < 0x1000000. So we need to
175 * skip this range to not re-scrub this area again.
177 temp
= reg_read(REG_SDRAM_CONFIG_ADDR
);
178 temp
|= (1 << REG_SDRAM_CONFIG_IERR_OFFS
);
179 reg_write(REG_SDRAM_CONFIG_ADDR
, temp
);
181 for (cs
= 0; cs
< CONFIG_NR_DRAM_BANKS
; cs
++) {
182 size
= mvebu_sdram_bs(cs
) - 1;
186 total
= (u64
)size
+ 1;
187 total_mem
+= (u32
)(total
/ (1 << 30));
191 /* Skip first 16 MiB */
193 start_addr
= 0x1000000;
197 mv_xor_mem_init(SCRB_XOR_CHAN
, start_addr
, size
,
198 SCRUB_MAGIC
, SCRUB_MAGIC
);
200 /* Wait for previous transfer completion */
201 while (mv_xor_state_get(SCRB_XOR_CHAN
) != MV_IDLE
)
207 temp
= reg_read(REG_SDRAM_CONFIG_ADDR
);
208 temp
&= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS
);
209 reg_write(REG_SDRAM_CONFIG_ADDR
, temp
);
212 static int ecc_enabled(void)
214 if (reg_read(REG_SDRAM_CONFIG_ADDR
) & (1 << REG_SDRAM_CONFIG_ECC_OFFS
))
220 static void dram_ecc_scrubbing(void)
224 static int ecc_enabled(void)
235 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
237 * It is assumed that all memory banks are consecutive
239 * If the gap is found, ram_size will be reported for
240 * consecutive memory only
242 if (mvebu_sdram_bar(i
) != size
)
246 * Don't report more than 3GiB of SDRAM, otherwise there is no
247 * address space left for the internal registers etc.
249 size
+= mvebu_sdram_bs(i
);
250 if (size
> SDRAM_SIZE_MAX
)
251 size
= SDRAM_SIZE_MAX
;
254 for (; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
255 /* If above loop terminated prematurely, we need to set
256 * remaining banks' start address & size as 0. Otherwise other
257 * u-boot functions and Linux kernel gets wrong values which
258 * could result in crash */
259 gd
->bd
->bi_dram
[i
].start
= 0;
260 gd
->bd
->bi_dram
[i
].size
= 0;
265 dram_ecc_scrubbing();
273 * If this function is not defined here,
274 * board.c alters dram bank zero configuration defined above.
276 void dram_init_banksize(void)
281 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
282 gd
->bd
->bi_dram
[i
].start
= mvebu_sdram_bar(i
);
283 gd
->bd
->bi_dram
[i
].size
= mvebu_sdram_bs(i
);
285 /* Clip the banksize to 1GiB if it exceeds the max size */
286 size
+= gd
->bd
->bi_dram
[i
].size
;
287 if (size
> SDRAM_SIZE_MAX
)
288 mvebu_sdram_bs_set(i
, 0x40000000);
292 #if defined(CONFIG_ARCH_MVEBU)
293 void board_add_ram_info(int use_default
)
295 struct sar_freq_modes sar_freq
;
297 get_sar_freq(&sar_freq
);
298 printf(" (%d MHz, ", sar_freq
.d_clk
);