arch/arm/mach-mvebu/include/mach/cpu.h

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _MVEBU_CPU_H
  10 #define _MVEBU_CPU_H
  11
  12 #include <asm/system.h>
  13
  14 #ifndef __ASSEMBLY__
  15
  16 #define MVEBU_REG_PCIE_DEVID            (MVEBU_REG_PCIE_BASE + 0x00)
  17 #define MVEBU_REG_PCIE_REVID            (MVEBU_REG_PCIE_BASE + 0x08)
  18
  19 enum memory_bank {
  20         BANK0,
  21         BANK1,
  22         BANK2,
  23         BANK3
  24 };
  25
  26 enum cpu_winen {
  27         CPU_WIN_DISABLE,
  28         CPU_WIN_ENABLE
  29 };
  30
  31 enum cpu_target {
  32         CPU_TARGET_DRAM = 0x0,
  33         CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
  34         CPU_TARGET_ETH23 = 0x3,
  35         CPU_TARGET_PCIE02 = 0x4,
  36         CPU_TARGET_ETH01 = 0x7,
  37         CPU_TARGET_PCIE13 = 0x8,
  38         CPU_TARGET_SASRAM = 0x9,
  39         CPU_TARGET_NAND = 0xd,
  40 };
  41
  42 enum cpu_attrib {
  43         CPU_ATTR_SASRAM = 0x01,
  44         CPU_ATTR_DRAM_CS0 = 0x0e,
  45         CPU_ATTR_DRAM_CS1 = 0x0d,
  46         CPU_ATTR_DRAM_CS2 = 0x0b,
  47         CPU_ATTR_DRAM_CS3 = 0x07,
  48         CPU_ATTR_NANDFLASH = 0x2f,
  49         CPU_ATTR_SPIFLASH = 0x1e,
  50         CPU_ATTR_BOOTROM = 0x1d,
  51         CPU_ATTR_PCIE_IO = 0xe0,
  52         CPU_ATTR_PCIE_MEM = 0xe8,
  53         CPU_ATTR_DEV_CS0 = 0x3e,
  54         CPU_ATTR_DEV_CS1 = 0x3d,
  55         CPU_ATTR_DEV_CS2 = 0x3b,
  56         CPU_ATTR_DEV_CS3 = 0x37,
  57 };
  58
  59 enum {
  60         MVEBU_SOC_AXP,
  61         MVEBU_SOC_A38X,
  62         MVEBU_SOC_UNKNOWN,
  63 };
  64
  65 /*
  66  * Default Device Address MAP BAR values
  67  */
  68 #define DEFADR_PCI_MEM          0x90000000
  69 #define DEFADR_PCI_IO           0xC0000000
  70 #define DEFADR_SPIF             0xF4000000
  71 #define DEFADR_BOOTROM          0xF8000000
  72
  73 struct mbus_win {
  74         u32 base;
  75         u32 size;
  76         u8 target;
  77         u8 attr;
  78 };
  79
  80 /*
  81  * System registers
  82  * Ref: Datasheet sec:A.28
  83  */
  84 struct mvebu_system_registers {
  85         u8 pad1[0x60];
  86         u32 rstoutn_mask; /* 0x60 */
  87         u32 sys_soft_rst; /* 0x64 */
  88 };
  89
  90 /*
  91  * GPIO Registers
  92  * Ref: Datasheet sec:A.19
  93  */
  94 struct kwgpio_registers {
  95         u32 dout;
  96         u32 oe;
  97         u32 blink_en;
  98         u32 din_pol;
  99         u32 din;
 100         u32 irq_cause;
 101         u32 irq_mask;
 102         u32 irq_level;
 103 };
 104
 105 /* Needed for dynamic (board-specific) mbus configuration */
 106 extern struct mvebu_mbus_state mbus_state;
 107
 108 /*
 109  * functions
 110  */
 111 unsigned int mvebu_sdram_bar(enum memory_bank bank);
 112 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 113 void mvebu_sdram_size_adjust(enum memory_bank bank);
 114 int mvebu_mbus_probe(struct mbus_win windows[], int count);
 115 int mvebu_soc_family(void);
 116
 117 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
 118
 119 /*
 120  * Highspeed SERDES PHY config init, ported from bin_hdr
 121  * to mainline U-Boot
 122  */
 123 int serdes_phy_config(void);
 124
 125 /*
 126  * DDR3 init / training code ported from Marvell bin_hdr. Now
 127  * available in mainline U-Boot in:
 128  * drivers/ddr/marvell
 129  */
 130 int ddr3_init(void);
 131 #endif /* __ASSEMBLY__ */
 132 #endif /* _MVEBU_CPU_H */