arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <spl.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/soc.h>
  13
  14 #include "high_speed_topology_spec.h"
  15 #include "sys_env_lib.h"
  16
  17 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
  18 /*
  19  * This is an example implementation for this custom board
  20  * specific function
  21  */
  22 static struct serdes_map custom_board_topology_config[] = {
  23         /* Customer Board Topology - reference from Marvell DB-GP board */
  24         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  25         {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  26         {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  27         {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  28         {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  29         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  30 };
  31
  32 int hws_board_topology_load(struct serdes_map *serdes_map_array)
  33 {
  34         serdes_map_array = custom_board_topology_config;
  35 }
  36 #endif
  37
  38 load_topology_func_ptr load_topology_func_arr[] = {
  39         load_topology_rd,       /* RD NAS */
  40         load_topology_db,       /* 6820 DB-BP (A38x) */
  41         load_topology_rd,       /* RD AP */
  42         load_topology_db_ap,    /* DB AP */
  43         load_topology_db_gp,    /* DB GP */
  44         load_topology_db_381,   /* 6821 DB-BP (A381) */
  45         load_topology_db_amc,   /* DB-AMC */
  46 };
  47
  48 /*****************************************/
  49 /** Load topology - Marvell 380 DB - BP **/
  50 /*****************************************/
  51 /* Configuration options */
  52 struct serdes_map db_config_default[MAX_SERDES_LANES] = {
  53         {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  54         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  55         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  56         {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  57         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  58         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  59 };
  60
  61 struct serdes_map db_config_slm1363_c[MAX_SERDES_LANES] = {
  62         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  63         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
  64         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  65         {PEX3, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  66         {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  67         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
  68 };
  69
  70 struct serdes_map db_config_slm1363_d[MAX_SERDES_LANES] = {
  71         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
  72         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
  73         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
  74         {PEX3, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
  75         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  76         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  77 };
  78
  79 struct serdes_map db_config_slm1363_e[MAX_SERDES_LANES] = {
  80         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  81         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  82         {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  83         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  84         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
  85         {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  86 };
  87
  88 struct serdes_map db_config_slm1363_f[MAX_SERDES_LANES] = {
  89         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  90         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
  91         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  92         {PEX3, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  93         {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  94         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  95 };
  96
  97 struct serdes_map db_config_slm1364_d[MAX_SERDES_LANES] = {
  98         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
  99         {SGMII0, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 100         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
 101         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
 102         {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 103         {SGMII2, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0}
 104 };
 105
 106 struct serdes_map db_config_slm1364_e[MAX_SERDES_LANES] = {
 107         {SGMII0, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 108         {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 109         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
 110         {SGMII2, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 111         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
 112         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
 113 };
 114
 115 struct serdes_map db_config_slm1364_f[MAX_SERDES_LANES] = {
 116         {SGMII0, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 117         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
 118         {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 119         {SGMII2, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 120         {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0, 0},
 121         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
 122 };
 123
 124 /*************************************************************************/
 125 /** The following structs are mapping for DB board 'SatR' configuration **/
 126 /*************************************************************************/
 127 struct serdes_map db_satr_config_lane1[SATR_DB_LANE1_MAX_OPTIONS] = {
 128         /* 0 */ {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0,
 129                  0},
 130         /* 1 */ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 131         /* 2 */ {SATA0, SERDES_SPEED_3_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 132         /* 3 */ {SGMII0, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 133                  0},
 134         /* 4 */ {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 135                  0},
 136         /* 5 */ {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0,
 137                  0},
 138         /* 6 */ {QSGMII, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
 139 };
 140
 141 struct serdes_map db_satr_config_lane2[SATR_DB_LANE2_MAX_OPTIONS] = {
 142         /* 0 */ {DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE, 0,
 143                  0},
 144         /* 1 */ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 145         /* 2 */ {SATA1, SERDES_SPEED_3_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 146         /* 3 */ {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 147                  0}
 148 };
 149
 150 /*******************************************************/
 151 /* Configuration options DB ****************************/
 152 /* mapping from TWSI address data to configuration map */
 153 /*******************************************************/
 154 struct serdes_map *topology_config_db[] = {
 155         db_config_slm1363_c,
 156         db_config_slm1363_d,
 157         db_config_slm1363_e,
 158         db_config_slm1363_f,
 159         db_config_slm1364_d,
 160         db_config_slm1364_e,
 161         db_config_slm1364_f,
 162         db_config_default
 163 };
 164
 165 /*************************************/
 166 /** Load topology - Marvell DB - AP **/
 167 /*************************************/
 168 struct serdes_map db_ap_config_default[MAX_SERDES_LANES] = {
 169         /* 0 */ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 170         /* 1 */ {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 171                  0},
 172         /* 2 */ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 173         /* 3 */ {SGMII2, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 174                  0},
 175         /* 4 */ {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0,
 176                  0},
 177         /* 5 */ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
 178 };
 179
 180 /*************************************/
 181 /** Load topology - Marvell DB - GP **/
 182 /*************************************/
 183 struct serdes_map db_gp_config_default[MAX_SERDES_LANES] = {
 184         /* 0 */ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 185         /* 1 */ {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 186         /* 2 */ {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 187         /* 3 */ {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 188         /* 4 */ {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 189         /* 5 */ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0,
 190                  0}
 191 };
 192
 193 struct serdes_map db_amc_config_default[MAX_SERDES_LANES] = {
 194         /* 0 */ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
 195         /* 1 */ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
 196         /* 2 */ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
 197         /* 3 */ {PEX3, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
 198         /* 4 */ {SGMII1, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 199                  0},
 200         /* 5 */ {SGMII2, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 0,
 201                  0},
 202 };
 203
 204 /*****************************************/
 205 /** Load topology - Marvell 381 DB - BP **/
 206 /*****************************************/
 207 /* Configuration options */
 208 struct serdes_map db381_config_default[MAX_SERDES_LANES] = {
 209         {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 1, 1},
 210         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 211         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
 212         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
 213 };
 214
 215 struct serdes_map db_config_slm1427[MAX_SERDES_LANES] = {
 216         {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 1, 1},
 217         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 1, 1},
 218         {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 1, 1},
 219         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 1, 1}
 220 };
 221
 222 struct serdes_map db_config_slm1426[MAX_SERDES_LANES] = {
 223         {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 1, 1},
 224         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 1, 1},
 225         {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 1, 1},
 226         {SGMII2, SERDES_SPEED_3_125_GBPS, SERDES_DEFAULT_MODE, 1, 1}
 227 };
 228
 229 /*
 230  * this array must be aligned with enum topology_config_db381 enum,
 231  * every update to this array requires update to enum topology_config_db381
 232  * enum
 233  */
 234 struct serdes_map *topology_config_db_381[] = {
 235         db_config_slm1427,
 236         db_config_slm1426,
 237         db381_config_default,
 238 };
 239
 240 u8 topology_config_db_mode_get(void)
 241 {
 242         u8 mode;
 243
 244         DEBUG_INIT_FULL_S("\n### topology_config_db_mode_get ###\n");
 245
 246         /* Default - return DB_CONFIG_DEFAULT */
 247
 248         if (!i2c_read(DB_GET_MODE_SLM1363_ADDR, 0, 1, &mode, 1)) {
 249                 switch (mode & 0xf) {
 250                 case 0xc:
 251                         DEBUG_INIT_S("\nInit DB board SLM 1363 C topology\n");
 252                         return DB_CONFIG_SLM1363_C;
 253                 case 0xd:
 254                         DEBUG_INIT_S("\nInit DB board SLM 1363 D topology\n");
 255                         return DB_CONFIG_SLM1363_D;
 256                 case 0xe:
 257                         DEBUG_INIT_S("\nInit DB board SLM 1363 E topology\n");
 258                         return DB_CONFIG_SLM1363_E;
 259                 case 0xf:
 260                         DEBUG_INIT_S("\nInit DB board SLM 1363 F topology\n");
 261                         return DB_CONFIG_SLM1363_F;
 262                 default:        /* not the right module */
 263                         break;
 264                 }
 265         }
 266
 267         /* SLM1364 Module */
 268         if (i2c_read(DB_GET_MODE_SLM1364_ADDR, 0, 1, &mode, 1)) {
 269                 DEBUG_INIT_S("\nInit DB board default topology\n");
 270                 return DB_CONFIG_DEFAULT;
 271         }
 272
 273         switch (mode & 0xf) {
 274         case 0xd:
 275                 DEBUG_INIT_S("\nInit DB board SLM 1364 D topology\n");
 276                 return DB_CONFIG_SLM1364_D;
 277         case 0xe:
 278                 DEBUG_INIT_S("\nInit DB board SLM 1364 E topology\n");
 279                 return DB_CONFIG_SLM1364_E;
 280         case 0xf:
 281                 DEBUG_INIT_S("\nInit DB board SLM 1364 F topology\n");
 282                 return DB_CONFIG_SLM1364_F;
 283         default:                /* Default configuration */
 284                 DEBUG_INIT_S("\nInit DB board default topology\n");
 285                 return DB_CONFIG_DEFAULT;
 286         }
 287 }
 288
 289 u8 topology_config_db_381_mode_get(void)
 290 {
 291         u8 mode;
 292
 293         DEBUG_INIT_FULL_S("\n### topology_config_db_381_mode_get ###\n");
 294
 295         if (!i2c_read(DB381_GET_MODE_SLM1426_1427_ADDR, 0, 2, &mode, 1)) {
 296                 switch (mode & 0xf) {
 297                 case 0x1:
 298                         DEBUG_INIT_S("\nInit DB-381 board SLM 1427 topology\n");
 299                         return DB_CONFIG_SLM1427;
 300                 case 0x2:
 301                         DEBUG_INIT_S("\nInit DB-381 board SLM 1426 topology\n");
 302                         return DB_CONFIG_SLM1426;
 303                 default:        /* not the right module */
 304                         break;
 305                 }
 306         }
 307
 308         /* in case not detected any supported module, use default topology */
 309         DEBUG_INIT_S("\nInit DB-381 board default topology\n");
 310         return DB_381_CONFIG_DEFAULT;
 311 }
 312
 313 /*
 314  * Read SatR field 'sgmiispeed' and update lane topology SGMII entries
 315  * speed setup
 316  */
 317 int update_topology_sgmii_speed(struct serdes_map *serdes_map_array)
 318 {
 319         u32 serdes_type, lane_num;
 320         u8 config_val;
 321
 322         /* Update SGMII speed settings by 'sgmiispeed' SatR value */
 323         for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
 324                 serdes_type = serdes_map_array[lane_num].serdes_type;
 325                 /*Read SatR configuration for SGMII speed */
 326                 if ((serdes_type == SGMII0) || (serdes_type == SGMII1) ||
 327                     (serdes_type == SGMII2)) {
 328                         /* Read SatR 'sgmiispeed' value */
 329                         if (i2c_read(EEPROM_I2C_ADDR, 0, 2, &config_val, 1)) {
 330                                 printf("%s: TWSI Read of 'sgmiispeed' failed\n",
 331                                        __func__);
 332                                 return MV_FAIL;
 333                         }
 334
 335                         if (0 == (config_val & 0x40)) {
 336                                 serdes_map_array[lane_num].serdes_speed =
 337                                         SERDES_SPEED_1_25_GBPS;
 338                         } else {
 339                                 serdes_map_array[lane_num].serdes_speed =
 340                                         SERDES_SPEED_3_125_GBPS;
 341                         }
 342                 }
 343         }
 344         return MV_OK;
 345 }
 346
 347 struct serdes_map default_lane = {
 348         DEFAULT_SERDES, LAST_SERDES_SPEED, SERDES_DEFAULT_MODE
 349 };
 350 int is_custom_topology = 0;     /* indicate user of non-default topology */
 351
 352 /*
 353  * Read SatR fields (dbserdes1/2 , gpserdes1/2/5) and update lane
 354  * topology accordingly
 355  */
 356 int update_topology_satr(struct serdes_map *serdes_map_array)
 357 {
 358         u8 config_val, lane_select, i;
 359         u32 board_id = mv_board_id_get();
 360
 361         switch (board_id) {
 362         case DB_68XX_ID:        /* read 'dbserdes1' & 'dbserdes2' */
 363         case DB_BP_6821_ID:
 364                 if (i2c_read(EEPROM_I2C_ADDR, 1, 2, &config_val, 1)) {
 365                         printf("%s: TWSI Read of 'dbserdes1/2' failed\n",
 366                                __func__);
 367                         return MV_FAIL;
 368                 }
 369
 370                 /* Lane #1 */
 371                 lane_select = (config_val & SATR_DB_LANE1_CFG_MASK) >>
 372                         SATR_DB_LANE1_CFG_OFFSET;
 373                 if (lane_select >= SATR_DB_LANE1_MAX_OPTIONS) {
 374                         printf("\n\%s: Error: invalid value for SatR field 'dbserdes1' (%x)\n",
 375                                __func__, lane_select);
 376                         printf("\t_skipping Topology update (run 'SatR write default')\n");
 377                         return MV_FAIL;
 378                 }
 379
 380                 /*
 381                  * If modified default serdes_type for lane#1, update
 382                  * topology and mark it as custom
 383                  */
 384                 if (serdes_map_array[1].serdes_type !=
 385                     db_satr_config_lane1[lane_select].serdes_type) {
 386                         serdes_map_array[1] = db_satr_config_lane1[lane_select];
 387                         is_custom_topology = 1;
 388                         /* DB 381/2 board has inverted SerDes polarity */
 389                         if (board_id == DB_BP_6821_ID)
 390                                 serdes_map_array[1].swap_rx =
 391                                         serdes_map_array[1].swap_tx = 1;
 392                 }
 393
 394                 /* Lane #2 */
 395                 lane_select = (config_val & SATR_DB_LANE2_CFG_MASK) >>
 396                         SATR_DB_LANE2_CFG_OFFSET;
 397                 if (lane_select >= SATR_DB_LANE2_MAX_OPTIONS) {
 398                         printf("\n\%s: Error: invalid value for SatR field 'dbserdes2' (%x)\n",
 399                                __func__, lane_select);
 400                         printf("\t_skipping Topology update (run 'SatR write default')\n");
 401                         return MV_FAIL;
 402                 }
 403
 404                 /*
 405                  * If modified default serdes_type for lane@2, update
 406                  * topology and mark it as custom
 407                  */
 408                 if (serdes_map_array[2].serdes_type !=
 409                     db_satr_config_lane2[lane_select].serdes_type) {
 410                         serdes_map_array[2] = db_satr_config_lane2[lane_select];
 411                         is_custom_topology = 1;
 412                         /* DB 381/2 board has inverted SerDes polarity */
 413                         if (board_id == DB_BP_6821_ID)
 414                                 serdes_map_array[2].swap_rx =
 415                                         serdes_map_array[2].swap_tx = 1;
 416                 }
 417
 418                 if (is_custom_topology == 1) {
 419                         /*
 420                          * Check for conflicts with detected lane #1 and
 421                          * lane #2 (Disable conflicted lanes)
 422                          */
 423                         for (i = 0; i < hws_serdes_get_max_lane(); i++) {
 424                                 if (i != 1 && serdes_map_array[1].serdes_type ==
 425                                     serdes_map_array[i].serdes_type) {
 426                                         printf("\t_lane #%d Type conflicts with Lane #1 (Lane #%d disabled)\n",
 427                                                i, i);
 428                                         serdes_map_array[i] =
 429                                                 db_satr_config_lane1[0];
 430                                 }
 431
 432                                 if (i != 2 &&
 433                                     serdes_map_array[2].serdes_type ==
 434                                     serdes_map_array[i].serdes_type) {
 435                                         printf("\t_lane #%d Type conflicts with Lane #2 (Lane #%d disabled)\n",
 436                                                i, i);
 437                                         serdes_map_array[i] =
 438                                                 db_satr_config_lane1[0];
 439                                 }
 440                         }
 441                 }
 442
 443                 break;          /* case DB_68XX_ID */
 444         case DB_GP_68XX_ID:     /* read 'gpserdes1' & 'gpserdes2' */
 445                 if (i2c_read(EEPROM_I2C_ADDR, 2, 2, &config_val, 1)) {
 446                         printf("%s: TWSI Read of 'gpserdes1/2' failed\n",
 447                                __func__);
 448                         return MV_FAIL;
 449                 }
 450
 451                 /*
 452                  * Lane #1:
 453                  * lane_select = 0 --> SATA0,
 454                  * lane_select = 1 --> PCIe0 (mini PCIe)
 455                  */
 456                 lane_select = (config_val & SATR_GP_LANE1_CFG_MASK) >>
 457                         SATR_GP_LANE1_CFG_OFFSET;
 458                 if (lane_select == 1) {
 459                         serdes_map_array[1].serdes_mode = PEX0;
 460                         serdes_map_array[1].serdes_speed = SERDES_SPEED_5_GBPS;
 461                         serdes_map_array[1].serdes_type = PEX_ROOT_COMPLEX_X1;
 462                         /*
 463                          * If lane 1 is set to PCIe0 --> disable PCIe0
 464                          * on lane 0
 465                          */
 466                         serdes_map_array[0] = default_lane;
 467                         /* indicate user of non-default topology */
 468                         is_custom_topology = 1;
 469                 }
 470                 printf("Lane 1 detection: %s\n",
 471                        lane_select ? "PCIe0 (mini PCIe)" : "SATA0");
 472
 473                 /*
 474                  * Lane #2:
 475                  * lane_select = 0 --> SATA1,
 476                  * lane_select = 1 --> PCIe1 (mini PCIe)
 477                  */
 478                 lane_select = (config_val & SATR_GP_LANE2_CFG_MASK) >>
 479                         SATR_GP_LANE2_CFG_OFFSET;
 480                 if (lane_select == 1) {
 481                         serdes_map_array[2].serdes_type = PEX1;
 482                         serdes_map_array[2].serdes_speed = SERDES_SPEED_5_GBPS;
 483                         serdes_map_array[2].serdes_mode = PEX_ROOT_COMPLEX_X1;
 484                         /* indicate user of non-default topology */
 485                         is_custom_topology = 1;
 486                 }
 487                 printf("Lane 2 detection: %s\n",
 488                        lane_select ? "PCIe1 (mini PCIe)" : "SATA1");
 489                 break;          /* case DB_GP_68XX_ID */
 490         }
 491
 492         if (is_custom_topology)
 493                 printf("\nDetected custom SerDes topology (to restore default run 'SatR write default')\n\n");
 494
 495         return MV_OK;
 496 }
 497
 498 /*
 499  * hws_update_device_toplogy
 500  * DESCRIPTION: Update the default board topology for specific device Id
 501  * INPUT:
 502  *      topology_config_ptr - pointer to the Serdes mapping
 503  *      topology_mode - topology mode (index)
 504  * OUTPUT: None
 505  * RRETURNS:
 506  *      MV_OK - if updating the board topology success
 507  *      MV_BAD_PARAM - if the input parameter is wrong
 508  */
 509 int hws_update_device_toplogy(struct serdes_map *topology_config_ptr,
 510                               enum topology_config_db topology_mode)
 511 {
 512         u32 dev_id = sys_env_device_id_get();
 513         u32 board_id = mv_board_id_get();
 514
 515         switch (topology_mode) {
 516         case DB_CONFIG_DEFAULT:
 517                 switch (dev_id) {
 518                 case MV_6810:
 519                         /*
 520                          * DB-AP : default for Lane3=SGMII2 -->
 521                          * 6810 supports only 2 SGMII interfaces:
 522                          * lane 3 disabled
 523                          */
 524                         if (board_id == DB_AP_68XX_ID) {
 525                                 printf("Device 6810 supports only 2 SGMII interfaces: SGMII-2 @ lane3 disabled\n");
 526                                 topology_config_ptr[3] = default_lane;
 527                         }
 528
 529                         /*
 530                          * 6810 has only 4 SerDes and the forth one is
 531                          * Serdes number 5 (i.e. Serdes 4 is not connected),
 532                          * therefore we need to copy SerDes 5 configuration
 533                          * to SerDes 4
 534                          */
 535                         printf("Device 6810 does not supports SerDes Lane #4: replaced topology entry with lane #5\n");
 536                         topology_config_ptr[4] = topology_config_ptr[5];
 537
 538                         /*
 539                          * No break between cases since the 1st
 540                          * 6820 limitation apply on 6810
 541                          */
 542                 case MV_6820:
 543                         /*
 544                          * DB-GP & DB-BP: default for Lane3=SATA3 -->
 545                          * 6810/20 supports only 2 SATA interfaces:
 546                          * lane 3 disabled
 547                          */
 548                         if ((board_id == DB_68XX_ID) ||
 549                             (board_id == DB_GP_68XX_ID)) {
 550                                 printf("Device 6810/20 supports only 2 SATA interfaces: SATA Port 3 @ lane3 disabled\n");
 551                                 topology_config_ptr[3] = default_lane;
 552                         }
 553                         /*
 554                          * DB-GP on 6820 only: default for Lane4=SATA2
 555                          * --> 6820 supports only 2 SATA interfaces:
 556                          * lane 3 disabled
 557                          */
 558                         if (board_id == DB_GP_68XX_ID && dev_id == MV_6820) {
 559                                 printf("Device 6820 supports only 2 SATA interfaces: SATA Port 2 @ lane4 disabled\n");
 560                                 topology_config_ptr[4] = default_lane;
 561                         }
 562                         break;
 563                 default:
 564                         break;
 565                 }
 566                 break;
 567
 568         default:
 569                 printf("sys_env_update_device_toplogy: selected topology is not supported by this routine\n");
 570                 break;
 571         }
 572
 573         return MV_OK;
 574 }
 575
 576 int load_topology_db_381(struct serdes_map *serdes_map_array)
 577 {
 578         u32 lane_num;
 579         u8 topology_mode;
 580         struct serdes_map *topology_config_ptr;
 581         u8 twsi_data;
 582         u8 usb3_host0_or_device = 0, usb3_host1_or_device = 0;
 583
 584         printf("\nInitialize DB-88F6821-BP board topology\n");
 585
 586         /* Getting the relevant topology mode (index) */
 587         topology_mode = topology_config_db_381_mode_get();
 588         topology_config_ptr = topology_config_db_381[topology_mode];
 589
 590         /* Read USB3.0 mode: HOST/DEVICE */
 591         if (load_topology_usb_mode_get(&twsi_data) == MV_OK) {
 592                 usb3_host0_or_device = (twsi_data & 0x1);
 593                 /* Only one USB3 device is enabled */
 594                 if (usb3_host0_or_device == 0)
 595                         usb3_host1_or_device = ((twsi_data >> 1) & 0x1);
 596         }
 597
 598         /* Updating the topology map */
 599         for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
 600                 serdes_map_array[lane_num].serdes_mode =
 601                         topology_config_ptr[lane_num].serdes_mode;
 602                 serdes_map_array[lane_num].serdes_speed =
 603                         topology_config_ptr[lane_num].serdes_speed;
 604                 serdes_map_array[lane_num].serdes_type =
 605                         topology_config_ptr[lane_num].serdes_type;
 606                 serdes_map_array[lane_num].swap_rx =
 607                         topology_config_ptr[lane_num].swap_rx;
 608                 serdes_map_array[lane_num].swap_tx =
 609                         topology_config_ptr[lane_num].swap_tx;
 610
 611                 /* Update USB3 device if needed */
 612                 if (usb3_host0_or_device == 1 &&
 613                     serdes_map_array[lane_num].serdes_type == USB3_HOST0)
 614                         serdes_map_array[lane_num].serdes_type = USB3_DEVICE;
 615
 616                 if (usb3_host1_or_device == 1 &&
 617                     serdes_map_array[lane_num].serdes_type == USB3_HOST1)
 618                         serdes_map_array[lane_num].serdes_type = USB3_DEVICE;
 619         }
 620
 621         /* If not detected any SerDes Site module, read 'SatR' lane setup */
 622         if (topology_mode == DB_381_CONFIG_DEFAULT)
 623                 update_topology_satr(serdes_map_array);
 624
 625         /* update 'sgmiispeed' settings */
 626         update_topology_sgmii_speed(serdes_map_array);
 627
 628         return MV_OK;
 629 }
 630
 631 int load_topology_db(struct serdes_map *serdes_map_array)
 632 {
 633         u32 lane_num;
 634         u8 topology_mode;
 635         struct serdes_map *topology_config_ptr;
 636         u8 twsi_data;
 637         u8 usb3_host0_or_device = 0, usb3_host1_or_device = 0;
 638
 639         printf("\nInitialize DB-88F6820-BP board topology\n");
 640
 641         /* Getting the relevant topology mode (index) */
 642         topology_mode = topology_config_db_mode_get();
 643
 644         if (topology_mode == DB_NO_TOPOLOGY)
 645                 topology_mode = DB_CONFIG_DEFAULT;
 646
 647         topology_config_ptr = topology_config_db[topology_mode];
 648
 649         /* Update the default board topology device flavours */
 650         CHECK_STATUS(hws_update_device_toplogy
 651                      (topology_config_ptr, topology_mode));
 652
 653         /* Read USB3.0 mode: HOST/DEVICE */
 654         if (load_topology_usb_mode_get(&twsi_data) == MV_OK) {
 655                 usb3_host0_or_device = (twsi_data & 0x1);
 656                 /* Only one USB3 device is enabled */
 657                 if (usb3_host0_or_device == 0)
 658                         usb3_host1_or_device = ((twsi_data >> 1) & 0x1);
 659         }
 660
 661         /* Updating the topology map */
 662         for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
 663                 serdes_map_array[lane_num].serdes_mode =
 664                         topology_config_ptr[lane_num].serdes_mode;
 665                 serdes_map_array[lane_num].serdes_speed =
 666                         topology_config_ptr[lane_num].serdes_speed;
 667                 serdes_map_array[lane_num].serdes_type =
 668                         topology_config_ptr[lane_num].serdes_type;
 669                 serdes_map_array[lane_num].swap_rx =
 670                         topology_config_ptr[lane_num].swap_rx;
 671                 serdes_map_array[lane_num].swap_tx =
 672                         topology_config_ptr[lane_num].swap_tx;
 673
 674                 /*
 675                  * Update USB3 device if needed - relevant for
 676                  * lane 3,4,5 only
 677                  */
 678                 if (lane_num >= 3) {
 679                         if ((serdes_map_array[lane_num].serdes_type ==
 680                              USB3_HOST0) && (usb3_host0_or_device == 1))
 681                                 serdes_map_array[lane_num].serdes_type =
 682                                         USB3_DEVICE;
 683
 684                         if ((serdes_map_array[lane_num].serdes_type ==
 685                              USB3_HOST1) && (usb3_host1_or_device == 1))
 686                                 serdes_map_array[lane_num].serdes_type =
 687                                         USB3_DEVICE;
 688                 }
 689         }
 690
 691         /* If not detected any SerDes Site module, read 'SatR' lane setup */
 692         if (topology_mode == DB_CONFIG_DEFAULT)
 693                 update_topology_satr(serdes_map_array);
 694
 695         /* update 'sgmiispeed' settings */
 696         update_topology_sgmii_speed(serdes_map_array);
 697
 698         return MV_OK;
 699 }
 700
 701 int load_topology_db_ap(struct serdes_map *serdes_map_array)
 702 {
 703         u32 lane_num;
 704         struct serdes_map *topology_config_ptr;
 705
 706         DEBUG_INIT_FULL_S("\n### load_topology_db_ap ###\n");
 707
 708         printf("\nInitialize DB-AP board topology\n");
 709         topology_config_ptr = db_ap_config_default;
 710
 711         /* Update the default board topology device flavours */
 712         CHECK_STATUS(hws_update_device_toplogy
 713                      (topology_config_ptr, DB_CONFIG_DEFAULT));
 714
 715         /* Updating the topology map */
 716         for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
 717                 serdes_map_array[lane_num].serdes_mode =
 718                         topology_config_ptr[lane_num].serdes_mode;
 719                 serdes_map_array[lane_num].serdes_speed =
 720                         topology_config_ptr[lane_num].serdes_speed;
 721                 serdes_map_array[lane_num].serdes_type =
 722                         topology_config_ptr[lane_num].serdes_type;
 723                 serdes_map_array[lane_num].swap_rx =
 724                         topology_config_ptr[lane_num].swap_rx;
 725                 serdes_map_array[lane_num].swap_tx =
 726                         topology_config_ptr[lane_num].swap_tx;
 727         }
 728
 729         update_topology_sgmii_speed(serdes_map_array);
 730
 731         return MV_OK;
 732 }
 733
 734 int load_topology_db_gp(struct serdes_map *serdes_map_array)
 735 {
 736         u32 lane_num;
 737         struct serdes_map *topology_config_ptr;
 738         int is_sgmii = 0;
 739
 740         DEBUG_INIT_FULL_S("\n### load_topology_db_gp ###\n");
 741
 742         topology_config_ptr = db_gp_config_default;
 743
 744         printf("\nInitialize DB-GP board topology\n");
 745
 746         /* check S@R: if lane 5 is USB3 or SGMII */
 747         if (load_topology_rd_sgmii_usb(&is_sgmii) != MV_OK)
 748                 printf("%s: TWSI Read failed - Loading Default Topology\n",
 749                        __func__);
 750         else {
 751                 topology_config_ptr[5].serdes_type =
 752                         is_sgmii ? SGMII2 : USB3_HOST1;
 753                 topology_config_ptr[5].serdes_speed = is_sgmii ?
 754                         SERDES_SPEED_3_125_GBPS : SERDES_SPEED_5_GBPS;
 755                 topology_config_ptr[5].serdes_mode = SERDES_DEFAULT_MODE;
 756         }
 757
 758         /* Update the default board topology device flavours */
 759         CHECK_STATUS(hws_update_device_toplogy
 760                      (topology_config_ptr, DB_CONFIG_DEFAULT));
 761
 762         /* Updating the topology map */
 763         for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
 764                 serdes_map_array[lane_num].serdes_mode =
 765                         topology_config_ptr[lane_num].serdes_mode;
 766                 serdes_map_array[lane_num].serdes_speed =
 767                         topology_config_ptr[lane_num].serdes_speed;
 768                 serdes_map_array[lane_num].serdes_type =
 769                         topology_config_ptr[lane_num].serdes_type;
 770                 serdes_map_array[lane_num].swap_rx =
 771                         topology_config_ptr[lane_num].swap_rx;
 772                 serdes_map_array[lane_num].swap_tx =
 773                         topology_config_ptr[lane_num].swap_tx;
 774         }
 775
 776         /*
 777          * Update 'gpserdes1/2/3' lane configuration , and 'sgmiispeed'
 778          * for SGMII lanes
 779          */
 780         update_topology_satr(serdes_map_array);
 781         update_topology_sgmii_speed(serdes_map_array);
 782
 783         return MV_OK;
 784 }
 785
 786 int load_topology_db_amc(struct serdes_map *serdes_map_array)
 787 {
 788         u32 lane_num;
 789         struct serdes_map *topology_config_ptr;
 790
 791         DEBUG_INIT_FULL_S("\n### load_topology_db_amc ###\n");
 792
 793         printf("\nInitialize DB-AMC board topology\n");
 794         topology_config_ptr = db_amc_config_default;
 795
 796         /* Update the default board topology device flavours */
 797         CHECK_STATUS(hws_update_device_toplogy
 798                      (topology_config_ptr, DB_CONFIG_DEFAULT));
 799
 800         /* Updating the topology map */
 801         for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
 802                 serdes_map_array[lane_num].serdes_mode =
 803                         topology_config_ptr[lane_num].serdes_mode;
 804                 serdes_map_array[lane_num].serdes_speed =
 805                         topology_config_ptr[lane_num].serdes_speed;
 806                 serdes_map_array[lane_num].serdes_type =
 807                         topology_config_ptr[lane_num].serdes_type;
 808                 serdes_map_array[lane_num].swap_rx =
 809                         topology_config_ptr[lane_num].swap_rx;
 810                 serdes_map_array[lane_num].swap_tx =
 811                         topology_config_ptr[lane_num].swap_tx;
 812         }
 813
 814         update_topology_sgmii_speed(serdes_map_array);
 815
 816         return MV_OK;
 817 }
 818
 819 int load_topology_rd(struct serdes_map *serdes_map_array)
 820 {
 821         u8 mode;
 822
 823         DEBUG_INIT_FULL_S("\n### load_topology_rd ###\n");
 824
 825         DEBUG_INIT_S("\nInit RD board ");
 826
 827         /* Reading mode */
 828         DEBUG_INIT_FULL_S("load_topology_rd: getting mode\n");
 829         if (i2c_read(EEPROM_I2C_ADDR, 0, 2, &mode, 1)) {
 830                 DEBUG_INIT_S("load_topology_rd: TWSI Read failed\n");
 831                 return MV_FAIL;
 832         }
 833
 834         /* Updating the topology map */
 835         DEBUG_INIT_FULL_S("load_topology_rd: Loading board topology details\n");
 836
 837         /* RD mode: 0 = NAS, 1 = AP */
 838         if (((mode >> 1) & 0x1) == 0) {
 839                 CHECK_STATUS(load_topology_rd_nas(serdes_map_array));
 840         } else {
 841                 CHECK_STATUS(load_topology_rd_ap(serdes_map_array));
 842         }
 843
 844         update_topology_sgmii_speed(serdes_map_array);
 845
 846         return MV_OK;
 847 }
 848
 849 int load_topology_rd_nas(struct serdes_map *serdes_map_array)
 850 {
 851         int is_sgmii = 0;
 852         u32 i;
 853
 854         DEBUG_INIT_S("\nInit RD NAS topology ");
 855
 856         /* check if lane 4 is USB3 or SGMII */
 857         if (load_topology_rd_sgmii_usb(&is_sgmii) != MV_OK) {
 858                 DEBUG_INIT_S("load_topology_rd NAS: TWSI Read failed\n");
 859                 return MV_FAIL;
 860         }
 861
 862         /* Lane 0 */
 863         serdes_map_array[0].serdes_type = PEX0;
 864         serdes_map_array[0].serdes_speed = SERDES_SPEED_5_GBPS;
 865         serdes_map_array[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
 866
 867         /* Lane 1 */
 868         serdes_map_array[1].serdes_type = SATA0;
 869         serdes_map_array[1].serdes_speed = SERDES_SPEED_3_GBPS;
 870         serdes_map_array[1].serdes_mode = SERDES_DEFAULT_MODE;
 871
 872         /* Lane 2 */
 873         serdes_map_array[2].serdes_type = SATA1;
 874         serdes_map_array[2].serdes_speed = SERDES_SPEED_3_GBPS;
 875         serdes_map_array[2].serdes_mode = SERDES_DEFAULT_MODE;
 876
 877         /* Lane 3 */
 878         serdes_map_array[3].serdes_type = SATA3;
 879         serdes_map_array[3].serdes_speed = SERDES_SPEED_3_GBPS;
 880         serdes_map_array[3].serdes_mode = SERDES_DEFAULT_MODE;
 881
 882         /* Lane 4 */
 883         if (is_sgmii == 1) {
 884                 DEBUG_INIT_S("Serdes Lane 4 is SGMII\n");
 885                 serdes_map_array[4].serdes_type = SGMII1;
 886                 serdes_map_array[4].serdes_speed = SERDES_SPEED_3_125_GBPS;
 887                 serdes_map_array[4].serdes_mode = SERDES_DEFAULT_MODE;
 888         } else {
 889                 DEBUG_INIT_S("Serdes Lane 4 is USB3\n");
 890                 serdes_map_array[4].serdes_type = USB3_HOST0;
 891                 serdes_map_array[4].serdes_speed = SERDES_SPEED_5_GBPS;
 892                 serdes_map_array[4].serdes_mode = SERDES_DEFAULT_MODE;
 893         }
 894
 895         /* Lane 5 */
 896         serdes_map_array[5].serdes_type = SATA2;
 897         serdes_map_array[5].serdes_speed = SERDES_SPEED_3_GBPS;
 898         serdes_map_array[5].serdes_mode = SERDES_DEFAULT_MODE;
 899
 900         /* init swap configuration */
 901         for (i = 0; i <= 5; i++) {
 902                 serdes_map_array[i].swap_rx = 0;
 903                 serdes_map_array[i].swap_tx = 0;
 904         }
 905
 906         return MV_OK;
 907 }
 908
 909 int load_topology_rd_ap(struct serdes_map *serdes_map_array)
 910 {
 911         int is_sgmii = 0;
 912         u32 i;
 913
 914         DEBUG_INIT_S("\nInit RD AP topology ");
 915
 916         /* check if lane 4 is USB3 or SGMII */
 917         if (load_topology_rd_sgmii_usb(&is_sgmii) != MV_OK) {
 918                 DEBUG_INIT_S("load_topology_rd AP: TWSI Read failed\n");
 919                 return MV_FAIL;
 920         }
 921
 922         /* Lane 0 */
 923         serdes_map_array[0].serdes_type = DEFAULT_SERDES;
 924         serdes_map_array[0].serdes_speed = LAST_SERDES_SPEED;
 925         serdes_map_array[0].serdes_mode = SERDES_DEFAULT_MODE;
 926
 927         /* Lane 1 */
 928         serdes_map_array[1].serdes_type = PEX0;
 929         serdes_map_array[1].serdes_speed = SERDES_SPEED_5_GBPS;
 930         serdes_map_array[1].serdes_mode = PEX_ROOT_COMPLEX_X1;
 931
 932         /* Lane 2 */
 933         serdes_map_array[2].serdes_type = PEX1;
 934         serdes_map_array[2].serdes_speed = SERDES_SPEED_5_GBPS;
 935         serdes_map_array[2].serdes_mode = PEX_ROOT_COMPLEX_X1;
 936
 937         /* Lane 3 */
 938         serdes_map_array[3].serdes_type = SATA3;
 939         serdes_map_array[3].serdes_speed = SERDES_SPEED_3_GBPS;
 940         serdes_map_array[3].serdes_mode = SERDES_DEFAULT_MODE;
 941
 942         /* Lane 4 */
 943         if (is_sgmii == 1) {
 944                 DEBUG_INIT_S("Serdes Lane 4 is SGMII\n");
 945                 serdes_map_array[4].serdes_type = SGMII1;
 946                 serdes_map_array[4].serdes_speed = SERDES_SPEED_3_125_GBPS;
 947                 serdes_map_array[4].serdes_mode = SERDES_DEFAULT_MODE;
 948         } else {
 949                 DEBUG_INIT_S("Serdes Lane 4 is USB3\n");
 950                 serdes_map_array[4].serdes_type = USB3_HOST0;
 951                 serdes_map_array[4].serdes_speed = SERDES_SPEED_5_GBPS;
 952                 serdes_map_array[4].serdes_mode = SERDES_DEFAULT_MODE;
 953         }
 954
 955         /* Lane 5 */
 956         serdes_map_array[5].serdes_type = SATA2;
 957         serdes_map_array[5].serdes_speed = SERDES_SPEED_3_GBPS;
 958         serdes_map_array[5].serdes_mode = SERDES_DEFAULT_MODE;
 959
 960         /* init swap configuration */
 961         for (i = 0; i <= 5; i++) {
 962                 serdes_map_array[i].swap_rx = 0;
 963                 serdes_map_array[i].swap_tx = 0;
 964         }
 965
 966         return MV_OK;
 967 }
 968
 969 int load_topology_rd_sgmii_usb(int *is_sgmii)
 970 {
 971         u8 mode;
 972
 973         /*
 974          * DB-GP board: Device 6810 supports only 2 GbE ports:
 975          * SGMII2 not supported (USE USB3 Host instead)
 976          */
 977         if (sys_env_device_id_get() == MV_6810) {
 978                 printf("Device 6810 supports only 2 GbE ports: SGMII-2 @ lane5 disabled (setting USB3.0 H1 instead)\n");
 979                 *is_sgmii = 0;
 980                 return MV_OK;
 981         }
 982
 983         if (!i2c_read(RD_GET_MODE_ADDR, 1, 2, &mode, 1)) {
 984                 *is_sgmii = ((mode >> 2) & 0x1);
 985         } else {
 986                 /* else use the default - USB3 */
 987                 *is_sgmii = 0;
 988         }
 989
 990         if (*is_sgmii)
 991                 is_custom_topology = 1;
 992
 993         printf("Lane 5 detection: %s\n",
 994                *is_sgmii ? "SGMII2" : "USB3.0 Host Port 1");
 995
 996         return MV_OK;
 997 }
 998
 999 /*
1000  * 'usb3port0'/'usb3port1' fields are located in EEPROM,
1001  * at 3rd byte(offset=2), bit 0:1 (respectively)
1002  */
1003 int load_topology_usb_mode_get(u8 *twsi_data)
1004 {
1005         if (!i2c_read(EEPROM_I2C_ADDR, 2, 2, twsi_data, 1))
1006                 return MV_OK;
1007
1008         return MV_ERROR;
1009 }