arch/arm/mach-mvebu/serdes/axp/board_env_spec.h

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef __BOARD_ENV_SPEC
   8 #define __BOARD_ENV_SPEC
   9
  10 /* Board specific configuration */
  11
  12 /* KW40 */
  13 #define MV_6710_DEV_ID                  0x6710
  14
  15 #define MV_6710_Z1_REV                  0x0
  16 #define MV_6710_Z1_ID                   ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV)
  17 #define MV_6710_Z1_NAME                 "MV6710 Z1"
  18
  19 /* Armada XP Family */
  20 #define MV_78130_DEV_ID                 0x7813
  21 #define MV_78160_DEV_ID                 0x7816
  22 #define MV_78230_DEV_ID                 0x7823
  23 #define MV_78260_DEV_ID                 0x7826
  24 #define MV_78460_DEV_ID                 0x7846
  25 #define MV_78000_DEV_ID                 0x7888
  26
  27 #define MV_FPGA_DEV_ID                  0x2107
  28
  29 #define MV_78XX0_Z1_REV                 0x0
  30
  31 /* boards ID numbers */
  32 #define BOARD_ID_BASE                   0x0
  33
  34 /* New board ID numbers */
  35 #define DB_88F78XX0_BP_ID               (BOARD_ID_BASE)
  36 #define RD_78460_SERVER_ID              (DB_88F78XX0_BP_ID + 1)
  37 #define DB_78X60_PCAC_ID                (RD_78460_SERVER_ID + 1)
  38 #define FPGA_88F78XX0_ID                (DB_78X60_PCAC_ID + 1)
  39 #define DB_88F78XX0_BP_REV2_ID          (FPGA_88F78XX0_ID + 1)
  40 #define RD_78460_NAS_ID                 (DB_88F78XX0_BP_REV2_ID + 1)
  41 #define DB_78X60_AMC_ID                 (RD_78460_NAS_ID + 1)
  42 #define DB_78X60_PCAC_REV2_ID           (DB_78X60_AMC_ID + 1)
  43 #define RD_78460_SERVER_REV2_ID         (DB_78X60_PCAC_REV2_ID + 1)
  44 #define DB_784MP_GP_ID                  (RD_78460_SERVER_REV2_ID + 1)
  45 #define RD_78460_CUSTOMER_ID            (DB_784MP_GP_ID + 1)
  46 #define MV_MAX_BOARD_ID                 (RD_78460_CUSTOMER_ID + 1)
  47 #define INVALID_BAORD_ID                0xFFFFFFFF
  48
  49 /* Sample at Reset */
  50 #define MPP_SAMPLE_AT_RESET(id)         (0x18230 + (id * 4))
  51
  52 /* BIOS Modes related defines */
  53
  54 #define SAR0_BOOTWIDTH_OFFSET           3
  55 #define SAR0_BOOTWIDTH_MASK             (0x3 << SAR0_BOOTWIDTH_OFFSET)
  56 #define SAR0_BOOTSRC_OFFSET             5
  57 #define SAR0_BOOTSRC_MASK               (0xF << SAR0_BOOTSRC_OFFSET)
  58
  59 #define SAR0_L2_SIZE_OFFSET             19
  60 #define SAR0_L2_SIZE_MASK               (0x3 << SAR0_L2_SIZE_OFFSET)
  61 #define SAR0_CPU_FREQ_OFFSET            21
  62 #define SAR0_CPU_FREQ_MASK              (0x7 << SAR0_CPU_FREQ_OFFSET)
  63 #define SAR0_FABRIC_FREQ_OFFSET         24
  64 #define SAR0_FABRIC_FREQ_MASK           (0xF << SAR0_FABRIC_FREQ_OFFSET)
  65 #define SAR0_CPU0CORE_OFFSET            31
  66 #define SAR0_CPU0CORE_MASK              (0x1 << SAR0_CPU0CORE_OFFSET)
  67 #define SAR1_CPU0CORE_OFFSET            0
  68 #define SAR1_CPU0CORE_MASK              (0x1 << SAR1_CPU0CORE_OFFSET)
  69
  70 #define PEX_CLK_100MHZ_OFFSET           2
  71 #define PEX_CLK_100MHZ_MASK             (0x1 << PEX_CLK_100MHZ_OFFSET)
  72
  73 #define SAR1_FABRIC_MODE_OFFSET         19
  74 #define SAR1_FABRIC_MODE_MASK           (0x1 << SAR1_FABRIC_MODE_OFFSET)
  75 #define SAR1_CPU_MODE_OFFSET            20
  76 #define SAR1_CPU_MODE_MASK              (0x1 << SAR1_CPU_MODE_OFFSET)
  77
  78 #define SAR_CPU_FAB_GET(cpu, fab)       (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
  79
  80
  81 #define CORE_AVS_CONTROL_0REG           0x18300
  82 #define CORE_AVS_CONTROL_2REG           0x18308
  83 #define CPU_AVS_CONTROL2_REG            0x20868
  84 #define CPU_AVS_CONTROL0_REG            0x20860
  85 #define GENERAL_PURPOSE_RESERVED0_REG   0x182E0
  86
  87 #define MSAR_TCLK_OFFS                  28
  88 #define MSAR_TCLK_MASK                  (0x1 << MSAR_TCLK_OFFS)
  89
  90
  91 /* Controler environment registers offsets */
  92 #define GEN_PURP_RES_1_REG              0x182F4
  93 #define GEN_PURP_RES_2_REG              0x182F8
  94
  95 /* registers offsets */
  96 #define MV_GPP_REGS_OFFSET(unit)        (0x18100 + ((unit) * 0x40))
  97 #define MPP_CONTROL_REG(id)             (0x18000 + (id * 4))
  98 #define MV_GPP_REGS_BASE(unit)          (MV_GPP_REGS_OFFSET(unit))
  99 #define MV_GPP_REGS_BASE_0              (MV_GPP_REGS_OFFSET_0)
 100
 101 #define GPP_DATA_OUT_REG(grp)           (MV_GPP_REGS_BASE(grp) + 0x00)
 102 #define GPP_DATA_OUT_REG_0              (MV_GPP_REGS_BASE_0 + 0x00)     /* Used in .S files */
 103 #define GPP_DATA_OUT_EN_REG(grp)        (MV_GPP_REGS_BASE(grp) + 0x04)
 104 #define GPP_BLINK_EN_REG(grp)           (MV_GPP_REGS_BASE(grp) + 0x08)
 105 #define GPP_DATA_IN_POL_REG(grp)        (MV_GPP_REGS_BASE(grp) + 0x0C)
 106 #define GPP_DATA_IN_REG(grp)            (MV_GPP_REGS_BASE(grp) + 0x10)
 107 #define GPP_INT_CAUSE_REG(grp)          (MV_GPP_REGS_BASE(grp) + 0x14)
 108 #define GPP_INT_MASK_REG(grp)           (MV_GPP_REGS_BASE(grp) + 0x18)
 109 #define GPP_INT_LVL_REG(grp)            (MV_GPP_REGS_BASE(grp) + 0x1C)
 110 #define GPP_OUT_SET_REG(grp)            (0x18130 + ((grp) * 0x40))
 111 #define GPP_64_66_DATA_OUT_SET_REG      0x181A4
 112 #define GPP_OUT_CLEAR_REG(grp)          (0x18134 + ((grp) * 0x40))
 113 #define GPP_64_66_DATA_OUT_CLEAR_REG    0x181B0
 114 #define GPP_FUNC_SELECT_REG             (MV_GPP_REGS_BASE(0) + 0x40)
 115
 116 #define MV_GPP66                        (1 << 2)
 117
 118 /* Relevant for MV78XX0 */
 119 #define GPP_DATA_OUT_SET_REG            (MV_GPP_REGS_BASE(0) + 0x20)
 120 #define GPP_DATA_OUT_CLEAR_REG          (MV_GPP_REGS_BASE(0) + 0x24)
 121
 122 /* This define describes the maximum number of supported PEX Interfaces */
 123 #define MV_PEX_MAX_IF                   10
 124 #define MV_PEX_MAX_UNIT                 4
 125
 126 #define MV_SERDES_NUM_TO_PEX_NUM(num)   ((num < 8) ? (num) : (8 + (num / 12)))
 127
 128 #define PEX_PHY_ACCESS_REG(unit)        (0x40000 + ((unit) % 2 * 0x40000) + \
 129                                          ((unit)/2 * 0x2000) + 0x1B00)
 130
 131 #define SATA_BASE_REG(port)             (0xA2000 + (port)*0x2000)
 132
 133 #define SATA_PWR_PLL_CTRL_REG(port)     (SATA_BASE_REG(port) + 0x804)
 134 #define SATA_DIG_LP_ENA_REG(port)       (SATA_BASE_REG(port) + 0x88C)
 135 #define SATA_REF_CLK_SEL_REG(port)      (SATA_BASE_REG(port) + 0x918)
 136 #define SATA_COMPHY_CTRL_REG(port)      (SATA_BASE_REG(port) + 0x920)
 137 #define SATA_LP_PHY_EXT_CTRL_REG(port)  (SATA_BASE_REG(port) + 0x058)
 138 #define SATA_LP_PHY_EXT_STAT_REG(port)  (SATA_BASE_REG(port) + 0x05C)
 139 #define SATA_IMP_TX_SSC_CTRL_REG(port)  (SATA_BASE_REG(port) + 0x810)
 140 #define SATA_GEN_1_SET_0_REG(port)      (SATA_BASE_REG(port) + 0x834)
 141 #define SATA_GEN_1_SET_1_REG(port)      (SATA_BASE_REG(port) + 0x838)
 142 #define SATA_GEN_2_SET_0_REG(port)      (SATA_BASE_REG(port) + 0x83C)
 143 #define SATA_GEN_2_SET_1_REG(port)      (SATA_BASE_REG(port) + 0x840)
 144
 145 #define MV_ETH_BASE_ADDR                (0x72000)
 146 #define MV_ETH_REGS_OFFSET(port)        (MV_ETH_BASE_ADDR - ((port) / 2) * \
 147                                          0x40000 + ((port) % 2) * 0x4000)
 148 #define MV_ETH_REGS_BASE(port)          MV_ETH_REGS_OFFSET(port)
 149
 150
 151 #define SGMII_PWR_PLL_CTRL_REG(port)    (MV_ETH_REGS_BASE(port) + 0xE04)
 152 #define SGMII_DIG_LP_ENA_REG(port)      (MV_ETH_REGS_BASE(port) + 0xE8C)
 153 #define SGMII_REF_CLK_SEL_REG(port)     (MV_ETH_REGS_BASE(port) + 0xF18)
 154 #define SGMII_SERDES_CFG_REG(port)      (MV_ETH_REGS_BASE(port) + 0x4A0)
 155 #define SGMII_SERDES_STAT_REG(port)     (MV_ETH_REGS_BASE(port) + 0x4A4)
 156 #define SGMII_COMPHY_CTRL_REG(port)     (MV_ETH_REGS_BASE(port) + 0xF20)
 157 #define QSGMII_GEN_1_SETTING_REG(port)  (MV_ETH_REGS_BASE(port) + 0xE38)
 158 #define QSGMII_SERDES_CFG_REG(port)     (MV_ETH_REGS_BASE(port) + 0x4a0)
 159
 160 #define SERDES_LINE_MUX_REG_0_7         0x18270
 161 #define SERDES_LINE_MUX_REG_8_15        0x18274
 162 #define QSGMII_CONTROL_1_REG            0x18404
 163
 164 /* SOC_CTRL_REG fields */
 165 #define SCR_PEX_ENA_OFFS(pex)           ((pex) & 0x3)
 166 #define SCR_PEX_ENA_MASK(pex)           (1 << pex)
 167
 168 #define PCIE0_QUADX1_EN                 (1<<7)
 169 #define PCIE1_QUADX1_EN                 (1<<8)
 170
 171 #define SCR_PEX_4BY1_OFFS(pex)          ((pex) + 7)
 172 #define SCR_PEX_4BY1_MASK(pex)          (1 << SCR_PEX_4BY1_OFFS(pex))
 173
 174 #define PCIE1_CLK_OUT_EN_OFF            5
 175 #define PCIE1_CLK_OUT_EN_MASK           (1 << PCIE1_CLK_OUT_EN_OFF)
 176
 177 #define PCIE0_CLK_OUT_EN_OFF            4
 178 #define PCIE0_CLK_OUT_EN_MASK           (1 << PCIE0_CLK_OUT_EN_OFF)
 179
 180 #define SCR_PEX0_4BY1_OFFS              7
 181 #define SCR_PEX0_4BY1_MASK              (1 << SCR_PEX0_4BY1_OFFS)
 182
 183 #define SCR_PEX1_4BY1_OFFS              8
 184 #define SCR_PEX1_4BY1_MASK              (1 << SCR_PEX1_4BY1_OFFS)
 185
 186
 187 #define MV_MISC_REGS_OFFSET             (0x18200)
 188 #define MV_MISC_REGS_BASE               (MV_MISC_REGS_OFFSET)
 189 #define SOC_CTRL_REG                    (MV_MISC_REGS_BASE + 0x4)
 190
 191 /*
 192  * PCI Express Control and Status Registers
 193  */
 194 #define MAX_PEX_DEVICES                 32
 195 #define MAX_PEX_FUNCS                   8
 196 #define MAX_PEX_BUSSES                  256
 197
 198 #define PXSR_PEX_BUS_NUM_OFFS           8       /* Bus Number Indication */
 199 #define PXSR_PEX_BUS_NUM_MASK           (0xff << PXSR_PEX_BUS_NUM_OFFS)
 200
 201 #define PXSR_PEX_DEV_NUM_OFFS           16      /* Device Number Indication */
 202 #define PXSR_PEX_DEV_NUM_MASK           (0x1f << PXSR_PEX_DEV_NUM_OFFS)
 203
 204 #define PXSR_DL_DOWN                    0x1     /* DL_Down indication. */
 205 #define PXCAR_CONFIG_EN                 (1 << 31)
 206 #define PEX_STATUS_AND_COMMAND          0x004
 207 #define PXSAC_MABORT                    (1 << 29) /* Recieved Master Abort */
 208
 209 /* PCI Express Configuration Address Register */
 210
 211 /* PEX_CFG_ADDR_REG (PXCAR) */
 212 #define PXCAR_REG_NUM_OFFS              2
 213 #define PXCAR_REG_NUM_MAX               0x3F
 214 #define PXCAR_REG_NUM_MASK              (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
 215 #define PXCAR_FUNC_NUM_OFFS             8
 216 #define PXCAR_FUNC_NUM_MAX              0x7
 217 #define PXCAR_FUNC_NUM_MASK             (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
 218 #define PXCAR_DEVICE_NUM_OFFS           11
 219 #define PXCAR_DEVICE_NUM_MAX            0x1F
 220 #define PXCAR_DEVICE_NUM_MASK           (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
 221 #define PXCAR_BUS_NUM_OFFS              16
 222 #define PXCAR_BUS_NUM_MAX               0xFF
 223 #define PXCAR_BUS_NUM_MASK              (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
 224 #define PXCAR_EXT_REG_NUM_OFFS          24
 225 #define PXCAR_EXT_REG_NUM_MAX           0xF
 226
 227 #define PXCAR_REAL_EXT_REG_NUM_OFFS     8
 228 #define PXCAR_REAL_EXT_REG_NUM_MASK     (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
 229
 230
 231 #define PEX_CAPABILITIES_REG(if)        ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
 232 #define PEX_LINK_CAPABILITIES_REG(if)   ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
 233 #define PEX_LINK_CTRL_STATUS_REG(if)    ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
 234 #define PEX_LINK_CTRL_STATUS2_REG(if)   ((MV_PEX_IF_REGS_BASE(if)) + 0x90)
 235 #define PEX_CTRL_REG(if)                ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00)
 236 #define PEX_STATUS_REG(if)              ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04)
 237 #define PEX_COMPLT_TMEOUT_REG(if)       ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10)
 238 #define PEX_PWR_MNG_EXT_REG(if)         ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18)
 239 #define PEX_FLOW_CTRL_REG(if)           ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20)
 240 #define PEX_DYNMC_WIDTH_MNG_REG(if)     ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30)
 241 #define PEX_ROOT_CMPLX_SSPL_REG(if)     ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C)
 242 #define PEX_RAM_PARITY_CTRL_REG(if)     ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50)
 243 #define PEX_DBG_CTRL_REG(if)            ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60)
 244 #define PEX_DBG_STATUS_REG(if)          ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64)
 245
 246 #define PXLCSR_NEG_LNK_GEN_OFFS         16      /* Negotiated Link GEN */
 247 #define PXLCSR_NEG_LNK_GEN_MASK         (0xf << PXLCSR_NEG_LNK_GEN_OFFS)
 248 #define PXLCSR_NEG_LNK_GEN_1_1          (0x1 << PXLCSR_NEG_LNK_GEN_OFFS)
 249 #define PXLCSR_NEG_LNK_GEN_2_0          (0x2 << PXLCSR_NEG_LNK_GEN_OFFS)
 250
 251 #define PEX_CFG_ADDR_REG(if)            ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8)
 252 #define PEX_CFG_DATA_REG(if)            ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC)
 253 #define PEX_CAUSE_REG(if)               ((MV_PEX_IF_REGS_BASE(if)) + 0x1900)
 254
 255 #define PEX_CAPABILITY_REG              0x60
 256 #define PEX_DEV_CAPABILITY_REG          0x64
 257 #define PEX_DEV_CTRL_STAT_REG           0x68
 258 #define PEX_LINK_CAPABILITY_REG         0x6C
 259 #define PEX_LINK_CTRL_STAT_REG          0x70
 260 #define PEX_LINK_CTRL_STAT_2_REG        0x90
 261
 262 #endif /* __BOARD_ENV_SPEC */