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[people/ms/u-boot.git] / arch / arm / mach-mvebu / serdes / high_speed_env_lib.c
1 /*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <spl.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13
14 #include "high_speed_env_spec.h"
15 #include "board_env_spec.h"
16
17 #define SERDES_VERION "2.1.5"
18 #define ENDED_OK "High speed PHY - Ended Successfully\n"
19
20 static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
21
22 extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
23
24 extern u8 rd78460gp_twsi_dev[];
25 extern u8 db88f78xx0rev2_twsi_dev[];
26
27 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
28 int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
29 int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
30
31 #define MV_BOARD_PEX_MODULE_ADDR 0x23
32 #define MV_BOARD_PEX_MODULE_ID 1
33 #define MV_BOARD_ETM_MODULE_ID 2
34
35 #define PEX_MODULE_DETECT 1
36 #define ETM_MODULE_DETECT 2
37
38 #define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
39 #define PEX_CAPABILITY_GET(satr) (satr & 1)
40 #define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
41
42 /* Static parametes */
43 static int config_module;
44 static int switch_module;
45
46 /* Local function */
47 static u32 board_id_get(void)
48 {
49 #if defined(CONFIG_DB_88F78X60)
50 return DB_88F78XX0_BP_ID;
51 #elif defined(CONFIG_RD_88F78460_SERVER)
52 return RD_78460_SERVER_ID;
53 #elif defined(CONFIG_RD_78460_SERVER_REV2)
54 return RD_78460_SERVER_REV2_ID;
55 #elif defined(CONFIG_DB_78X60_PCAC)
56 return DB_78X60_PCAC_ID;
57 #elif defined(CONFIG_DB_88F78X60_REV2)
58 return DB_88F78XX0_BP_REV2_ID;
59 #elif defined(CONFIG_RD_78460_NAS)
60 return RD_78460_NAS_ID;
61 #elif defined(CONFIG_DB_78X60_AMC)
62 return DB_78X60_AMC_ID;
63 #elif defined(CONFIG_DB_78X60_PCAC_REV2)
64 return DB_78X60_PCAC_REV2_ID;
65 #elif defined(CONFIG_DB_784MP_GP)
66 return DB_784MP_GP_ID;
67 #elif defined(CONFIG_RD_78460_CUSTOMER)
68 return RD_78460_CUSTOMER_ID;
69 #else
70 /*
71 * Return 0 here for custom board as this should not be used
72 * for custom boards.
73 */
74 return 0;
75 #endif
76 }
77
78 static u8 board_sat_r_get(u8 dev_num, u8 reg)
79 {
80 u8 data;
81 u8 *dev;
82 u32 board_id = board_id_get();
83 int ret;
84
85 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
86
87 switch (board_id) {
88 case DB_784MP_GP_ID:
89 dev = rd78460gp_twsi_dev;
90
91 break;
92 case DB_88F78XX0_BP_ID:
93 case DB_88F78XX0_BP_REV2_ID:
94 dev = db88f78xx0rev2_twsi_dev;
95 break;
96
97 case DB_78X60_PCAC_ID:
98 case FPGA_88F78XX0_ID:
99 case DB_78X60_PCAC_REV2_ID:
100 case RD_78460_SERVER_REV2_ID:
101 default:
102 return 0;
103 }
104
105 /* Read MPP module ID */
106 ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
107 if (ret)
108 return MV_ERROR;
109
110 return data;
111 }
112
113 static int board_modules_scan(void)
114 {
115 u8 val;
116 u32 board_id = board_id_get();
117 int ret;
118
119 /* Perform scan only for DB board */
120 if ((board_id == DB_88F78XX0_BP_ID) ||
121 (board_id == DB_88F78XX0_BP_REV2_ID)) {
122 /* reset modules flags */
123 config_module = 0;
124
125 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
126
127 /* SERDES module (only PEX model is supported now) */
128 ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
129 if (ret)
130 return MV_ERROR;
131
132 if (val == MV_BOARD_PEX_MODULE_ID)
133 config_module = PEX_MODULE_DETECT;
134 if (val == MV_BOARD_ETM_MODULE_ID)
135 config_module = ETM_MODULE_DETECT;
136 } else if (board_id == RD_78460_NAS_ID) {
137 switch_module = 0;
138 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
139 switch_module = 1;
140 }
141
142 return MV_OK;
143 }
144
145 u32 pex_max_unit_get(void)
146 {
147 /*
148 * TODO:
149 * Right now only MV78460 is supported. Other SoC's might need
150 * a different value here.
151 */
152 return MV_PEX_MAX_UNIT;
153 }
154
155 u32 pex_max_if_get(void)
156 {
157 /*
158 * TODO:
159 * Right now only MV78460 is supported. Other SoC's might need
160 * a different value here.
161 */
162 return MV_PEX_MAX_IF;
163 }
164
165 u8 board_cpu_freq_get(void)
166 {
167 u32 sar;
168 u32 sar_msb;
169
170 sar = reg_read(MPP_SAMPLE_AT_RESET(0));
171 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
172 return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
173 }
174
175 __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
176 {
177 u32 board_id;
178 u32 serdes_cfg_val = 0; /* default */
179
180 board_id = board_id_get();
181
182 switch (board_id) {
183 case DB_784MP_GP_ID:
184 serdes_cfg_val = 0;
185 break;
186 }
187
188 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
189 }
190
191 u16 ctrl_model_get(void)
192 {
193 /* Right now only MV78460 supported */
194 return MV_78460_DEV_ID;
195 }
196
197 u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
198 {
199 if (line_num < 8)
200 return (info->line0_7 >> (line_num << 2)) & 0xF;
201 else
202 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
203 }
204
205 int serdes_phy_config(void)
206 {
207 int status = MV_OK;
208 u32 line_cfg;
209 u8 line_num;
210 /* addr/value for each line @ every setup step */
211 u32 addr[16][11], val[16][11];
212 u8 pex_unit, pex_line_num;
213 u8 sgmii_port = 0;
214 u32 tmp;
215 u32 in_direct;
216 u8 max_serdes_lines;
217 MV_BIN_SERDES_CFG *info;
218 u8 satr11;
219 u8 sata_port;
220 u8 freq;
221 u8 device_rev;
222 u32 rx_high_imp_mode;
223 u16 ctrl_mode;
224 u32 board_id = board_id_get();
225 u32 pex_if;
226 u32 pex_if_num;
227
228 /*
229 * TODO:
230 * Right now we only support the MV78460 with 16 serdes lines
231 */
232 max_serdes_lines = 16;
233 if (max_serdes_lines == 0)
234 return MV_OK;
235
236 switch (board_id) {
237 case DB_78X60_AMC_ID:
238 case DB_78X60_PCAC_REV2_ID:
239 case RD_78460_CUSTOMER_ID:
240 case RD_78460_SERVER_ID:
241 case RD_78460_SERVER_REV2_ID:
242 case DB_78X60_PCAC_ID:
243 satr11 = (0x1 << 1) | 1;
244 break;
245 case FPGA_88F78XX0_ID:
246 case RD_78460_NAS_ID:
247 satr11 = (0x0 << 1) | 1;
248 break;
249 case DB_88F78XX0_BP_REV2_ID:
250 case DB_784MP_GP_ID:
251 case DB_88F78XX0_BP_ID:
252 satr11 = board_sat_r_get(1, 1);
253 if ((u8) MV_ERROR == (u8) satr11)
254 return MV_ERROR;
255 break;
256 }
257
258 board_modules_scan();
259 memset(addr, 0, sizeof(addr));
260 memset(val, 0, sizeof(val));
261
262 /* Check if DRAM is already initialized */
263 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
264 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
265 DEBUG_INIT_S("High speed PHY - Version: ");
266 DEBUG_INIT_S(SERDES_VERION);
267 DEBUG_INIT_S(" - 2nd boot - Skip\n");
268 return MV_OK;
269 }
270 DEBUG_INIT_S("High speed PHY - Version: ");
271 DEBUG_INIT_S(SERDES_VERION);
272 DEBUG_INIT_S(" (COM-PHY-V20)\n");
273
274 /*
275 * AVS : disable AVS for frequency less than 1333
276 */
277 freq = board_cpu_freq_get();
278 device_rev = mv_ctrl_rev_get();
279
280 if (device_rev == 2) { /* for B0 only */
281 u32 cpu_avs;
282 u8 fabric_freq;
283 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
284 DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
285 cpu_avs &= ~(1 << 9);
286
287 if ((0x4 == freq) || (0xB == freq)) {
288 u32 tmp2;
289
290 tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
291 DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
292 /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
293 tmp2 |= 0x0FF;
294 reg_write(CPU_AVS_CONTROL0_REG, tmp2);
295 DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
296 cpu_avs |= (1 << 9); /* cpu avs enable */
297 cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
298 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
299 SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
300 if ((0xB == freq) && (5 == fabric_freq)) {
301 u32 core_avs;
302
303 core_avs = reg_read(CORE_AVS_CONTROL_0REG);
304 DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
305
306 /*
307 * Set core lower limit = 0.9V &
308 * core upper limit = 0.9125V
309 */
310 core_avs &= ~(0xff);
311 core_avs |= 0x0E;
312 reg_write(CORE_AVS_CONTROL_0REG, core_avs);
313 DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
314
315 core_avs = reg_read(CORE_AVS_CONTROL_2REG);
316 DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
317 core_avs |= (1 << 9); /* core AVS enable */
318 reg_write(CORE_AVS_CONTROL_2REG, core_avs);
319 DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
320
321 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
322 DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
323 tmp2);
324 tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
325 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
326 DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
327 tmp2);
328 }
329 }
330 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
331 DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
332 }
333
334 info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
335 DEBUG_INIT_FULL_S("info->line0_7= 0x");
336 DEBUG_INIT_FULL_D(info->line0_7, 8);
337 DEBUG_INIT_FULL_S(" info->line8_15= 0x");
338 DEBUG_INIT_FULL_D(info->line8_15, 8);
339 DEBUG_INIT_FULL_S("\n");
340
341 if (info == NULL) {
342 DEBUG_INIT_S("Hight speed PHY Error #1\n");
343 return MV_ERROR;
344 }
345
346 if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
347 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
348 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
349 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
350 info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
351 mdelay(100);
352 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
353 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
354 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
355 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
356 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
357 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
358 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
359 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
360 reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
361 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
362 reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
363 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
364 reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
365 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
366 reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
367 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
368 reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
369 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
370 reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
371 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
372 }
373
374 /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
375 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
376 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
377 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
378 continue;
379
380 /* 1. GLOB_CLK_CTRL Reset and Clock Control */
381 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
382 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
383
384 /* 2. GLOB_TEST_CTRL Test Mode Control */
385 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
386 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
387 (0xC2 << 16) | 0x200);
388 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
389 (0xC2 << 16) | 0x200);
390 }
391
392 /* 3. GLOB_CLK_SRC_LO Clock Source Low */
393 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
394 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
395 (0xC3 << 16) | 0x0F);
396 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
397 (0xC3 << 16) | 0x0F);
398 }
399
400 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
401 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
402 (0xC5 << 16) | 0x11F);
403 }
404
405 /*
406 * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
407 * PU_RX,PU_TX. (bits[12:5])
408 */
409 DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
410 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
411 line_cfg = get_line_cfg(line_num, info);
412 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
413 continue;
414 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
415 continue;
416 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
417 switch (line_num) {
418 case 4:
419 case 6:
420 sata_port = 0;
421 break;
422 case 5:
423 sata_port = 1;
424 break;
425 default:
426 DEBUG_INIT_C
427 ("SATA port error for serdes line: ",
428 line_num, 2);
429 return MV_ERROR;
430 }
431 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
432 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
433 tmp &= ~((0x1ff << 5) | 0x7);
434 tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
435 (0x11 << 5) : 0x0;
436
437 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
438 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
439 }
440
441 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
442 /*
443 * 4) Configure the desire PIN_PHY_GEN and do power
444 * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
445 */
446 tmp = reg_read(SGMII_SERDES_CFG_REG(0));
447 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
448 tmp &= ~((0x1ff << 5) | 0x7);
449 tmp |= 0x660;
450 reg_write(SGMII_SERDES_CFG_REG(0), tmp);
451 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
452 continue;
453 }
454
455 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
456 sgmii_port = 0;
457 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
458 sgmii_port = 1;
459 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
460 sgmii_port = 2;
461 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
462 sgmii_port = 3;
463 else
464 continue;
465
466 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
467 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
468 tmp &= ~((0x1ff << 5) | 0x7);
469 tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
470 (0x88 << 5) : (0x66 << 5));
471 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
472 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
473 }
474
475 /* Step 3 - QSGMII enable */
476 DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
477 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
478 line_cfg = get_line_cfg(line_num, info);
479 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
480 /* QSGMII Active bit set to true */
481 tmp = reg_read(QSGMII_CONTROL_1_REG);
482 DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
483 tmp |= (1 << 30);
484 #ifdef ERRATA_GL_6572255
485 tmp |= (1 << 27);
486 #endif
487 reg_write(QSGMII_CONTROL_1_REG, tmp);
488 DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
489 }
490 }
491
492 /* Step 4 - configure SERDES MUXes */
493 DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
494 if (config_module & ETM_MODULE_DETECT) {
495 reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
496 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
497 } else {
498 reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
499 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
500 }
501 reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
502 DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
503
504 /* Step 5: Activate the RX High Impedance Mode */
505 DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
506 rx_high_imp_mode = 0x8080;
507 if (device_rev == 2) /* for B0 only */
508 rx_high_imp_mode |= 4;
509
510 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
511 /* for each serdes lane */
512 DEBUG_INIT_FULL_S("SERDES ");
513 DEBUG_INIT_FULL_D_10(line_num, 2);
514 line_cfg = get_line_cfg(line_num, info);
515 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
516 DEBUG_INIT_FULL_S(" unconnected ***\n");
517 continue;
518 }
519 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
520 pex_unit = line_num >> 2;
521 pex_line_num = line_num % 4;
522 DEBUG_INIT_FULL_S(" - PEX unit ");
523 DEBUG_INIT_FULL_D_10(pex_unit, 1);
524 DEBUG_INIT_FULL_S(" line= ");
525 DEBUG_INIT_FULL_D_10(pex_line_num, 1);
526 DEBUG_INIT_FULL_S("\n");
527
528 /* Needed for PEX_PHY_ACCESS_REG macro */
529 if ((line_num > 7) &&
530 (info->pex_mode[3] == PEX_BUS_MODE_X8))
531 /* lines 8 - 15 are belong to PEX3 in x8 mode */
532 pex_unit = 3;
533
534 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
535 continue;
536
537 /*
538 * 8) Activate the RX High Impedance Mode field
539 * (bit [2]) in register /PCIe_USB Control (Each MAC
540 * contain different Access to reach its
541 * Serdes-Regfile).
542 * [PEX-Only] Set bit[12]: The analog part latches idle
543 * if PU_TX = 1 and PU_PLL =1.
544 */
545
546 /* Termination enable */
547 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
548 in_direct = (0x48 << 16) | (pex_line_num << 24) |
549 0x1000 | rx_high_imp_mode; /* x1 */
550 } else if ((info->pex_mode[pex_unit] ==
551 PEX_BUS_MODE_X4) && (pex_line_num == 0))
552 in_direct = (0x48 << 16) | (pex_line_num << 24) |
553 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
554 else
555 in_direct = 0;
556
557 if (in_direct) {
558 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
559 in_direct);
560 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
561 in_direct);
562 }
563
564 continue;
565 }
566
567 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
568 /*
569 * port 0 for serdes lines 4,6, and port 1 for
570 * serdes lines 5
571 */
572 sata_port = line_num & 1;
573 DEBUG_INIT_FULL_S(" - SATA port ");
574 DEBUG_INIT_FULL_D_10(sata_port, 2);
575 DEBUG_INIT_FULL_S("\n");
576 reg_write(SATA_COMPHY_CTRL_REG(sata_port),
577 rx_high_imp_mode);
578 DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
579 rx_high_imp_mode);
580 continue;
581 }
582
583 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
584 DEBUG_INIT_FULL_S(" - QSGMII\n");
585 reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
586 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
587 rx_high_imp_mode);
588 continue;
589 }
590
591 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
592 sgmii_port = 0;
593 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
594 sgmii_port = 1;
595 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
596 sgmii_port = 2;
597 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
598 sgmii_port = 3;
599 else
600 continue;
601 DEBUG_INIT_FULL_S(" - SGMII port ");
602 DEBUG_INIT_FULL_D_10(sgmii_port, 2);
603 DEBUG_INIT_FULL_S("\n");
604 reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
605 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
606 rx_high_imp_mode);
607 } /* for each serdes lane */
608
609 /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
610 DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
611 tmp = reg_read(SOC_CTRL_REG);
612 DEBUG_RD_REG(SOC_CTRL_REG, tmp);
613 tmp &= 0x200;
614 if (info->pex_mode[0] == PEX_BUS_MODE_X1)
615 tmp |= PCIE0_QUADX1_EN;
616 if (info->pex_mode[1] == PEX_BUS_MODE_X1)
617 tmp |= PCIE1_QUADX1_EN;
618 if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
619 PEX_CLK_100MHZ_OFFSET) == 0x1)
620 tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
621
622 reg_write(SOC_CTRL_REG, tmp);
623 DEBUG_WR_REG(SOC_CTRL_REG, tmp);
624
625 /* 6.2 PCI Express Link Capabilities */
626 DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
627
628 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
629 line_cfg = get_line_cfg(line_num, info);
630
631 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
632 /*
633 * PCI Express Control
634 * 0xX1A00 [0]:
635 * 0x0 X4-Link.
636 * 0x1 X1-Link
637 */
638 pex_unit = line_num >> 2;
639 pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
640 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
641 continue;
642
643 /* set Common Clock Configuration */
644 tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
645 DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
646 tmp |= (1 << 6);
647 reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
648 DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
649
650 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
651 DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
652 tmp &= ~(0x3FF);
653 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
654 tmp |= (0x1 << 4);
655 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
656 tmp |= (0x4 << 4);
657 if (0 == PEX_CAPABILITY_GET(satr11))
658 tmp |= 0x1;
659 else
660 tmp |= 0x2;
661 DEBUG_INIT_FULL_S("Step 6.2: PEX ");
662 DEBUG_INIT_FULL_D(pex_if, 1);
663 DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
664 reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
665 DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
666
667 /*
668 * If pex is X4, no need to pass thru the other
669 * 3X1 serdes lines
670 */
671 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
672 line_num += 3;
673 }
674 }
675
676 /*
677 * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
678 * need to config the register SOC_Misc/General Purpose2
679 * (Address= 182F8)
680 */
681 DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
682 tmp = reg_read(GEN_PURP_RES_2_REG);
683 DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
684
685 tmp &= 0xFFFF0000;
686 if (info->pex_mode[0] == PEX_BUS_MODE_X4)
687 tmp |= 0x0000000F;
688
689 if (info->pex_mode[1] == PEX_BUS_MODE_X4)
690 tmp |= 0x000000F0;
691
692 if (info->pex_mode[2] == PEX_BUS_MODE_X4)
693 tmp |= 0x00000F00;
694
695 if (info->pex_mode[3] == PEX_BUS_MODE_X4)
696 tmp |= 0x0000F000;
697
698 reg_write(GEN_PURP_RES_2_REG, tmp);
699 DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
700
701 /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
702 DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
703
704 /* Prepare PHY parameters for each step according to MUX selection */
705 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
706 /* for each serdes lane */
707
708 line_cfg = get_line_cfg(line_num, info);
709
710 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
711 continue;
712
713 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
714 pex_unit = line_num >> 2;
715 pex_line_num = line_num % 4;
716
717 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
718 continue;
719 /*
720 * 8) Configure the desire PHY_MODE (bits [7:5])
721 * and REF_FREF_SEL (bits[4:0]) in the register Power
722 * and PLL Control (Each MAC contain different Access
723 * to reach its Serdes-Regfile).
724 */
725 if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
726 (0 == pex_line_num))
727 || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
728 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
729 (0x01 << 16) | (pex_line_num << 24) |
730 0xFC60);
731 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
732 (0x01 << 16) | (pex_line_num << 24)
733 | 0xFC60);
734 /*
735 * Step 8.1: [PEX-Only] Configure Max PLL Rate
736 * (bit 8 in KVCO Calibration Control and
737 * bits[10:9] in
738 */
739 /* Use Maximum PLL Rate(Bit 8) */
740 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
741 (0x02 << 16) | (1 << 31) |
742 (pex_line_num << 24)); /* read command */
743 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
744 (0x02 << 16) | (1 << 31) |
745 (pex_line_num << 24));
746 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
747 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
748 tmp &= ~(1 << 31);
749 tmp |= (1 << 8);
750 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
751 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
752
753 /* Use Maximum PLL Rate(Bits [10:9]) */
754 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
755 (0x81 << 16) | (1 << 31) |
756 (pex_line_num << 24)); /* read command */
757 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
758 (0x81 << 16) | (1 << 31) |
759 (pex_line_num << 24));
760 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
761 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
762 tmp &= ~(1 << 31);
763 tmp |= (3 << 9);
764 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
765 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
766 }
767
768 continue;
769 }
770
771 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
772 /*
773 * Port 0 for serdes lines 4,6, and port 1 for serdes
774 * lines 5
775 */
776 sata_port = line_num & 1;
777
778 /*
779 * 8) Configure the desire PHY_MODE (bits [7:5]) and
780 * REF_FREF_SEL (bits[4:0]) in the register Power
781 * and PLL Control (Each MAC contain different Access
782 * to reach its Serdes-Regfile).
783 */
784 reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
785 DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
786
787 /* 9) Configure the desire SEL_BITS */
788 reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
789 DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
790
791 /* 10) Configure the desire REFCLK_SEL */
792
793 reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
794 DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
795
796 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
797 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
798 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
799 tmp |= 7;
800 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
801 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
802
803 continue;
804 }
805
806 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
807 /*
808 * 8) Configure the desire PHY_MODE (bits [7:5])
809 * and REF_FREF_SEL (bits[4:0]) in the register
810 */
811 reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
812 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
813
814 /*
815 * 9) Configure the desire SEL_BITS (bits [11:0]
816 * in register
817 */
818 reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
819 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
820
821 /*
822 * 10) Configure the desire REFCLK_SEL (bit [10])
823 * in register
824 */
825 reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
826 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
827
828 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
829 tmp = reg_read(SGMII_SERDES_CFG_REG(0));
830 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
831 tmp |= 7;
832 reg_write(SGMII_SERDES_CFG_REG(0), tmp);
833 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
834 continue;
835 }
836
837 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
838 sgmii_port = 0;
839 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
840 sgmii_port = 1;
841 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
842 sgmii_port = 2;
843 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
844 sgmii_port = 3;
845 else
846 continue;
847
848 /*
849 * 8) Configure the desire PHY_MODE (bits [7:5]) and
850 * REF_FREF_SEL (bits[4:0]) in the register
851 */
852 reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
853 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
854
855 /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
856 reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
857 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
858
859 /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
860 reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
861 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
862
863 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
864 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
865 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
866 tmp |= 7;
867 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
868 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
869
870 } /* for each serdes lane */
871
872 /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
873 DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
874 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
875 /* for each serdes lane */
876
877 line_cfg = get_line_cfg(line_num, info);
878
879 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
880 continue;
881
882 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
883 pex_unit = line_num >> 2;
884 pex_line_num = line_num % 4;
885 if (0 == pex_line_num) {
886 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
887 (0xC1 << 16) | 0x24);
888 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
889 (0xC1 << 16) | 0x24);
890 }
891 }
892 }
893
894 /*--------------------------------------------------------------*/
895 /* Step 13: Wait 15ms before checking results */
896 DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
897 mdelay(15);
898 tmp = 20;
899 while (tmp) {
900 status = MV_OK;
901 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
902 u32 tmp;
903 line_cfg = get_line_cfg(line_num, info);
904 if (line_cfg ==
905 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
906 continue;
907
908 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
909 continue;
910
911 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
912 /*
913 * Port 0 for serdes lines 4,6, and port 1
914 * for serdes lines 5
915 */
916 sata_port = line_num & 1;
917
918 tmp =
919 reg_read(SATA_LP_PHY_EXT_STAT_REG
920 (sata_port));
921 DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
922 (sata_port), tmp);
923 if ((tmp & 0x7) != 0x7)
924 status = MV_ERROR;
925 continue;
926 }
927
928 if (line_cfg ==
929 serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
930 tmp = reg_read(SGMII_SERDES_STAT_REG(0));
931 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
932 if ((tmp & 0x7) != 0x7)
933 status = MV_ERROR;
934 continue;
935 }
936
937 if (line_cfg ==
938 serdes_cfg[line_num][SERDES_UNIT_SGMII0])
939 sgmii_port = 0;
940 else if (line_cfg ==
941 serdes_cfg[line_num][SERDES_UNIT_SGMII1])
942 sgmii_port = 1;
943 else if (line_cfg ==
944 serdes_cfg[line_num][SERDES_UNIT_SGMII2])
945 sgmii_port = 2;
946 else if (line_cfg ==
947 serdes_cfg[line_num][SERDES_UNIT_SGMII3])
948 sgmii_port = 3;
949 else
950 continue;
951
952 tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
953 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
954 if ((tmp & 0x7) != 0x7)
955 status = MV_ERROR;
956 }
957
958 if (status == MV_OK)
959 break;
960 mdelay(5);
961 tmp--;
962 }
963
964 /*
965 * Step14 [PEX-Only] In order to configure RC/EP mode please write
966 * to register 0x0060 bits
967 */
968 DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
969 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
970 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
971 continue;
972 tmp =
973 reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
974 DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
975 tmp);
976 tmp &= ~(0xf << 20);
977 if (info->pex_type == MV_PEX_ROOT_COMPLEX)
978 tmp |= (0x4 << 20);
979 else
980 tmp |= (0x1 << 20);
981 reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
982 tmp);
983 DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
984 tmp);
985 }
986
987 /*
988 * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
989 * register 0x1a60
990 */
991 DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
992 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
993 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
994 continue;
995 if (info->pex_type == MV_PEX_END_POINT) {
996 tmp =
997 reg_read(PEX_DBG_CTRL_REG
998 (MV_PEX_UNIT_TO_IF(pex_unit)));
999 DEBUG_RD_REG(PEX_DBG_CTRL_REG
1000 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1001 tmp &= 0xfff6ffff;
1002 reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1003 tmp);
1004 DEBUG_WR_REG(PEX_DBG_CTRL_REG
1005 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1006 }
1007 }
1008
1009 if (info->serdes_m_phy_change) {
1010 MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
1011 u32 bus_speed;
1012 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
1013 line_cfg = get_line_cfg(line_num, info);
1014 if (line_cfg ==
1015 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
1016 continue;
1017 serdes_m_phy_change = info->serdes_m_phy_change;
1018 bus_speed = info->bus_speed & (1 << line_num);
1019 while (serdes_m_phy_change->type !=
1020 SERDES_UNIT_UNCONNECTED) {
1021 switch (serdes_m_phy_change->type) {
1022 case SERDES_UNIT_PEX:
1023 if (line_cfg != SERDES_UNIT_PEX)
1024 break;
1025 pex_unit = line_num >> 2;
1026 pex_line_num = line_num % 4;
1027 if (info->pex_mode[pex_unit] ==
1028 PEX_BUS_DISABLED)
1029 break;
1030 if ((info->pex_mode[pex_unit] ==
1031 PEX_BUS_MODE_X4) && pex_line_num)
1032 break;
1033
1034 if (bus_speed) {
1035 reg_write(PEX_PHY_ACCESS_REG
1036 (pex_unit),
1037 (pex_line_num << 24) |
1038 serdes_m_phy_change->val_hi_speed);
1039 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1040 (pex_unit),
1041 (pex_line_num <<
1042 24) |
1043 serdes_m_phy_change->val_hi_speed);
1044 } else {
1045 reg_write(PEX_PHY_ACCESS_REG
1046 (pex_unit),
1047 (pex_line_num << 24) |
1048 serdes_m_phy_change->val_low_speed);
1049 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1050 (pex_unit),
1051 (pex_line_num <<
1052 24) |
1053 serdes_m_phy_change->val_low_speed);
1054 }
1055 break;
1056 case SERDES_UNIT_SATA:
1057 if (line_cfg != SERDES_UNIT_SATA)
1058 break;
1059 /*
1060 * Port 0 for serdes lines 4,6, and
1061 * port 1 for serdes lines 5
1062 */
1063 sata_port = line_num & 1;
1064 if (bus_speed) {
1065 reg_write(SATA_BASE_REG
1066 (sata_port) |
1067 serdes_m_phy_change->reg_hi_speed,
1068 serdes_m_phy_change->val_hi_speed);
1069 DEBUG_WR_REG(SATA_BASE_REG
1070 (sata_port) |
1071 serdes_m_phy_change->reg_hi_speed,
1072 serdes_m_phy_change->val_hi_speed);
1073 } else {
1074 reg_write(SATA_BASE_REG
1075 (sata_port) |
1076 serdes_m_phy_change->reg_low_speed,
1077 serdes_m_phy_change->val_low_speed);
1078 DEBUG_WR_REG(SATA_BASE_REG
1079 (sata_port) |
1080 serdes_m_phy_change->reg_low_speed,
1081 serdes_m_phy_change->val_low_speed);
1082 }
1083 break;
1084 case SERDES_UNIT_SGMII0:
1085 case SERDES_UNIT_SGMII1:
1086 case SERDES_UNIT_SGMII2:
1087 case SERDES_UNIT_SGMII3:
1088 if (line_cfg == serdes_cfg[line_num]
1089 [SERDES_UNIT_SGMII0])
1090 sgmii_port = 0;
1091 else if (line_cfg ==
1092 serdes_cfg[line_num]
1093 [SERDES_UNIT_SGMII1])
1094 sgmii_port = 1;
1095 else if (line_cfg ==
1096 serdes_cfg[line_num]
1097 [SERDES_UNIT_SGMII2])
1098 sgmii_port = 2;
1099 else if (line_cfg ==
1100 serdes_cfg[line_num]
1101 [SERDES_UNIT_SGMII3])
1102 sgmii_port = 3;
1103 else
1104 break;
1105 if (bus_speed) {
1106 reg_write(MV_ETH_REGS_BASE
1107 (sgmii_port) |
1108 serdes_m_phy_change->reg_hi_speed,
1109 serdes_m_phy_change->val_hi_speed);
1110 DEBUG_WR_REG(MV_ETH_REGS_BASE
1111 (sgmii_port) |
1112 serdes_m_phy_change->reg_hi_speed,
1113 serdes_m_phy_change->val_hi_speed);
1114 } else {
1115 reg_write(MV_ETH_REGS_BASE
1116 (sgmii_port) |
1117 serdes_m_phy_change->reg_low_speed,
1118 serdes_m_phy_change->val_low_speed);
1119 DEBUG_WR_REG(MV_ETH_REGS_BASE
1120 (sgmii_port) |
1121 serdes_m_phy_change->reg_low_speed,
1122 serdes_m_phy_change->val_low_speed);
1123 }
1124 break;
1125 case SERDES_UNIT_QSGMII:
1126 if (line_cfg != SERDES_UNIT_QSGMII)
1127 break;
1128 if (bus_speed) {
1129 reg_write
1130 (serdes_m_phy_change->reg_hi_speed,
1131 serdes_m_phy_change->val_hi_speed);
1132 DEBUG_WR_REG
1133 (serdes_m_phy_change->reg_hi_speed,
1134 serdes_m_phy_change->val_hi_speed);
1135 } else {
1136 reg_write
1137 (serdes_m_phy_change->reg_low_speed,
1138 serdes_m_phy_change->val_low_speed);
1139 DEBUG_WR_REG
1140 (serdes_m_phy_change->reg_low_speed,
1141 serdes_m_phy_change->val_low_speed);
1142 }
1143 break;
1144 default:
1145 break;
1146 }
1147 serdes_m_phy_change++;
1148 }
1149 }
1150 }
1151
1152 /* Step 16 [PEX-Only] Training Enable */
1153 DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
1154 tmp = reg_read(SOC_CTRL_REG);
1155 DEBUG_RD_REG(SOC_CTRL_REG, tmp);
1156 tmp &= ~(0x0F);
1157 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1158 reg_write(PEX_CAUSE_REG(pex_unit), 0);
1159 DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
1160 if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
1161 tmp |= (0x1 << pex_unit);
1162 }
1163 reg_write(SOC_CTRL_REG, tmp);
1164 DEBUG_WR_REG(SOC_CTRL_REG, tmp);
1165
1166 /* Step 17: Speed change to target speed and width */
1167 {
1168 u32 tmp_reg, tmp_pex_reg;
1169 u32 addr;
1170 u32 first_busno, next_busno;
1171 u32 max_link_width = 0;
1172 u32 neg_link_width = 0;
1173 pex_if_num = pex_max_if_get();
1174 mdelay(150);
1175 DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
1176 next_busno = 0;
1177 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1178 line_num = (pex_if <= 8) ? pex_if : 12;
1179 line_cfg = get_line_cfg(line_num, info);
1180 if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
1181 continue;
1182 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1183 DEBUG_INIT_FULL_S("step 17: PEX");
1184 DEBUG_INIT_FULL_D(pex_if, 1);
1185 DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
1186
1187 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1188 DEBUG_INIT_FULL_C("PEX disabled interface ",
1189 pex_if, 1);
1190 if (pex_if < 8)
1191 pex_if += 3;
1192 continue;
1193 }
1194 first_busno = next_busno;
1195 if ((info->pex_type == MV_PEX_END_POINT) &&
1196 (0 == pex_if)) {
1197 if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
1198 PEX_BUS_MODE_X4))
1199 pex_if += 3;
1200 continue;
1201 }
1202
1203 tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
1204 DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
1205 if ((tmp & 0x7f) == 0x7e) {
1206 next_busno++;
1207 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
1208 max_link_width = tmp;
1209 DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
1210 (pex_if)), tmp);
1211 max_link_width = ((max_link_width >> 4) & 0x3F);
1212 neg_link_width =
1213 reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
1214 DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
1215 neg_link_width);
1216 neg_link_width = ((neg_link_width >> 20) & 0x3F);
1217 if (max_link_width > neg_link_width) {
1218 tmp &= ~(0x3F << 4);
1219 tmp |= (neg_link_width << 4);
1220 reg_write(PEX_LINK_CAPABILITIES_REG
1221 (pex_if), tmp);
1222 DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
1223 (pex_if)), tmp);
1224 mdelay(1); /* wait 1ms before reading capability for speed */
1225 DEBUG_INIT_S("PEX");
1226 DEBUG_INIT_D(pex_if, 1);
1227 DEBUG_INIT_C(": change width to X",
1228 neg_link_width, 1);
1229 }
1230 tmp_pex_reg =
1231 reg_read((PEX_CFG_DIRECT_ACCESS
1232 (pex_if,
1233 PEX_LINK_CAPABILITY_REG)));
1234 DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
1235 (pex_if,
1236 PEX_LINK_CAPABILITY_REG)),
1237 tmp_pex_reg);
1238 tmp_pex_reg &= (0xF);
1239 if (tmp_pex_reg == 0x2) {
1240 tmp_reg =
1241 (reg_read
1242 (PEX_CFG_DIRECT_ACCESS
1243 (pex_if,
1244 PEX_LINK_CTRL_STAT_REG)) &
1245 0xF0000) >> 16;
1246 DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
1247 (pex_if,
1248 PEX_LINK_CTRL_STAT_REG),
1249 tmp_pex_reg);
1250 /* check if the link established is GEN1 */
1251 if (tmp_reg == 0x1) {
1252 pex_local_bus_num_set(pex_if,
1253 first_busno);
1254 pex_local_dev_num_set(pex_if,
1255 1);
1256
1257 DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
1258 /* link is Gen1, check the EP capability */
1259 addr =
1260 pex_cfg_read(pex_if,
1261 first_busno, 0,
1262 0,
1263 0x34) & 0xFF;
1264 DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
1265 addr, 4);
1266 if (addr == 0xff) {
1267 DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
1268 pex_if, 1);
1269 continue;
1270 }
1271 while ((pex_cfg_read
1272 (pex_if, first_busno, 0,
1273 0,
1274 addr) & 0xFF) !=
1275 0x10) {
1276 addr =
1277 (pex_cfg_read
1278 (pex_if,
1279 first_busno, 0, 0,
1280 addr) & 0xFF00) >>
1281 8;
1282 }
1283 if ((pex_cfg_read
1284 (pex_if, first_busno, 0, 0,
1285 addr + 0xC) & 0xF) >=
1286 0x2) {
1287 tmp =
1288 reg_read
1289 (PEX_LINK_CTRL_STATUS2_REG
1290 (pex_if));
1291 DEBUG_RD_REG
1292 (PEX_LINK_CTRL_STATUS2_REG
1293 (pex_if), tmp);
1294 tmp &= ~(0x1 | 1 << 1);
1295 tmp |= (1 << 1);
1296 reg_write
1297 (PEX_LINK_CTRL_STATUS2_REG
1298 (pex_if), tmp);
1299 DEBUG_WR_REG
1300 (PEX_LINK_CTRL_STATUS2_REG
1301 (pex_if), tmp);
1302
1303 tmp =
1304 reg_read
1305 (PEX_CTRL_REG
1306 (pex_if));
1307 DEBUG_RD_REG
1308 (PEX_CTRL_REG
1309 (pex_if), tmp);
1310 tmp |= (1 << 10);
1311 reg_write(PEX_CTRL_REG
1312 (pex_if),
1313 tmp);
1314 DEBUG_WR_REG
1315 (PEX_CTRL_REG
1316 (pex_if), tmp);
1317 mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
1318 DEBUG_INIT_FULL_S
1319 ("Gen2 client!\n");
1320 } else {
1321 DEBUG_INIT_FULL_S
1322 ("GEN1 client!\n");
1323 }
1324 }
1325 }
1326 } else {
1327 DEBUG_INIT_FULL_S("PEX");
1328 DEBUG_INIT_FULL_D(pex_if, 1);
1329 DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
1330 DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
1331 8);
1332 DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
1333 }
1334
1335 if ((pex_if < 8) &&
1336 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1337 pex_if += 3;
1338 }
1339 }
1340
1341 /* Step 18: update pex DEVICE ID */
1342 {
1343 u32 devId;
1344 pex_if_num = pex_max_if_get();
1345 ctrl_mode = ctrl_model_get();
1346 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1347 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1348 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1349 if ((pex_if < 8) &&
1350 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1351 pex_if += 3;
1352 continue;
1353 }
1354
1355 devId = reg_read(PEX_CFG_DIRECT_ACCESS(
1356 pex_if, PEX_DEVICE_AND_VENDOR_ID));
1357 devId &= 0xFFFF;
1358 devId |= ((ctrl_mode << 16) & 0xffff0000);
1359 DEBUG_INIT_S("Update Device ID PEX");
1360 DEBUG_INIT_D(pex_if, 1);
1361 DEBUG_INIT_D(devId, 8);
1362 DEBUG_INIT_S("\n");
1363 reg_write(PEX_CFG_DIRECT_ACCESS
1364 (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
1365 if ((pex_if < 8) &&
1366 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1367 pex_if += 3;
1368 }
1369 DEBUG_INIT_S("Update PEX Device ID 0x");
1370 DEBUG_INIT_D(ctrl_mode, 4);
1371 DEBUG_INIT_S("0\n");
1372 }
1373 tmp = reg_read(PEX_DBG_STATUS_REG(0));
1374 DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
1375
1376 DEBUG_INIT_S(ENDED_OK);
1377 return MV_OK;
1378 }
1379
1380 /* PEX configuration space read write */
1381
1382 /*
1383 * pex_cfg_read - Read from configuration space
1384 *
1385 * DESCRIPTION:
1386 * This function performs a 32 bit read from PEX configuration space.
1387 * It supports both type 0 and type 1 of Configuration Transactions
1388 * (local and over bridge). In order to read from local bus segment, use
1389 * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
1390 * will result configuration transaction of type 1 (over bridge).
1391 *
1392 * INPUT:
1393 * pex_if - PEX interface number.
1394 * bus - PEX segment bus number.
1395 * dev - PEX device number.
1396 * func - Function number.
1397 * offss - Register offset.
1398 *
1399 * OUTPUT:
1400 * None.
1401 *
1402 * RETURN:
1403 * 32bit register data, 0xffffffff on error
1404 *
1405 */
1406 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
1407 {
1408 u32 pex_data = 0;
1409 u32 local_dev, local_bus;
1410 u32 val;
1411
1412 if (pex_if >= MV_PEX_MAX_IF)
1413 return 0xFFFFFFFF;
1414
1415 if (dev >= MAX_PEX_DEVICES) {
1416 DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
1417 1);
1418 return 0xFFFFFFFF;
1419 }
1420
1421 if (func >= MAX_PEX_FUNCS) {
1422 DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
1423 1);
1424 return 0xFFFFFFFF;
1425 }
1426
1427 if (bus >= MAX_PEX_BUSSES) {
1428 DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
1429 return MV_ERROR;
1430 }
1431 val = reg_read(PEX_STATUS_REG(pex_if));
1432
1433 local_dev =
1434 ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
1435 local_bus =
1436 ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
1437
1438 /* Speed up the process. In case on no link, return MV_ERROR */
1439 if ((dev != local_dev) || (bus != local_bus)) {
1440 pex_data = reg_read(PEX_STATUS_REG(pex_if));
1441
1442 if ((pex_data & PXSR_DL_DOWN))
1443 return MV_ERROR;
1444 }
1445
1446 /*
1447 * In PCI Express we have only one device number
1448 * and this number is the first number we encounter else that the
1449 * local_dev spec pex define return on config read/write on any device
1450 */
1451 if (bus == local_bus) {
1452 if (local_dev == 0) {
1453 /*
1454 * If local dev is 0 then the first number we encounter
1455 * after 0 is 1
1456 */
1457 if ((dev != 1) && (dev != local_dev))
1458 return MV_ERROR;
1459 } else {
1460 /*
1461 * If local dev is not 0 then the first number we
1462 * encounter is 0
1463 */
1464 if ((dev != 0) && (dev != local_dev))
1465 return MV_ERROR;
1466 }
1467 }
1468
1469 /* Creating PEX address to be passed */
1470 pex_data = (bus << PXCAR_BUS_NUM_OFFS);
1471 pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
1472 pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
1473 pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
1474 /* extended register space */
1475 pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
1476 PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
1477
1478 pex_data |= PXCAR_CONFIG_EN;
1479
1480 /* Write the address to the PEX configuration address register */
1481 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
1482
1483 /*
1484 * In order to let the PEX controller absorbed the address of the read
1485 * transaction we perform a validity check that the address was written
1486 */
1487 if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
1488 return MV_ERROR;
1489
1490 /* cleaning Master Abort */
1491 reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
1492 PXSAC_MABORT);
1493 /* Read the Data returned in the PEX Data register */
1494 pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
1495
1496 DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
1497
1498 return pex_data;
1499 }
1500
1501 /*
1502 * pex_local_bus_num_set - Set PEX interface local bus number.
1503 *
1504 * DESCRIPTION:
1505 * This function sets given PEX interface its local bus number.
1506 * Note: In case the PEX interface is PEX-X, the information is read-only.
1507 *
1508 * INPUT:
1509 * pex_if - PEX interface number.
1510 * bus_num - Bus number.
1511 *
1512 * OUTPUT:
1513 * None.
1514 *
1515 * RETURN:
1516 * MV_NOT_ALLOWED in case PEX interface is PEX-X.
1517 * MV_BAD_PARAM on bad parameters ,
1518 * otherwise MV_OK
1519 *
1520 */
1521 int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
1522 {
1523 u32 val;
1524
1525 if (bus_num >= MAX_PEX_BUSSES) {
1526 DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
1527 bus_num, 4);
1528 return MV_ERROR;
1529 }
1530
1531 val = reg_read(PEX_STATUS_REG(pex_if));
1532 val &= ~PXSR_PEX_BUS_NUM_MASK;
1533 val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
1534 reg_write(PEX_STATUS_REG(pex_if), val);
1535
1536 return MV_OK;
1537 }
1538
1539 /*
1540 * pex_local_dev_num_set - Set PEX interface local device number.
1541 *
1542 * DESCRIPTION:
1543 * This function sets given PEX interface its local device number.
1544 * Note: In case the PEX interface is PEX-X, the information is read-only.
1545 *
1546 * INPUT:
1547 * pex_if - PEX interface number.
1548 * dev_num - Device number.
1549 *
1550 * OUTPUT:
1551 * None.
1552 *
1553 * RETURN:
1554 * MV_NOT_ALLOWED in case PEX interface is PEX-X.
1555 * MV_BAD_PARAM on bad parameters ,
1556 * otherwise MV_OK
1557 *
1558 */
1559 int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
1560 {
1561 u32 val;
1562
1563 if (pex_if >= MV_PEX_MAX_IF)
1564 return MV_BAD_PARAM;
1565
1566 val = reg_read(PEX_STATUS_REG(pex_if));
1567 val &= ~PXSR_PEX_DEV_NUM_MASK;
1568 val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
1569 reg_write(PEX_STATUS_REG(pex_if), val);
1570
1571 return MV_OK;
1572 }
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