arch/arm/mach-mvebu/timer.c

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/soc.h>
  11
  12 #define UBOOT_CNTR      0       /* counter to use for U-Boot timer */
  13
  14 /*
  15  * ARM Timers Registers Map
  16  */
  17 #define CNTMR_CTRL_REG                  &tmr_regs->ctrl
  18 #define CNTMR_RELOAD_REG(tmrnum)        &tmr_regs->tmr[tmrnum].reload
  19 #define CNTMR_VAL_REG(tmrnum)           &tmr_regs->tmr[tmrnum].val
  20
  21 /*
  22  * ARM Timers Control Register
  23  * CPU_TIMERS_CTRL_REG (CTCR)
  24  */
  25 #define CTCR_ARM_TIMER_EN_OFFS(cntr)    (cntr * 2)
  26 #define CTCR_ARM_TIMER_EN(cntr)         (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  27
  28 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr)  ((cntr * 2) + 1)
  29 #define CTCR_ARM_TIMER_AUTO_EN(cntr)    (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  30
  31 /* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
  32 #if defined(CONFIG_ARMADA_XP)
  33 #define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
  34 #define CTCR_ARM_TIMER_25MHZ(cntr)      (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
  35 #else
  36 #define CTCR_ARM_TIMER_25MHZ(cntr)      0
  37 #endif
  38
  39 #define TIMER_LOAD_VAL                  0xffffffff
  40
  41 #define timestamp                       gd->arch.tbl
  42 #define lastdec                         gd->arch.lastinc
  43
  44 /* Timer reload and current value registers */
  45 struct kwtmr_val {
  46         u32 reload;     /* Timer reload reg */
  47         u32 val;        /* Timer value reg */
  48 };
  49
  50 /* Timer registers */
  51 struct kwtmr_registers {
  52         u32 ctrl;       /* Timer control reg */
  53         u32 pad[3];
  54         struct kwtmr_val tmr[4];
  55         u32 wdt_reload;
  56         u32 wdt_val;
  57 };
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 static struct kwtmr_registers *tmr_regs =
  62         (struct kwtmr_registers *)MVEBU_TIMER_BASE;
  63
  64 static inline ulong read_timer(void)
  65 {
  66         return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
  67 }
  68
  69 ulong get_timer_masked(void)
  70 {
  71         ulong now = read_timer();
  72
  73         if (lastdec >= now) {
  74                 /* normal mode */
  75                 timestamp += lastdec - now;
  76         } else {
  77                 /* we have an overflow ... */
  78                 timestamp += lastdec +
  79                         (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
  80         }
  81         lastdec = now;
  82
  83         return timestamp;
  84 }
  85
  86 ulong get_timer(ulong base)
  87 {
  88         return get_timer_masked() - base;
  89 }
  90
  91 void __udelay(unsigned long usec)
  92 {
  93         uint current;
  94         ulong delayticks;
  95
  96         current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
  97         delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
  98
  99         if (current < delayticks) {
 100                 delayticks -= current;
 101                 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
 102                 while ((TIMER_LOAD_VAL - delayticks) <
 103                         readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
 104         } else {
 105                 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
 106                         (current - delayticks)) ;
 107         }
 108 }
 109
 110 /*
 111  * init the counter
 112  */
 113 int timer_init(void)
 114 {
 115         /* load value into timer */
 116         writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
 117         writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
 118
 119         /* enable timer in auto reload mode */
 120         clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
 121                         CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
 122                         CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
 123
 124         /* init the timestamp and lastdec value */
 125         lastdec = read_timer();
 126         timestamp = 0;
 127
 128         return 0;
 129 }
 130
 131 /*
 132  * This function is derived from PowerPC code (read timebase as long long).
 133  * On ARM it just returns the timer value.
 134  */
 135 unsigned long long get_ticks(void)
 136 {
 137         return get_timer(0);
 138 }
 139
 140 /*
 141  * This function is derived from PowerPC code (timebase clock frequency).
 142  * On ARM it returns the number of timer ticks per second.
 143  */
 144 ulong get_tbclk (void)
 145 {
 146         return (ulong)CONFIG_SYS_HZ;
 147 }