arch/arm/mach-omap2/am33xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Common board functions for AM33XX based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <debug_uart.h>
  13 #include <errno.h>
  14 #include <event.h>
  15 #include <init.h>
  16 #include <net.h>
  17 #include <ns16550.h>
  18 #include <omap3_spi.h>
  19 #include <spl.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/i2c.h>
  27 #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
  28 #include <asm/arch/mem-guardian.h>
  29 #else
  30 #include <asm/arch/mem.h>
  31 #endif
  32 #include <asm/arch/mmc_host_def.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/global_data.h>
  35 #include <asm/io.h>
  36 #include <asm/emif.h>
  37 #include <asm/gpio.h>
  38 #include <asm/omap_common.h>
  39 #include <i2c.h>
  40 #include <miiphy.h>
  41 #include <cpsw.h>
  42 #include <linux/delay.h>
  43 #include <linux/errno.h>
  44 #include <linux/compiler.h>
  45 #include <linux/usb/ch9.h>
  46 #include <linux/usb/gadget.h>
  47 #include <linux/usb/musb.h>
  48 #include <asm/omap_musb.h>
  49 #include <asm/davinci_rtc.h>
  50
  51 #define AM43XX_EMIF_BASE                                0x4C000000
  52 #define AM43XX_SDRAM_CONFIG_OFFSET                      0x8
  53 #define AM43XX_SDRAM_TYPE_MASK                          0xE0000000
  54 #define AM43XX_SDRAM_TYPE_SHIFT                         29
  55 #define AM43XX_SDRAM_TYPE_DDR3                          3
  56 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET          0xDC
  57 #define AM43XX_RDWRLVLFULL_START                        0x80000000
  58
  59 /* SPI flash. */
  60 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
  61 #define AM33XX_SPI0_BASE        0x48030000
  62 #define AM33XX_SPI0_OFFSET      (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 int dram_init(void)
  68 {
  69 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
  70         sdram_init();
  71 #endif
  72
  73         /* dram_init must store complete ramsize in gd->ram_size */
  74         gd->ram_size = get_ram_size(
  75                         (void *)CFG_SYS_SDRAM_BASE,
  76                         CFG_MAX_RAM_BANK_SIZE);
  77         return 0;
  78 }
  79
  80 int dram_init_banksize(void)
  81 {
  82         gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
  83         gd->bd->bi_dram[0].size = gd->ram_size;
  84
  85         return 0;
  86 }
  87
  88 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  89 static const struct ns16550_plat am33xx_serial[] = {
  90         { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
  91           .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  92 # ifdef CFG_SYS_NS16550_COM2
  93         { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
  94           .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  95 #  ifdef CFG_SYS_NS16550_COM3
  96         { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
  97           .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  98         { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
  99           .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 100         { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
 101           .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 102         { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
 103           .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 104 #  endif
 105 # endif
 106 };
 107
 108 U_BOOT_DRVINFOS(am33xx_uarts) = {
 109         { "ns16550_serial", &am33xx_serial[0] },
 110 #  ifdef CFG_SYS_NS16550_COM2
 111         { "ns16550_serial", &am33xx_serial[1] },
 112 #   ifdef CFG_SYS_NS16550_COM3
 113         { "ns16550_serial", &am33xx_serial[2] },
 114         { "ns16550_serial", &am33xx_serial[3] },
 115         { "ns16550_serial", &am33xx_serial[4] },
 116         { "ns16550_serial", &am33xx_serial[5] },
 117 #   endif
 118 #  endif
 119 };
 120
 121 #if CONFIG_IS_ENABLED(DM_I2C)
 122 static const struct omap_i2c_plat am33xx_i2c[] = {
 123         { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
 124         { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
 125         { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
 126 };
 127
 128 U_BOOT_DRVINFOS(am33xx_i2c) = {
 129         { "i2c_omap", &am33xx_i2c[0] },
 130         { "i2c_omap", &am33xx_i2c[1] },
 131         { "i2c_omap", &am33xx_i2c[2] },
 132 };
 133 #endif
 134
 135 #if CONFIG_IS_ENABLED(DM_GPIO)
 136 static const struct omap_gpio_plat am33xx_gpio[] = {
 137         { 0, AM33XX_GPIO0_BASE },
 138         { 1, AM33XX_GPIO1_BASE },
 139         { 2, AM33XX_GPIO2_BASE },
 140         { 3, AM33XX_GPIO3_BASE },
 141 #ifdef CONFIG_AM43XX
 142         { 4, AM33XX_GPIO4_BASE },
 143         { 5, AM33XX_GPIO5_BASE },
 144 #endif
 145 };
 146
 147 U_BOOT_DRVINFOS(am33xx_gpios) = {
 148         { "gpio_omap", &am33xx_gpio[0] },
 149         { "gpio_omap", &am33xx_gpio[1] },
 150         { "gpio_omap", &am33xx_gpio[2] },
 151         { "gpio_omap", &am33xx_gpio[3] },
 152 #ifdef CONFIG_AM43XX
 153         { "gpio_omap", &am33xx_gpio[4] },
 154         { "gpio_omap", &am33xx_gpio[5] },
 155 #endif
 156 };
 157 #endif
 158 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
 159 static const struct omap3_spi_plat omap3_spi_pdata = {
 160         .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
 161         .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
 162 };
 163
 164 U_BOOT_DRVINFO(am33xx_spi) = {
 165         .name = "omap3_spi",
 166         .plat = &omap3_spi_pdata,
 167 };
 168 #endif
 169 #endif
 170
 171 #if !CONFIG_IS_ENABLED(DM_GPIO)
 172 static const struct gpio_bank gpio_bank_am33xx[] = {
 173         { (void *)AM33XX_GPIO0_BASE },
 174         { (void *)AM33XX_GPIO1_BASE },
 175         { (void *)AM33XX_GPIO2_BASE },
 176         { (void *)AM33XX_GPIO3_BASE },
 177 #ifdef CONFIG_AM43XX
 178         { (void *)AM33XX_GPIO4_BASE },
 179         { (void *)AM33XX_GPIO5_BASE },
 180 #endif
 181 };
 182
 183 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 184 #endif
 185
 186 #if defined(CONFIG_MMC_OMAP_HS)
 187 int cpu_mmc_init(struct bd_info *bis)
 188 {
 189         int ret;
 190
 191         ret = omap_mmc_init(0, 0, 0, -1, -1);
 192         if (ret)
 193                 return ret;
 194
 195         return omap_mmc_init(1, 0, 0, -1, -1);
 196 }
 197 #endif
 198
 199 /*
 200  * RTC only with DDR in self-refresh mode magic value, checked against during
 201  * boot to see if we have a valid config. This should be in sync with the value
 202  * that will be in drivers/soc/ti/pm33xx.c.
 203  */
 204 #define RTC_MAGIC_VAL           0x8cd0
 205
 206 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
 207 #define RTC_BOARD_TYPE_SHIFT    16
 208
 209 /* AM33XX has two MUSB controllers which can be host or gadget */
 210 #if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
 211         defined(CONFIG_SPL_BUILD)
 212
 213 static struct musb_hdrc_config musb_config = {
 214         .multipoint     = 1,
 215         .dyn_fifo       = 1,
 216         .num_eps        = 16,
 217         .ram_bits       = 12,
 218 };
 219
 220 #ifdef CONFIG_AM335X_USB0
 221 static struct ti_musb_plat usb0 = {
 222         .base = (void *)USB0_OTG_BASE,
 223         .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
 224         .plat = {
 225                 .config         = &musb_config,
 226                 .power          = 50,
 227                 .platform_ops   = &musb_dsps_ops,
 228                 },
 229 };
 230 #endif
 231
 232 #ifdef CONFIG_AM335X_USB1
 233 static struct ti_musb_plat usb1 = {
 234         .base = (void *)USB1_OTG_BASE,
 235         .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
 236         .plat = {
 237                 .config         = &musb_config,
 238                 .power          = 50,
 239                 .platform_ops   = &musb_dsps_ops,
 240                 },
 241 };
 242 #endif
 243
 244 U_BOOT_DRVINFOS(am33xx_usbs) = {
 245 #ifdef CONFIG_AM335X_USB0_PERIPHERAL
 246         { "ti-musb-peripheral", &usb0 },
 247 #elif defined(CONFIG_AM335X_USB0_HOST)
 248         { "ti-musb-host", &usb0 },
 249 #endif
 250 #ifdef CONFIG_AM335X_USB1_PERIPHERAL
 251         { "ti-musb-peripheral", &usb1 },
 252 #elif defined(CONFIG_AM335X_USB1_HOST)
 253         { "ti-musb-host", &usb1 },
 254 #endif
 255 };
 256
 257 int arch_misc_init(void)
 258 {
 259         return 0;
 260 }
 261 #else   /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
 262
 263 int arch_misc_init(void)
 264 {
 265         struct udevice *dev;
 266         int ret;
 267
 268         ret = uclass_first_device_err(UCLASS_MISC, &dev);
 269         if (ret)
 270                 return ret;
 271
 272 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
 273         usb_ether_init();
 274 #endif
 275
 276         return 0;
 277 }
 278
 279 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
 280
 281 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 282
 283 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
 284         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
 285 static void rtc32k_unlock(struct davinci_rtc *rtc)
 286 {
 287         /*
 288          * Unlock the RTC's registers.  For more details please see the
 289          * RTC_SS section of the TRM.  In order to unlock we need to
 290          * write these specific values (keys) in this order.
 291          */
 292         writel(RTC_KICK0R_WE, &rtc->kick0r);
 293         writel(RTC_KICK1R_WE, &rtc->kick1r);
 294 }
 295 #endif
 296
 297 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 298 /*
 299  * Write contents of the RTC_SCRATCH1 register based on board type
 300  * Two things are passed
 301  * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
 302  * control gets to kernel, kernel reads the scratchpad register and gets to
 303  * know that bootloader has rtc_only support.
 304  *
 305  * Second important thing is the board type  (16:31). This is needed in the
 306  * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
 307  * identify the board type and we go ahead and copy the board strings to
 308  * am43xx_board_name.
 309  */
 310 void update_rtc_magic(void)
 311 {
 312         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 313         u32 magic = RTC_MAGIC_VAL;
 314
 315         magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
 316
 317         rtc32k_unlock(rtc);
 318
 319         /* write magic */
 320         writel(magic, &rtc->scratch1);
 321 }
 322 #endif
 323
 324 /*
 325  * In the case of non-SPL based booting we'll want to call these
 326  * functions a tiny bit later as it will require gd to be set and cleared
 327  * and that's not true in s_init in this case so we cannot do it there.
 328  */
 329 int board_early_init_f(void)
 330 {
 331         set_mux_conf_regs();
 332         prcm_init();
 333 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 334         update_rtc_magic();
 335 #endif
 336         return 0;
 337 }
 338
 339 /*
 340  * This function is the place to do per-board things such as ramp up the
 341  * MPU clock frequency.
 342  */
 343 __weak void am33xx_spl_board_init(void)
 344 {
 345 }
 346
 347 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 348 static void rtc32k_enable(void)
 349 {
 350         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 351
 352         rtc32k_unlock(rtc);
 353
 354         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
 355         writel((1 << 3) | (1 << 6), &rtc->osc);
 356 }
 357 #endif
 358
 359 static void uart_soft_reset(void)
 360 {
 361         struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 362         u32 regval;
 363
 364         regval = readl(&uart_base->uartsyscfg);
 365         regval |= UART_RESET;
 366         writel(regval, &uart_base->uartsyscfg);
 367         while ((readl(&uart_base->uartsyssts) &
 368                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 369                 ;
 370
 371         /* Disable smart idle */
 372         regval = readl(&uart_base->uartsyscfg);
 373         regval |= UART_SMART_IDLE_EN;
 374         writel(regval, &uart_base->uartsyscfg);
 375 }
 376
 377 static void watchdog_disable(void)
 378 {
 379         struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 380
 381         writel(0xAAAA, &wdtimer->wdtwspr);
 382         while (readl(&wdtimer->wdtwwps) != 0x0)
 383                 ;
 384         writel(0x5555, &wdtimer->wdtwspr);
 385         while (readl(&wdtimer->wdtwwps) != 0x0)
 386                 ;
 387 }
 388
 389 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 390 /*
 391  * Check if we are executing rtc-only + DDR mode, and resume from it if needed
 392  */
 393 static void rtc_only(void)
 394 {
 395         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 396         struct prm_device_inst *prm_device =
 397                                 (struct prm_device_inst *)PRM_DEVICE_INST;
 398
 399         u32 scratch1, sdrc;
 400         void (*resume_func)(void);
 401
 402         scratch1 = readl(&rtc->scratch1);
 403
 404         /*
 405          * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
 406          * written to this register when we want to wake up from RTC only
 407          * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
 408          * bits 0-15:  RTC_MAGIC_VAL
 409          * bits 16-31: board type (needed for sdram_init)
 410          */
 411         if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
 412                 return;
 413
 414         rtc32k_unlock(rtc);
 415
 416         /* Clear RTC magic */
 417         writel(0, &rtc->scratch1);
 418
 419         /*
 420          * Update board type based on value stored on RTC_SCRATCH1, this
 421          * is done so that we don't need to read the board type from eeprom
 422          * over i2c bus which is expensive
 423          */
 424         rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
 425
 426         /*
 427          * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
 428          * are resuming from self-refresh. This avoids an unnecessary re-init
 429          * of the DDR. The re-init takes time and we would need to wait for
 430          * it to complete before accessing DDR to avoid L3 NOC errors.
 431          */
 432         writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
 433
 434         rtc_only_prcm_init();
 435         sdram_init();
 436
 437         /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
 438         /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
 439         sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
 440
 441         sdrc &= AM43XX_SDRAM_TYPE_MASK;
 442         sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
 443
 444         if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
 445                 writel(AM43XX_RDWRLVLFULL_START,
 446                        AM43XX_EMIF_BASE +
 447                        AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
 448                 mdelay(1);
 449
 450 am43xx_wait:
 451                 sdrc = readl(AM43XX_EMIF_BASE +
 452                              AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
 453                 if (sdrc == AM43XX_RDWRLVLFULL_START)
 454                         goto am43xx_wait;
 455         }
 456
 457         resume_func = (void *)readl(&rtc->scratch0);
 458         if (resume_func)
 459                 resume_func();
 460 }
 461 #endif
 462
 463 void s_init(void)
 464 {
 465 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 466         rtc_only();
 467 #endif
 468 }
 469
 470 void early_system_init(void)
 471 {
 472         /*
 473          * The ROM will only have set up sufficient pinmux to allow for the
 474          * first 4KiB NOR to be read, we must finish doing what we know of
 475          * the NOR mux in this space in order to continue.
 476          */
 477 #ifdef CONFIG_NOR_BOOT
 478         enable_norboot_pin_mux();
 479 #endif
 480         watchdog_disable();
 481         set_uart_mux_conf();
 482         setup_early_clocks();
 483         uart_soft_reset();
 484 #ifdef CONFIG_SPL_BUILD
 485         /*
 486          * Save the boot parameters passed from romcode.
 487          * We cannot delay the saving further than this,
 488          * to prevent overwrites.
 489          */
 490         save_omap_boot_params();
 491 #endif
 492 #ifdef CONFIG_DEBUG_UART_OMAP
 493         debug_uart_init();
 494 #endif
 495
 496 #ifdef CONFIG_SPL_BUILD
 497         spl_early_init();
 498 #endif
 499
 500 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 501         do_board_detect();
 502 #endif
 503
 504 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 505         /* Enable RTC32K clock */
 506         rtc32k_enable();
 507 #endif
 508 }
 509
 510 #ifdef CONFIG_SPL_BUILD
 511 void board_init_f(ulong dummy)
 512 {
 513         hw_data_init();
 514         early_system_init();
 515         board_early_init_f();
 516         sdram_init();
 517         /* dram_init must store complete ramsize in gd->ram_size */
 518         gd->ram_size = get_ram_size(
 519                         (void *)CFG_SYS_SDRAM_BASE,
 520                         CFG_MAX_RAM_BANK_SIZE);
 521 }
 522 #endif
 523
 524 #endif
 525
 526 static int am33xx_dm_post_init(void)
 527 {
 528         hw_data_init();
 529 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 530         early_system_init();
 531 #endif
 532         return 0;
 533 }
 534 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);