arch/arm/mach-omap2/am33xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Common board functions for AM33XX based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <debug_uart.h>
  13 #include <errno.h>
  14 #include <init.h>
  15 #include <ns16550.h>
  16 #include <spl.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/omap.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/i2c.h>
  24 #include <asm/arch/mem.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <asm/omap_common.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <linux/errno.h>
  35 #include <linux/compiler.h>
  36 #include <linux/usb/ch9.h>
  37 #include <linux/usb/gadget.h>
  38 #include <linux/usb/musb.h>
  39 #include <asm/omap_musb.h>
  40 #include <asm/davinci_rtc.h>
  41
  42 #define AM43XX_EMIF_BASE                                0x4C000000
  43 #define AM43XX_SDRAM_CONFIG_OFFSET                      0x8
  44 #define AM43XX_SDRAM_TYPE_MASK                          0xE0000000
  45 #define AM43XX_SDRAM_TYPE_SHIFT                         29
  46 #define AM43XX_SDRAM_TYPE_DDR3                          3
  47 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET          0xDC
  48 #define AM43XX_RDWRLVLFULL_START                        0x80000000
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 int dram_init(void)
  53 {
  54 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  55         sdram_init();
  56 #endif
  57
  58         /* dram_init must store complete ramsize in gd->ram_size */
  59         gd->ram_size = get_ram_size(
  60                         (void *)CONFIG_SYS_SDRAM_BASE,
  61                         CONFIG_MAX_RAM_BANK_SIZE);
  62         return 0;
  63 }
  64
  65 int dram_init_banksize(void)
  66 {
  67         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  68         gd->bd->bi_dram[0].size = gd->ram_size;
  69
  70         return 0;
  71 }
  72
  73 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  74 static const struct ns16550_platdata am33xx_serial[] = {
  75         { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  76           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  77 # ifdef CONFIG_SYS_NS16550_COM2
  78         { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  79           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  80 #  ifdef CONFIG_SYS_NS16550_COM3
  81         { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  82           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  83         { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  84           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  85         { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  86           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  87         { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  88           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  89 #  endif
  90 # endif
  91 };
  92
  93 U_BOOT_DEVICES(am33xx_uarts) = {
  94         { "ns16550_serial", &am33xx_serial[0] },
  95 #  ifdef CONFIG_SYS_NS16550_COM2
  96         { "ns16550_serial", &am33xx_serial[1] },
  97 #   ifdef CONFIG_SYS_NS16550_COM3
  98         { "ns16550_serial", &am33xx_serial[2] },
  99         { "ns16550_serial", &am33xx_serial[3] },
 100         { "ns16550_serial", &am33xx_serial[4] },
 101         { "ns16550_serial", &am33xx_serial[5] },
 102 #   endif
 103 #  endif
 104 };
 105
 106 #ifdef CONFIG_DM_I2C
 107 static const struct omap_i2c_platdata am33xx_i2c[] = {
 108         { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
 109         { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
 110         { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
 111 };
 112
 113 U_BOOT_DEVICES(am33xx_i2c) = {
 114         { "i2c_omap", &am33xx_i2c[0] },
 115         { "i2c_omap", &am33xx_i2c[1] },
 116         { "i2c_omap", &am33xx_i2c[2] },
 117 };
 118 #endif
 119
 120 #if CONFIG_IS_ENABLED(DM_GPIO)
 121 static const struct omap_gpio_platdata am33xx_gpio[] = {
 122         { 0, AM33XX_GPIO0_BASE },
 123         { 1, AM33XX_GPIO1_BASE },
 124         { 2, AM33XX_GPIO2_BASE },
 125         { 3, AM33XX_GPIO3_BASE },
 126 #ifdef CONFIG_AM43XX
 127         { 4, AM33XX_GPIO4_BASE },
 128         { 5, AM33XX_GPIO5_BASE },
 129 #endif
 130 };
 131
 132 U_BOOT_DEVICES(am33xx_gpios) = {
 133         { "gpio_omap", &am33xx_gpio[0] },
 134         { "gpio_omap", &am33xx_gpio[1] },
 135         { "gpio_omap", &am33xx_gpio[2] },
 136         { "gpio_omap", &am33xx_gpio[3] },
 137 #ifdef CONFIG_AM43XX
 138         { "gpio_omap", &am33xx_gpio[4] },
 139         { "gpio_omap", &am33xx_gpio[5] },
 140 #endif
 141 };
 142 #endif
 143 #endif
 144
 145 #if !CONFIG_IS_ENABLED(DM_GPIO)
 146 static const struct gpio_bank gpio_bank_am33xx[] = {
 147         { (void *)AM33XX_GPIO0_BASE },
 148         { (void *)AM33XX_GPIO1_BASE },
 149         { (void *)AM33XX_GPIO2_BASE },
 150         { (void *)AM33XX_GPIO3_BASE },
 151 #ifdef CONFIG_AM43XX
 152         { (void *)AM33XX_GPIO4_BASE },
 153         { (void *)AM33XX_GPIO5_BASE },
 154 #endif
 155 };
 156
 157 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 158 #endif
 159
 160 #if defined(CONFIG_MMC_OMAP_HS)
 161 int cpu_mmc_init(bd_t *bis)
 162 {
 163         int ret;
 164
 165         ret = omap_mmc_init(0, 0, 0, -1, -1);
 166         if (ret)
 167                 return ret;
 168
 169         return omap_mmc_init(1, 0, 0, -1, -1);
 170 }
 171 #endif
 172
 173 /*
 174  * RTC only with DDR in self-refresh mode magic value, checked against during
 175  * boot to see if we have a valid config. This should be in sync with the value
 176  * that will be in drivers/soc/ti/pm33xx.c.
 177  */
 178 #define RTC_MAGIC_VAL           0x8cd0
 179
 180 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
 181 #define RTC_BOARD_TYPE_SHIFT    16
 182
 183 /* AM33XX has two MUSB controllers which can be host or gadget */
 184 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
 185         (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
 186         (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
 187         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
 188
 189 static struct musb_hdrc_config musb_config = {
 190         .multipoint     = 1,
 191         .dyn_fifo       = 1,
 192         .num_eps        = 16,
 193         .ram_bits       = 12,
 194 };
 195
 196 #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
 197 static struct ti_musb_platdata usb0 = {
 198         .base = (void *)USB0_OTG_BASE,
 199         .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
 200         .plat = {
 201                 .config         = &musb_config,
 202                 .power          = 50,
 203                 .platform_ops   = &musb_dsps_ops,
 204                 },
 205 };
 206
 207 static struct ti_musb_platdata usb1 = {
 208         .base = (void *)USB1_OTG_BASE,
 209         .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
 210         .plat = {
 211                 .config         = &musb_config,
 212                 .power          = 50,
 213                 .platform_ops   = &musb_dsps_ops,
 214                 },
 215 };
 216
 217 U_BOOT_DEVICES(am33xx_usbs) = {
 218 #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
 219         { "ti-musb-peripheral", &usb0 },
 220 #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
 221         { "ti-musb-host", &usb0 },
 222 #endif
 223 #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
 224         { "ti-musb-peripheral", &usb1 },
 225 #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
 226         { "ti-musb-host", &usb1 },
 227 #endif
 228 };
 229
 230 int arch_misc_init(void)
 231 {
 232         return 0;
 233 }
 234 #else
 235 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 236
 237 /* USB 2.0 PHY Control */
 238 #define CM_PHY_PWRDN                    (1 << 0)
 239 #define CM_PHY_OTG_PWRDN                (1 << 1)
 240 #define OTGVDET_EN                      (1 << 19)
 241 #define OTGSESSENDEN                    (1 << 20)
 242
 243 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
 244 {
 245         if (on) {
 246                 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
 247                                 OTGVDET_EN | OTGSESSENDEN);
 248         } else {
 249                 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
 250         }
 251 }
 252
 253 #ifdef CONFIG_AM335X_USB0
 254 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
 255 {
 256         am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
 257 }
 258
 259 struct omap_musb_board_data otg0_board_data = {
 260         .set_phy_power = am33xx_otg0_set_phy_power,
 261 };
 262
 263 static struct musb_hdrc_platform_data otg0_plat = {
 264         .mode           = CONFIG_AM335X_USB0_MODE,
 265         .config         = &musb_config,
 266         .power          = 50,
 267         .platform_ops   = &musb_dsps_ops,
 268         .board_data     = &otg0_board_data,
 269 };
 270 #endif
 271
 272 #ifdef CONFIG_AM335X_USB1
 273 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
 274 {
 275         am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
 276 }
 277
 278 struct omap_musb_board_data otg1_board_data = {
 279         .set_phy_power = am33xx_otg1_set_phy_power,
 280 };
 281
 282 static struct musb_hdrc_platform_data otg1_plat = {
 283         .mode           = CONFIG_AM335X_USB1_MODE,
 284         .config         = &musb_config,
 285         .power          = 50,
 286         .platform_ops   = &musb_dsps_ops,
 287         .board_data     = &otg1_board_data,
 288 };
 289 #endif
 290
 291 int arch_misc_init(void)
 292 {
 293 #ifdef CONFIG_AM335X_USB0
 294         musb_register(&otg0_plat, &otg0_board_data,
 295                 (void *)USB0_OTG_BASE);
 296 #endif
 297 #ifdef CONFIG_AM335X_USB1
 298         musb_register(&otg1_plat, &otg1_board_data,
 299                 (void *)USB1_OTG_BASE);
 300 #endif
 301         return 0;
 302 }
 303 #endif
 304
 305 #else   /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
 306
 307 int arch_misc_init(void)
 308 {
 309         struct udevice *dev;
 310         int ret;
 311
 312         ret = uclass_first_device(UCLASS_MISC, &dev);
 313         if (ret || !dev)
 314                 return ret;
 315
 316 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
 317         ret = usb_ether_init();
 318         if (ret) {
 319                 pr_err("USB ether init failed\n");
 320                 return ret;
 321         }
 322 #endif
 323
 324         return 0;
 325 }
 326
 327 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
 328
 329 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 330
 331 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
 332         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
 333 static void rtc32k_unlock(struct davinci_rtc *rtc)
 334 {
 335         /*
 336          * Unlock the RTC's registers.  For more details please see the
 337          * RTC_SS section of the TRM.  In order to unlock we need to
 338          * write these specific values (keys) in this order.
 339          */
 340         writel(RTC_KICK0R_WE, &rtc->kick0r);
 341         writel(RTC_KICK1R_WE, &rtc->kick1r);
 342 }
 343 #endif
 344
 345 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 346 /*
 347  * Write contents of the RTC_SCRATCH1 register based on board type
 348  * Two things are passed
 349  * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
 350  * control gets to kernel, kernel reads the scratchpad register and gets to
 351  * know that bootloader has rtc_only support.
 352  *
 353  * Second important thing is the board type  (16:31). This is needed in the
 354  * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
 355  * identify the board type and we go ahead and copy the board strings to
 356  * am43xx_board_name.
 357  */
 358 void update_rtc_magic(void)
 359 {
 360         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 361         u32 magic = RTC_MAGIC_VAL;
 362
 363         magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
 364
 365         rtc32k_unlock(rtc);
 366
 367         /* write magic */
 368         writel(magic, &rtc->scratch1);
 369 }
 370 #endif
 371
 372 /*
 373  * In the case of non-SPL based booting we'll want to call these
 374  * functions a tiny bit later as it will require gd to be set and cleared
 375  * and that's not true in s_init in this case so we cannot do it there.
 376  */
 377 int board_early_init_f(void)
 378 {
 379         set_mux_conf_regs();
 380         prcm_init();
 381 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 382         update_rtc_magic();
 383 #endif
 384         return 0;
 385 }
 386
 387 /*
 388  * This function is the place to do per-board things such as ramp up the
 389  * MPU clock frequency.
 390  */
 391 __weak void am33xx_spl_board_init(void)
 392 {
 393 }
 394
 395 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 396 static void rtc32k_enable(void)
 397 {
 398         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 399
 400         rtc32k_unlock(rtc);
 401
 402         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
 403         writel((1 << 3) | (1 << 6), &rtc->osc);
 404 }
 405 #endif
 406
 407 static void uart_soft_reset(void)
 408 {
 409         struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 410         u32 regval;
 411
 412         regval = readl(&uart_base->uartsyscfg);
 413         regval |= UART_RESET;
 414         writel(regval, &uart_base->uartsyscfg);
 415         while ((readl(&uart_base->uartsyssts) &
 416                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 417                 ;
 418
 419         /* Disable smart idle */
 420         regval = readl(&uart_base->uartsyscfg);
 421         regval |= UART_SMART_IDLE_EN;
 422         writel(regval, &uart_base->uartsyscfg);
 423 }
 424
 425 static void watchdog_disable(void)
 426 {
 427         struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 428
 429         writel(0xAAAA, &wdtimer->wdtwspr);
 430         while (readl(&wdtimer->wdtwwps) != 0x0)
 431                 ;
 432         writel(0x5555, &wdtimer->wdtwspr);
 433         while (readl(&wdtimer->wdtwwps) != 0x0)
 434                 ;
 435 }
 436
 437 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 438 /*
 439  * Check if we are executing rtc-only + DDR mode, and resume from it if needed
 440  */
 441 static void rtc_only(void)
 442 {
 443         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 444         struct prm_device_inst *prm_device =
 445                                 (struct prm_device_inst *)PRM_DEVICE_INST;
 446
 447         u32 scratch1, sdrc;
 448         void (*resume_func)(void);
 449
 450         scratch1 = readl(&rtc->scratch1);
 451
 452         /*
 453          * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
 454          * written to this register when we want to wake up from RTC only
 455          * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
 456          * bits 0-15:  RTC_MAGIC_VAL
 457          * bits 16-31: board type (needed for sdram_init)
 458          */
 459         if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
 460                 return;
 461
 462         rtc32k_unlock(rtc);
 463
 464         /* Clear RTC magic */
 465         writel(0, &rtc->scratch1);
 466
 467         /*
 468          * Update board type based on value stored on RTC_SCRATCH1, this
 469          * is done so that we don't need to read the board type from eeprom
 470          * over i2c bus which is expensive
 471          */
 472         rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
 473
 474         /*
 475          * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
 476          * are resuming from self-refresh. This avoids an unnecessary re-init
 477          * of the DDR. The re-init takes time and we would need to wait for
 478          * it to complete before accessing DDR to avoid L3 NOC errors.
 479          */
 480         writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
 481
 482         rtc_only_prcm_init();
 483         sdram_init();
 484
 485         /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
 486         /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
 487         sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
 488
 489         sdrc &= AM43XX_SDRAM_TYPE_MASK;
 490         sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
 491
 492         if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
 493                 writel(AM43XX_RDWRLVLFULL_START,
 494                        AM43XX_EMIF_BASE +
 495                        AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
 496                 mdelay(1);
 497
 498 am43xx_wait:
 499                 sdrc = readl(AM43XX_EMIF_BASE +
 500                              AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
 501                 if (sdrc == AM43XX_RDWRLVLFULL_START)
 502                         goto am43xx_wait;
 503         }
 504
 505         resume_func = (void *)readl(&rtc->scratch0);
 506         if (resume_func)
 507                 resume_func();
 508 }
 509 #endif
 510
 511 void s_init(void)
 512 {
 513 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
 514         rtc_only();
 515 #endif
 516 }
 517
 518 void early_system_init(void)
 519 {
 520         /*
 521          * The ROM will only have set up sufficient pinmux to allow for the
 522          * first 4KiB NOR to be read, we must finish doing what we know of
 523          * the NOR mux in this space in order to continue.
 524          */
 525 #ifdef CONFIG_NOR_BOOT
 526         enable_norboot_pin_mux();
 527 #endif
 528         watchdog_disable();
 529         set_uart_mux_conf();
 530         setup_early_clocks();
 531         uart_soft_reset();
 532 #ifdef CONFIG_SPL_BUILD
 533         /*
 534          * Save the boot parameters passed from romcode.
 535          * We cannot delay the saving further than this,
 536          * to prevent overwrites.
 537          */
 538         save_omap_boot_params();
 539 #endif
 540 #ifdef CONFIG_DEBUG_UART_OMAP
 541         debug_uart_init();
 542 #endif
 543
 544 #ifdef CONFIG_SPL_BUILD
 545         spl_early_init();
 546 #endif
 547
 548 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 549         do_board_detect();
 550 #endif
 551
 552 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 553         /* Enable RTC32K clock */
 554         rtc32k_enable();
 555 #endif
 556 }
 557
 558 #ifdef CONFIG_SPL_BUILD
 559 void board_init_f(ulong dummy)
 560 {
 561         hw_data_init();
 562         early_system_init();
 563         board_early_init_f();
 564         sdram_init();
 565         /* dram_init must store complete ramsize in gd->ram_size */
 566         gd->ram_size = get_ram_size(
 567                         (void *)CONFIG_SYS_SDRAM_BASE,
 568                         CONFIG_MAX_RAM_BANK_SIZE);
 569 }
 570 #endif
 571
 572 #endif
 573
 574 int arch_cpu_init_dm(void)
 575 {
 576         hw_data_init();
 577 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 578         early_system_init();
 579 #endif
 580         return 0;
 581 }