arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26
  27 #include "omap_hwmod.h"
  28 #include "omap_hwmod_common_data.h"
  29 #include "cm1_54xx.h"
  30 #include "cm2_54xx.h"
  31 #include "prm54xx.h"
  32 #include "i2c.h"
  33 #include "wd_timer.h"
  34
  35 /* Base offset for all OMAP5 interrupts external to MPUSS */
  36 #define OMAP54XX_IRQ_GIC_START  32
  37
  38 /* Base offset for all OMAP5 dma requests */
  39 #define OMAP54XX_DMA_REQ_START  1
  40
  41
  42 /*
  43  * IP blocks
  44  */
  45
  46 /*
  47  * 'dmm' class
  48  * instance(s): dmm
  49  */
  50 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  51         .name   = "dmm",
  52 };
  53
  54 /* dmm */
  55 static struct omap_hwmod omap54xx_dmm_hwmod = {
  56         .name           = "dmm",
  57         .class          = &omap54xx_dmm_hwmod_class,
  58         .clkdm_name     = "emif_clkdm",
  59         .prcm = {
  60                 .omap4 = {
  61                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  62                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  63                 },
  64         },
  65 };
  66
  67 /*
  68  * 'l3' class
  69  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  70  */
  71 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  72         .name   = "l3",
  73 };
  74
  75 /* l3_instr */
  76 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  77         .name           = "l3_instr",
  78         .class          = &omap54xx_l3_hwmod_class,
  79         .clkdm_name     = "l3instr_clkdm",
  80         .prcm = {
  81                 .omap4 = {
  82                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  83                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  84                         .modulemode   = MODULEMODE_HWCTRL,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_1 */
  90 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  91         .name           = "l3_main_1",
  92         .class          = &omap54xx_l3_hwmod_class,
  93         .clkdm_name     = "l3main1_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /* l3_main_2 */
 103 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 104         .name           = "l3_main_2",
 105         .class          = &omap54xx_l3_hwmod_class,
 106         .clkdm_name     = "l3main2_clkdm",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 110                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 111                 },
 112         },
 113 };
 114
 115 /* l3_main_3 */
 116 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 117         .name           = "l3_main_3",
 118         .class          = &omap54xx_l3_hwmod_class,
 119         .clkdm_name     = "l3instr_clkdm",
 120         .prcm = {
 121                 .omap4 = {
 122                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 123                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 124                         .modulemode   = MODULEMODE_HWCTRL,
 125                 },
 126         },
 127 };
 128
 129 /*
 130  * 'l4' class
 131  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 132  */
 133 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 134         .name   = "l4",
 135 };
 136
 137 /* l4_abe */
 138 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 139         .name           = "l4_abe",
 140         .class          = &omap54xx_l4_hwmod_class,
 141         .clkdm_name     = "abe_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 145                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 146                 },
 147         },
 148 };
 149
 150 /* l4_cfg */
 151 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 152         .name           = "l4_cfg",
 153         .class          = &omap54xx_l4_hwmod_class,
 154         .clkdm_name     = "l4cfg_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /* l4_per */
 164 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 165         .name           = "l4_per",
 166         .class          = &omap54xx_l4_hwmod_class,
 167         .clkdm_name     = "l4per_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 171                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /* l4_wkup */
 177 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 178         .name           = "l4_wkup",
 179         .class          = &omap54xx_l4_hwmod_class,
 180         .clkdm_name     = "wkupaon_clkdm",
 181         .prcm = {
 182                 .omap4 = {
 183                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 184                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 185                 },
 186         },
 187 };
 188
 189 /*
 190  * 'mpu_bus' class
 191  * instance(s): mpu_private
 192  */
 193 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 194         .name   = "mpu_bus",
 195 };
 196
 197 /* mpu_private */
 198 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 199         .name           = "mpu_private",
 200         .class          = &omap54xx_mpu_bus_hwmod_class,
 201         .clkdm_name     = "mpu_clkdm",
 202         .prcm = {
 203                 .omap4 = {
 204                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 205                 },
 206         },
 207 };
 208
 209 /*
 210  * 'counter' class
 211  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 212  */
 213
 214 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 215         .rev_offs       = 0x0000,
 216         .sysc_offs      = 0x0010,
 217         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 218         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 219         .sysc_fields    = &omap_hwmod_sysc_type1,
 220 };
 221
 222 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 223         .name   = "counter",
 224         .sysc   = &omap54xx_counter_sysc,
 225 };
 226
 227 /* counter_32k */
 228 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 229         .name           = "counter_32k",
 230         .class          = &omap54xx_counter_hwmod_class,
 231         .clkdm_name     = "wkupaon_clkdm",
 232         .flags          = HWMOD_SWSUP_SIDLE,
 233         .main_clk       = "wkupaon_iclk_mux",
 234         .prcm = {
 235                 .omap4 = {
 236                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 237                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'dma' class
 244  * dma controller for data exchange between memory to memory (i.e. internal or
 245  * external memory) and gp peripherals to memory or memory to gp peripherals
 246  */
 247
 248 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 249         .rev_offs       = 0x0000,
 250         .sysc_offs      = 0x002c,
 251         .syss_offs      = 0x0028,
 252         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 253                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 254                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 255                            SYSS_HAS_RESET_STATUS),
 256         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 257                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 258         .sysc_fields    = &omap_hwmod_sysc_type1,
 259 };
 260
 261 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 262         .name   = "dma",
 263         .sysc   = &omap54xx_dma_sysc,
 264 };
 265
 266 /* dma dev_attr */
 267 static struct omap_dma_dev_attr dma_dev_attr = {
 268         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 269                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 270         .lch_count      = 32,
 271 };
 272
 273 /* dma_system */
 274 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 275         .name           = "dma_system",
 276         .class          = &omap54xx_dma_hwmod_class,
 277         .clkdm_name     = "dma_clkdm",
 278         .main_clk       = "l3_iclk_div",
 279         .prcm = {
 280                 .omap4 = {
 281                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 282                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 283                 },
 284         },
 285         .dev_attr       = &dma_dev_attr,
 286 };
 287
 288 /*
 289  * 'dmic' class
 290  * digital microphone controller
 291  */
 292
 293 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 294         .rev_offs       = 0x0000,
 295         .sysc_offs      = 0x0010,
 296         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 297                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 298         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 299                            SIDLE_SMART_WKUP),
 300         .sysc_fields    = &omap_hwmod_sysc_type2,
 301 };
 302
 303 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 304         .name   = "dmic",
 305         .sysc   = &omap54xx_dmic_sysc,
 306 };
 307
 308 /* dmic */
 309 static struct omap_hwmod omap54xx_dmic_hwmod = {
 310         .name           = "dmic",
 311         .class          = &omap54xx_dmic_hwmod_class,
 312         .clkdm_name     = "abe_clkdm",
 313         .main_clk       = "dmic_gfclk",
 314         .prcm = {
 315                 .omap4 = {
 316                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 317                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 318                         .modulemode   = MODULEMODE_SWCTRL,
 319                 },
 320         },
 321 };
 322
 323 /*
 324  * 'dss' class
 325  * display sub-system
 326  */
 327 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 328         .rev_offs       = 0x0000,
 329         .syss_offs      = 0x0014,
 330         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 331 };
 332
 333 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 334         .name   = "dss",
 335         .sysc   = &omap54xx_dss_sysc,
 336         .reset  = omap_dss_reset,
 337 };
 338
 339 /* dss */
 340 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 341         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 342         { .role = "sys_clk", .clk = "dss_sys_clk" },
 343         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 344 };
 345
 346 static struct omap_hwmod omap54xx_dss_hwmod = {
 347         .name           = "dss_core",
 348         .class          = &omap54xx_dss_hwmod_class,
 349         .clkdm_name     = "dss_clkdm",
 350         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 351         .main_clk       = "dss_dss_clk",
 352         .prcm = {
 353                 .omap4 = {
 354                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 355                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 356                         .modulemode   = MODULEMODE_SWCTRL,
 357                 },
 358         },
 359         .opt_clks       = dss_opt_clks,
 360         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 361 };
 362
 363 /*
 364  * 'dispc' class
 365  * display controller
 366  */
 367
 368 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 369         .rev_offs       = 0x0000,
 370         .sysc_offs      = 0x0010,
 371         .syss_offs      = 0x0014,
 372         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 373                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 374                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 375                            SYSS_HAS_RESET_STATUS),
 376         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 377                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 378         .sysc_fields    = &omap_hwmod_sysc_type1,
 379 };
 380
 381 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 382         .name   = "dispc",
 383         .sysc   = &omap54xx_dispc_sysc,
 384 };
 385
 386 /* dss_dispc */
 387 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 388         { .role = "sys_clk", .clk = "dss_sys_clk" },
 389 };
 390
 391 /* dss_dispc dev_attr */
 392 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 393         .has_framedonetv_irq    = 1,
 394         .manager_count          = 4,
 395 };
 396
 397 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 398         .name           = "dss_dispc",
 399         .class          = &omap54xx_dispc_hwmod_class,
 400         .clkdm_name     = "dss_clkdm",
 401         .main_clk       = "dss_dss_clk",
 402         .prcm = {
 403                 .omap4 = {
 404                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 405                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 406                 },
 407         },
 408         .opt_clks       = dss_dispc_opt_clks,
 409         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 410         .dev_attr       = &dss_dispc_dev_attr,
 411         .parent_hwmod   = &omap54xx_dss_hwmod,
 412 };
 413
 414 /*
 415  * 'dsi1' class
 416  * display serial interface controller
 417  */
 418
 419 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 420         .rev_offs       = 0x0000,
 421         .sysc_offs      = 0x0010,
 422         .syss_offs      = 0x0014,
 423         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 424                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 425                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 426         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 427         .sysc_fields    = &omap_hwmod_sysc_type1,
 428 };
 429
 430 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 431         .name   = "dsi1",
 432         .sysc   = &omap54xx_dsi1_sysc,
 433 };
 434
 435 /* dss_dsi1_a */
 436 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 437         { .role = "sys_clk", .clk = "dss_sys_clk" },
 438 };
 439
 440 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 441         .name           = "dss_dsi1",
 442         .class          = &omap54xx_dsi1_hwmod_class,
 443         .clkdm_name     = "dss_clkdm",
 444         .main_clk       = "dss_dss_clk",
 445         .prcm = {
 446                 .omap4 = {
 447                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 448                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 449                 },
 450         },
 451         .opt_clks       = dss_dsi1_a_opt_clks,
 452         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 453         .parent_hwmod   = &omap54xx_dss_hwmod,
 454 };
 455
 456 /* dss_dsi1_c */
 457 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 458         { .role = "sys_clk", .clk = "dss_sys_clk" },
 459 };
 460
 461 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 462         .name           = "dss_dsi2",
 463         .class          = &omap54xx_dsi1_hwmod_class,
 464         .clkdm_name     = "dss_clkdm",
 465         .main_clk       = "dss_dss_clk",
 466         .prcm = {
 467                 .omap4 = {
 468                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 469                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 470                 },
 471         },
 472         .opt_clks       = dss_dsi1_c_opt_clks,
 473         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 474         .parent_hwmod   = &omap54xx_dss_hwmod,
 475 };
 476
 477 /*
 478  * 'hdmi' class
 479  * hdmi controller
 480  */
 481
 482 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 483         .rev_offs       = 0x0000,
 484         .sysc_offs      = 0x0010,
 485         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 486                            SYSC_HAS_SOFTRESET),
 487         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 488                            SIDLE_SMART_WKUP),
 489         .sysc_fields    = &omap_hwmod_sysc_type2,
 490 };
 491
 492 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 493         .name   = "hdmi",
 494         .sysc   = &omap54xx_hdmi_sysc,
 495 };
 496
 497 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 498         { .role = "sys_clk", .clk = "dss_sys_clk" },
 499 };
 500
 501 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 502         .name           = "dss_hdmi",
 503         .class          = &omap54xx_hdmi_hwmod_class,
 504         .clkdm_name     = "dss_clkdm",
 505         .main_clk       = "dss_48mhz_clk",
 506         .prcm = {
 507                 .omap4 = {
 508                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 509                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 510                 },
 511         },
 512         .opt_clks       = dss_hdmi_opt_clks,
 513         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 514         .parent_hwmod   = &omap54xx_dss_hwmod,
 515 };
 516
 517 /*
 518  * 'rfbi' class
 519  * remote frame buffer interface
 520  */
 521
 522 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 523         .rev_offs       = 0x0000,
 524         .sysc_offs      = 0x0010,
 525         .syss_offs      = 0x0014,
 526         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 527                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 528         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 529         .sysc_fields    = &omap_hwmod_sysc_type1,
 530 };
 531
 532 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 533         .name   = "rfbi",
 534         .sysc   = &omap54xx_rfbi_sysc,
 535 };
 536
 537 /* dss_rfbi */
 538 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 539         { .role = "ick", .clk = "l3_iclk_div" },
 540 };
 541
 542 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 543         .name           = "dss_rfbi",
 544         .class          = &omap54xx_rfbi_hwmod_class,
 545         .clkdm_name     = "dss_clkdm",
 546         .prcm = {
 547                 .omap4 = {
 548                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 549                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 550                 },
 551         },
 552         .opt_clks       = dss_rfbi_opt_clks,
 553         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 554         .parent_hwmod   = &omap54xx_dss_hwmod,
 555 };
 556
 557 /*
 558  * 'emif' class
 559  * external memory interface no1 (wrapper)
 560  */
 561
 562 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 563         .rev_offs       = 0x0000,
 564 };
 565
 566 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 567         .name   = "emif",
 568         .sysc   = &omap54xx_emif_sysc,
 569 };
 570
 571 /* emif1 */
 572 static struct omap_hwmod omap54xx_emif1_hwmod = {
 573         .name           = "emif1",
 574         .class          = &omap54xx_emif_hwmod_class,
 575         .clkdm_name     = "emif_clkdm",
 576         .flags          = HWMOD_INIT_NO_IDLE,
 577         .main_clk       = "dpll_core_h11x2_ck",
 578         .prcm = {
 579                 .omap4 = {
 580                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 581                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 582                         .modulemode   = MODULEMODE_HWCTRL,
 583                 },
 584         },
 585 };
 586
 587 /* emif2 */
 588 static struct omap_hwmod omap54xx_emif2_hwmod = {
 589         .name           = "emif2",
 590         .class          = &omap54xx_emif_hwmod_class,
 591         .clkdm_name     = "emif_clkdm",
 592         .flags          = HWMOD_INIT_NO_IDLE,
 593         .main_clk       = "dpll_core_h11x2_ck",
 594         .prcm = {
 595                 .omap4 = {
 596                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 597                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 598                         .modulemode   = MODULEMODE_HWCTRL,
 599                 },
 600         },
 601 };
 602
 603 /*
 604  * 'gpio' class
 605  * general purpose io module
 606  */
 607
 608 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 609         .rev_offs       = 0x0000,
 610         .sysc_offs      = 0x0010,
 611         .syss_offs      = 0x0114,
 612         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 613                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 614                            SYSS_HAS_RESET_STATUS),
 615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 616                            SIDLE_SMART_WKUP),
 617         .sysc_fields    = &omap_hwmod_sysc_type1,
 618 };
 619
 620 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 621         .name   = "gpio",
 622         .sysc   = &omap54xx_gpio_sysc,
 623         .rev    = 2,
 624 };
 625
 626 /* gpio1 */
 627 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 628         { .role = "dbclk", .clk = "gpio1_dbclk" },
 629 };
 630
 631 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 632         .name           = "gpio1",
 633         .class          = &omap54xx_gpio_hwmod_class,
 634         .clkdm_name     = "wkupaon_clkdm",
 635         .main_clk       = "wkupaon_iclk_mux",
 636         .prcm = {
 637                 .omap4 = {
 638                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 639                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 640                         .modulemode   = MODULEMODE_HWCTRL,
 641                 },
 642         },
 643         .opt_clks       = gpio1_opt_clks,
 644         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 645 };
 646
 647 /* gpio2 */
 648 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 649         { .role = "dbclk", .clk = "gpio2_dbclk" },
 650 };
 651
 652 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 653         .name           = "gpio2",
 654         .class          = &omap54xx_gpio_hwmod_class,
 655         .clkdm_name     = "l4per_clkdm",
 656         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 657         .main_clk       = "l4_root_clk_div",
 658         .prcm = {
 659                 .omap4 = {
 660                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 661                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665         .opt_clks       = gpio2_opt_clks,
 666         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 667 };
 668
 669 /* gpio3 */
 670 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 671         { .role = "dbclk", .clk = "gpio3_dbclk" },
 672 };
 673
 674 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 675         .name           = "gpio3",
 676         .class          = &omap54xx_gpio_hwmod_class,
 677         .clkdm_name     = "l4per_clkdm",
 678         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 679         .main_clk       = "l4_root_clk_div",
 680         .prcm = {
 681                 .omap4 = {
 682                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 683                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 684                         .modulemode   = MODULEMODE_HWCTRL,
 685                 },
 686         },
 687         .opt_clks       = gpio3_opt_clks,
 688         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 689 };
 690
 691 /* gpio4 */
 692 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 693         { .role = "dbclk", .clk = "gpio4_dbclk" },
 694 };
 695
 696 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 697         .name           = "gpio4",
 698         .class          = &omap54xx_gpio_hwmod_class,
 699         .clkdm_name     = "l4per_clkdm",
 700         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 701         .main_clk       = "l4_root_clk_div",
 702         .prcm = {
 703                 .omap4 = {
 704                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 705                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 706                         .modulemode   = MODULEMODE_HWCTRL,
 707                 },
 708         },
 709         .opt_clks       = gpio4_opt_clks,
 710         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 711 };
 712
 713 /* gpio5 */
 714 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 715         { .role = "dbclk", .clk = "gpio5_dbclk" },
 716 };
 717
 718 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 719         .name           = "gpio5",
 720         .class          = &omap54xx_gpio_hwmod_class,
 721         .clkdm_name     = "l4per_clkdm",
 722         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 723         .main_clk       = "l4_root_clk_div",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 728                         .modulemode   = MODULEMODE_HWCTRL,
 729                 },
 730         },
 731         .opt_clks       = gpio5_opt_clks,
 732         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 733 };
 734
 735 /* gpio6 */
 736 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 737         { .role = "dbclk", .clk = "gpio6_dbclk" },
 738 };
 739
 740 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 741         .name           = "gpio6",
 742         .class          = &omap54xx_gpio_hwmod_class,
 743         .clkdm_name     = "l4per_clkdm",
 744         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 745         .main_clk       = "l4_root_clk_div",
 746         .prcm = {
 747                 .omap4 = {
 748                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 749                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 750                         .modulemode   = MODULEMODE_HWCTRL,
 751                 },
 752         },
 753         .opt_clks       = gpio6_opt_clks,
 754         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 755 };
 756
 757 /* gpio7 */
 758 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 759         { .role = "dbclk", .clk = "gpio7_dbclk" },
 760 };
 761
 762 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 763         .name           = "gpio7",
 764         .class          = &omap54xx_gpio_hwmod_class,
 765         .clkdm_name     = "l4per_clkdm",
 766         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 767         .main_clk       = "l4_root_clk_div",
 768         .prcm = {
 769                 .omap4 = {
 770                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 771                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 772                         .modulemode   = MODULEMODE_HWCTRL,
 773                 },
 774         },
 775         .opt_clks       = gpio7_opt_clks,
 776         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 777 };
 778
 779 /* gpio8 */
 780 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 781         { .role = "dbclk", .clk = "gpio8_dbclk" },
 782 };
 783
 784 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 785         .name           = "gpio8",
 786         .class          = &omap54xx_gpio_hwmod_class,
 787         .clkdm_name     = "l4per_clkdm",
 788         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 789         .main_clk       = "l4_root_clk_div",
 790         .prcm = {
 791                 .omap4 = {
 792                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 793                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 794                         .modulemode   = MODULEMODE_HWCTRL,
 795                 },
 796         },
 797         .opt_clks       = gpio8_opt_clks,
 798         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 799 };
 800
 801 /*
 802  * 'i2c' class
 803  * multimaster high-speed i2c controller
 804  */
 805
 806 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 807         .rev_offs       = 0,
 808         .sysc_offs      = 0x0010,
 809         .syss_offs      = 0x0090,
 810         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 811                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 812                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 814                            SIDLE_SMART_WKUP),
 815         .sysc_fields    = &omap_hwmod_sysc_type1,
 816 };
 817
 818 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 819         .name   = "i2c",
 820         .sysc   = &omap54xx_i2c_sysc,
 821         .reset  = &omap_i2c_reset,
 822         .rev    = OMAP_I2C_IP_VERSION_2,
 823 };
 824
 825 /* i2c1 */
 826 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 827         .name           = "i2c1",
 828         .class          = &omap54xx_i2c_hwmod_class,
 829         .clkdm_name     = "l4per_clkdm",
 830         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 831         .main_clk       = "func_96m_fclk",
 832         .prcm = {
 833                 .omap4 = {
 834                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 835                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 836                         .modulemode   = MODULEMODE_SWCTRL,
 837                 },
 838         },
 839 };
 840
 841 /* i2c2 */
 842 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 843         .name           = "i2c2",
 844         .class          = &omap54xx_i2c_hwmod_class,
 845         .clkdm_name     = "l4per_clkdm",
 846         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 847         .main_clk       = "func_96m_fclk",
 848         .prcm = {
 849                 .omap4 = {
 850                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 851                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 852                         .modulemode   = MODULEMODE_SWCTRL,
 853                 },
 854         },
 855 };
 856
 857 /* i2c3 */
 858 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 859         .name           = "i2c3",
 860         .class          = &omap54xx_i2c_hwmod_class,
 861         .clkdm_name     = "l4per_clkdm",
 862         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 863         .main_clk       = "func_96m_fclk",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 867                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 868                         .modulemode   = MODULEMODE_SWCTRL,
 869                 },
 870         },
 871 };
 872
 873 /* i2c4 */
 874 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 875         .name           = "i2c4",
 876         .class          = &omap54xx_i2c_hwmod_class,
 877         .clkdm_name     = "l4per_clkdm",
 878         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 879         .main_clk       = "func_96m_fclk",
 880         .prcm = {
 881                 .omap4 = {
 882                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 883                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 884                         .modulemode   = MODULEMODE_SWCTRL,
 885                 },
 886         },
 887 };
 888
 889 /* i2c5 */
 890 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 891         .name           = "i2c5",
 892         .class          = &omap54xx_i2c_hwmod_class,
 893         .clkdm_name     = "l4per_clkdm",
 894         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 895         .main_clk       = "func_96m_fclk",
 896         .prcm = {
 897                 .omap4 = {
 898                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 899                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 900                         .modulemode   = MODULEMODE_SWCTRL,
 901                 },
 902         },
 903 };
 904
 905 /*
 906  * 'kbd' class
 907  * keyboard controller
 908  */
 909
 910 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 911         .rev_offs       = 0x0000,
 912         .sysc_offs      = 0x0010,
 913         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 920         .name   = "kbd",
 921         .sysc   = &omap54xx_kbd_sysc,
 922 };
 923
 924 /* kbd */
 925 static struct omap_hwmod omap54xx_kbd_hwmod = {
 926         .name           = "kbd",
 927         .class          = &omap54xx_kbd_hwmod_class,
 928         .clkdm_name     = "wkupaon_clkdm",
 929         .main_clk       = "sys_32k_ck",
 930         .prcm = {
 931                 .omap4 = {
 932                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 933                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 934                         .modulemode   = MODULEMODE_SWCTRL,
 935                 },
 936         },
 937 };
 938
 939 /*
 940  * 'mailbox' class
 941  * mailbox module allowing communication between the on-chip processors using a
 942  * queued mailbox-interrupt mechanism.
 943  */
 944
 945 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 946         .rev_offs       = 0x0000,
 947         .sysc_offs      = 0x0010,
 948         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 949                            SYSC_HAS_SOFTRESET),
 950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 951         .sysc_fields    = &omap_hwmod_sysc_type2,
 952 };
 953
 954 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 955         .name   = "mailbox",
 956         .sysc   = &omap54xx_mailbox_sysc,
 957 };
 958
 959 /* mailbox */
 960 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 961         .name           = "mailbox",
 962         .class          = &omap54xx_mailbox_hwmod_class,
 963         .clkdm_name     = "l4cfg_clkdm",
 964         .prcm = {
 965                 .omap4 = {
 966                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
 967                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
 968                 },
 969         },
 970 };
 971
 972 /*
 973  * 'mcbsp' class
 974  * multi channel buffered serial port controller
 975  */
 976
 977 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
 978         .rev_offs       = -ENODEV,
 979         .sysc_offs      = 0x008c,
 980         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 981                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type1,
 984 };
 985
 986 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
 987         .name   = "mcbsp",
 988         .sysc   = &omap54xx_mcbsp_sysc,
 989 };
 990
 991 /* mcbsp1 */
 992 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
 993         { .role = "pad_fck", .clk = "pad_clks_ck" },
 994         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
 995 };
 996
 997 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
 998         .name           = "mcbsp1",
 999         .class          = &omap54xx_mcbsp_hwmod_class,
1000         .clkdm_name     = "abe_clkdm",
1001         .main_clk       = "mcbsp1_gfclk",
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1005                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1006                         .modulemode   = MODULEMODE_SWCTRL,
1007                 },
1008         },
1009         .opt_clks       = mcbsp1_opt_clks,
1010         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1011 };
1012
1013 /* mcbsp2 */
1014 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1015         { .role = "pad_fck", .clk = "pad_clks_ck" },
1016         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1017 };
1018
1019 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1020         .name           = "mcbsp2",
1021         .class          = &omap54xx_mcbsp_hwmod_class,
1022         .clkdm_name     = "abe_clkdm",
1023         .main_clk       = "mcbsp2_gfclk",
1024         .prcm = {
1025                 .omap4 = {
1026                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1027                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1028                         .modulemode   = MODULEMODE_SWCTRL,
1029                 },
1030         },
1031         .opt_clks       = mcbsp2_opt_clks,
1032         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1033 };
1034
1035 /* mcbsp3 */
1036 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1037         { .role = "pad_fck", .clk = "pad_clks_ck" },
1038         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1039 };
1040
1041 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1042         .name           = "mcbsp3",
1043         .class          = &omap54xx_mcbsp_hwmod_class,
1044         .clkdm_name     = "abe_clkdm",
1045         .main_clk       = "mcbsp3_gfclk",
1046         .prcm = {
1047                 .omap4 = {
1048                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1049                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1050                         .modulemode   = MODULEMODE_SWCTRL,
1051                 },
1052         },
1053         .opt_clks       = mcbsp3_opt_clks,
1054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1055 };
1056
1057 /*
1058  * 'mcpdm' class
1059  * multi channel pdm controller (proprietary interface with phoenix power
1060  * ic)
1061  */
1062
1063 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1064         .rev_offs       = 0x0000,
1065         .sysc_offs      = 0x0010,
1066         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1067                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1069                            SIDLE_SMART_WKUP),
1070         .sysc_fields    = &omap_hwmod_sysc_type2,
1071 };
1072
1073 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1074         .name   = "mcpdm",
1075         .sysc   = &omap54xx_mcpdm_sysc,
1076 };
1077
1078 /* mcpdm */
1079 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1080         .name           = "mcpdm",
1081         .class          = &omap54xx_mcpdm_hwmod_class,
1082         .clkdm_name     = "abe_clkdm",
1083         /*
1084          * It's suspected that the McPDM requires an off-chip main
1085          * functional clock, controlled via I2C.  This IP block is
1086          * currently reset very early during boot, before I2C is
1087          * available, so it doesn't seem that we have any choice in
1088          * the kernel other than to avoid resetting it.  XXX This is
1089          * really a hardware issue workaround: every IP block should
1090          * be able to source its main functional clock from either
1091          * on-chip or off-chip sources.  McPDM seems to be the only
1092          * current exception.
1093          */
1094
1095         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1096         .main_clk       = "pad_clks_ck",
1097         .prcm = {
1098                 .omap4 = {
1099                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1100                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1101                         .modulemode   = MODULEMODE_SWCTRL,
1102                 },
1103         },
1104 };
1105
1106 /*
1107  * 'mcspi' class
1108  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1109  * bus
1110  */
1111
1112 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1113         .rev_offs       = 0x0000,
1114         .sysc_offs      = 0x0010,
1115         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1116                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1117         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1118                            SIDLE_SMART_WKUP),
1119         .sysc_fields    = &omap_hwmod_sysc_type2,
1120 };
1121
1122 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1123         .name   = "mcspi",
1124         .sysc   = &omap54xx_mcspi_sysc,
1125 };
1126
1127 /* mcspi1 */
1128 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1129         .name           = "mcspi1",
1130         .class          = &omap54xx_mcspi_hwmod_class,
1131         .clkdm_name     = "l4per_clkdm",
1132         .main_clk       = "func_48m_fclk",
1133         .prcm = {
1134                 .omap4 = {
1135                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1136                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1137                         .modulemode   = MODULEMODE_SWCTRL,
1138                 },
1139         },
1140 };
1141
1142 /* mcspi2 */
1143 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1144         .name           = "mcspi2",
1145         .class          = &omap54xx_mcspi_hwmod_class,
1146         .clkdm_name     = "l4per_clkdm",
1147         .main_clk       = "func_48m_fclk",
1148         .prcm = {
1149                 .omap4 = {
1150                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1151                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1152                         .modulemode   = MODULEMODE_SWCTRL,
1153                 },
1154         },
1155 };
1156
1157 /* mcspi3 */
1158 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1159         .name           = "mcspi3",
1160         .class          = &omap54xx_mcspi_hwmod_class,
1161         .clkdm_name     = "l4per_clkdm",
1162         .main_clk       = "func_48m_fclk",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1166                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_SWCTRL,
1168                 },
1169         },
1170 };
1171
1172 /* mcspi4 */
1173 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1174         .name           = "mcspi4",
1175         .class          = &omap54xx_mcspi_hwmod_class,
1176         .clkdm_name     = "l4per_clkdm",
1177         .main_clk       = "func_48m_fclk",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1181                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1182                         .modulemode   = MODULEMODE_SWCTRL,
1183                 },
1184         },
1185 };
1186
1187 /*
1188  * 'mmc' class
1189  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1190  */
1191
1192 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1193         .rev_offs       = 0x0000,
1194         .sysc_offs      = 0x0010,
1195         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1196                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1197                            SYSC_HAS_SOFTRESET),
1198         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1199                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1200                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1201         .sysc_fields    = &omap_hwmod_sysc_type2,
1202 };
1203
1204 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1205         .name   = "mmc",
1206         .sysc   = &omap54xx_mmc_sysc,
1207 };
1208
1209 /* mmc1 */
1210 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1211         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1212 };
1213
1214 /* mmc1 dev_attr */
1215 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1216         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1217 };
1218
1219 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1220         .name           = "mmc1",
1221         .class          = &omap54xx_mmc_hwmod_class,
1222         .clkdm_name     = "l3init_clkdm",
1223         .main_clk       = "mmc1_fclk",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_SWCTRL,
1229                 },
1230         },
1231         .opt_clks       = mmc1_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1233         .dev_attr       = &mmc1_dev_attr,
1234 };
1235
1236 /* mmc2 */
1237 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1238         .name           = "mmc2",
1239         .class          = &omap54xx_mmc_hwmod_class,
1240         .clkdm_name     = "l3init_clkdm",
1241         .main_clk       = "mmc2_fclk",
1242         .prcm = {
1243                 .omap4 = {
1244                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1245                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1246                         .modulemode   = MODULEMODE_SWCTRL,
1247                 },
1248         },
1249 };
1250
1251 /* mmc3 */
1252 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1253         .name           = "mmc3",
1254         .class          = &omap54xx_mmc_hwmod_class,
1255         .clkdm_name     = "l4per_clkdm",
1256         .main_clk       = "func_48m_fclk",
1257         .prcm = {
1258                 .omap4 = {
1259                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1260                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1261                         .modulemode   = MODULEMODE_SWCTRL,
1262                 },
1263         },
1264 };
1265
1266 /* mmc4 */
1267 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1268         .name           = "mmc4",
1269         .class          = &omap54xx_mmc_hwmod_class,
1270         .clkdm_name     = "l4per_clkdm",
1271         .main_clk       = "func_48m_fclk",
1272         .prcm = {
1273                 .omap4 = {
1274                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1275                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1276                         .modulemode   = MODULEMODE_SWCTRL,
1277                 },
1278         },
1279 };
1280
1281 /* mmc5 */
1282 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1283         .name           = "mmc5",
1284         .class          = &omap54xx_mmc_hwmod_class,
1285         .clkdm_name     = "l4per_clkdm",
1286         .main_clk       = "func_96m_fclk",
1287         .prcm = {
1288                 .omap4 = {
1289                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1290                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1291                         .modulemode   = MODULEMODE_SWCTRL,
1292                 },
1293         },
1294 };
1295
1296 /*
1297  * 'mmu' class
1298  * The memory management unit performs virtual to physical address translation
1299  * for its requestors.
1300  */
1301
1302 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1303         .rev_offs       = 0x0000,
1304         .sysc_offs      = 0x0010,
1305         .syss_offs      = 0x0014,
1306         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1307                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1308                            SYSS_HAS_RESET_STATUS),
1309         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1310         .sysc_fields    = &omap_hwmod_sysc_type1,
1311 };
1312
1313 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1314         .name = "mmu",
1315         .sysc = &omap54xx_mmu_sysc,
1316 };
1317
1318 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1319         { .name = "mmu_cache", .rst_shift = 1 },
1320 };
1321
1322 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1323         .name           = "mmu_dsp",
1324         .class          = &omap54xx_mmu_hwmod_class,
1325         .clkdm_name     = "dsp_clkdm",
1326         .rst_lines      = omap54xx_mmu_dsp_resets,
1327         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1328         .main_clk       = "dpll_iva_h11x2_ck",
1329         .prcm = {
1330                 .omap4 = {
1331                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1332                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1333                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1334                         .modulemode   = MODULEMODE_HWCTRL,
1335                 },
1336         },
1337 };
1338
1339 /* mmu ipu */
1340 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1341         { .name = "mmu_cache", .rst_shift = 2 },
1342 };
1343
1344 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1345         .name           = "mmu_ipu",
1346         .class          = &omap54xx_mmu_hwmod_class,
1347         .clkdm_name     = "ipu_clkdm",
1348         .rst_lines      = omap54xx_mmu_ipu_resets,
1349         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1350         .main_clk       = "dpll_core_h22x2_ck",
1351         .prcm = {
1352                 .omap4 = {
1353                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1354                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1355                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1356                         .modulemode   = MODULEMODE_HWCTRL,
1357                 },
1358         },
1359 };
1360
1361 /*
1362  * 'mpu' class
1363  * mpu sub-system
1364  */
1365
1366 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1367         .name   = "mpu",
1368 };
1369
1370 /* mpu */
1371 static struct omap_hwmod omap54xx_mpu_hwmod = {
1372         .name           = "mpu",
1373         .class          = &omap54xx_mpu_hwmod_class,
1374         .clkdm_name     = "mpu_clkdm",
1375         .flags          = HWMOD_INIT_NO_IDLE,
1376         .main_clk       = "dpll_mpu_m2_ck",
1377         .prcm = {
1378                 .omap4 = {
1379                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1380                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1381                 },
1382         },
1383 };
1384
1385 /*
1386  * 'spinlock' class
1387  * spinlock provides hardware assistance for synchronizing the processes
1388  * running on multiple processors
1389  */
1390
1391 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1392         .rev_offs       = 0x0000,
1393         .sysc_offs      = 0x0010,
1394         .syss_offs      = 0x0014,
1395         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1396                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1397                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1398         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1399         .sysc_fields    = &omap_hwmod_sysc_type1,
1400 };
1401
1402 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1403         .name   = "spinlock",
1404         .sysc   = &omap54xx_spinlock_sysc,
1405 };
1406
1407 /* spinlock */
1408 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1409         .name           = "spinlock",
1410         .class          = &omap54xx_spinlock_hwmod_class,
1411         .clkdm_name     = "l4cfg_clkdm",
1412         .prcm = {
1413                 .omap4 = {
1414                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1415                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1416                 },
1417         },
1418 };
1419
1420 /*
1421  * 'ocp2scp' class
1422  * bridge to transform ocp interface protocol to scp (serial control port)
1423  * protocol
1424  */
1425
1426 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1427         .rev_offs       = 0x0000,
1428         .sysc_offs      = 0x0010,
1429         .syss_offs      = 0x0014,
1430         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1431                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1432         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1433         .sysc_fields    = &omap_hwmod_sysc_type1,
1434 };
1435
1436 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1437         .name   = "ocp2scp",
1438         .sysc   = &omap54xx_ocp2scp_sysc,
1439 };
1440
1441 /* ocp2scp1 */
1442 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1443         .name           = "ocp2scp1",
1444         .class          = &omap54xx_ocp2scp_hwmod_class,
1445         .clkdm_name     = "l3init_clkdm",
1446         .main_clk       = "l4_root_clk_div",
1447         .prcm = {
1448                 .omap4 = {
1449                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1450                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1451                         .modulemode   = MODULEMODE_HWCTRL,
1452                 },
1453         },
1454 };
1455
1456 /*
1457  * 'timer' class
1458  * general purpose timer module with accurate 1ms tick
1459  * This class contains several variants: ['timer_1ms', 'timer']
1460  */
1461
1462 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1463         .rev_offs       = 0x0000,
1464         .sysc_offs      = 0x0010,
1465         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1466                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1467         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1468                            SIDLE_SMART_WKUP),
1469         .sysc_fields    = &omap_hwmod_sysc_type2,
1470 };
1471
1472 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1473         .name   = "timer",
1474         .sysc   = &omap54xx_timer_1ms_sysc,
1475 };
1476
1477 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1478         .rev_offs       = 0x0000,
1479         .sysc_offs      = 0x0010,
1480         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1481                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1482         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1483                            SIDLE_SMART_WKUP),
1484         .sysc_fields    = &omap_hwmod_sysc_type2,
1485 };
1486
1487 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1488         .name   = "timer",
1489         .sysc   = &omap54xx_timer_sysc,
1490 };
1491
1492 /* timer1 */
1493 static struct omap_hwmod omap54xx_timer1_hwmod = {
1494         .name           = "timer1",
1495         .class          = &omap54xx_timer_1ms_hwmod_class,
1496         .clkdm_name     = "wkupaon_clkdm",
1497         .main_clk       = "timer1_gfclk_mux",
1498         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1499         .prcm = {
1500                 .omap4 = {
1501                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1502                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1503                         .modulemode   = MODULEMODE_SWCTRL,
1504                 },
1505         },
1506 };
1507
1508 /* timer2 */
1509 static struct omap_hwmod omap54xx_timer2_hwmod = {
1510         .name           = "timer2",
1511         .class          = &omap54xx_timer_1ms_hwmod_class,
1512         .clkdm_name     = "l4per_clkdm",
1513         .main_clk       = "timer2_gfclk_mux",
1514         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1515         .prcm = {
1516                 .omap4 = {
1517                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1518                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1519                         .modulemode   = MODULEMODE_SWCTRL,
1520                 },
1521         },
1522 };
1523
1524 /* timer3 */
1525 static struct omap_hwmod omap54xx_timer3_hwmod = {
1526         .name           = "timer3",
1527         .class          = &omap54xx_timer_hwmod_class,
1528         .clkdm_name     = "l4per_clkdm",
1529         .main_clk       = "timer3_gfclk_mux",
1530         .prcm = {
1531                 .omap4 = {
1532                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1533                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1534                         .modulemode   = MODULEMODE_SWCTRL,
1535                 },
1536         },
1537 };
1538
1539 /* timer4 */
1540 static struct omap_hwmod omap54xx_timer4_hwmod = {
1541         .name           = "timer4",
1542         .class          = &omap54xx_timer_hwmod_class,
1543         .clkdm_name     = "l4per_clkdm",
1544         .main_clk       = "timer4_gfclk_mux",
1545         .prcm = {
1546                 .omap4 = {
1547                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1548                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1549                         .modulemode   = MODULEMODE_SWCTRL,
1550                 },
1551         },
1552 };
1553
1554 /* timer5 */
1555 static struct omap_hwmod omap54xx_timer5_hwmod = {
1556         .name           = "timer5",
1557         .class          = &omap54xx_timer_hwmod_class,
1558         .clkdm_name     = "abe_clkdm",
1559         .main_clk       = "timer5_gfclk_mux",
1560         .prcm = {
1561                 .omap4 = {
1562                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1563                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1564                         .modulemode   = MODULEMODE_SWCTRL,
1565                 },
1566         },
1567 };
1568
1569 /* timer6 */
1570 static struct omap_hwmod omap54xx_timer6_hwmod = {
1571         .name           = "timer6",
1572         .class          = &omap54xx_timer_hwmod_class,
1573         .clkdm_name     = "abe_clkdm",
1574         .main_clk       = "timer6_gfclk_mux",
1575         .prcm = {
1576                 .omap4 = {
1577                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1578                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1579                         .modulemode   = MODULEMODE_SWCTRL,
1580                 },
1581         },
1582 };
1583
1584 /* timer7 */
1585 static struct omap_hwmod omap54xx_timer7_hwmod = {
1586         .name           = "timer7",
1587         .class          = &omap54xx_timer_hwmod_class,
1588         .clkdm_name     = "abe_clkdm",
1589         .main_clk       = "timer7_gfclk_mux",
1590         .prcm = {
1591                 .omap4 = {
1592                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1593                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1594                         .modulemode   = MODULEMODE_SWCTRL,
1595                 },
1596         },
1597 };
1598
1599 /* timer8 */
1600 static struct omap_hwmod omap54xx_timer8_hwmod = {
1601         .name           = "timer8",
1602         .class          = &omap54xx_timer_hwmod_class,
1603         .clkdm_name     = "abe_clkdm",
1604         .main_clk       = "timer8_gfclk_mux",
1605         .prcm = {
1606                 .omap4 = {
1607                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1608                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1609                         .modulemode   = MODULEMODE_SWCTRL,
1610                 },
1611         },
1612 };
1613
1614 /* timer9 */
1615 static struct omap_hwmod omap54xx_timer9_hwmod = {
1616         .name           = "timer9",
1617         .class          = &omap54xx_timer_hwmod_class,
1618         .clkdm_name     = "l4per_clkdm",
1619         .main_clk       = "timer9_gfclk_mux",
1620         .prcm = {
1621                 .omap4 = {
1622                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1623                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1624                         .modulemode   = MODULEMODE_SWCTRL,
1625                 },
1626         },
1627 };
1628
1629 /* timer10 */
1630 static struct omap_hwmod omap54xx_timer10_hwmod = {
1631         .name           = "timer10",
1632         .class          = &omap54xx_timer_1ms_hwmod_class,
1633         .clkdm_name     = "l4per_clkdm",
1634         .main_clk       = "timer10_gfclk_mux",
1635         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1636         .prcm = {
1637                 .omap4 = {
1638                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1639                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1640                         .modulemode   = MODULEMODE_SWCTRL,
1641                 },
1642         },
1643 };
1644
1645 /* timer11 */
1646 static struct omap_hwmod omap54xx_timer11_hwmod = {
1647         .name           = "timer11",
1648         .class          = &omap54xx_timer_hwmod_class,
1649         .clkdm_name     = "l4per_clkdm",
1650         .main_clk       = "timer11_gfclk_mux",
1651         .prcm = {
1652                 .omap4 = {
1653                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1654                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1655                         .modulemode   = MODULEMODE_SWCTRL,
1656                 },
1657         },
1658 };
1659
1660 /*
1661  * 'uart' class
1662  * universal asynchronous receiver/transmitter (uart)
1663  */
1664
1665 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1666         .rev_offs       = 0x0050,
1667         .sysc_offs      = 0x0054,
1668         .syss_offs      = 0x0058,
1669         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1670                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1671                            SYSS_HAS_RESET_STATUS),
1672         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673                            SIDLE_SMART_WKUP),
1674         .sysc_fields    = &omap_hwmod_sysc_type1,
1675 };
1676
1677 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1678         .name   = "uart",
1679         .sysc   = &omap54xx_uart_sysc,
1680 };
1681
1682 /* uart1 */
1683 static struct omap_hwmod omap54xx_uart1_hwmod = {
1684         .name           = "uart1",
1685         .class          = &omap54xx_uart_hwmod_class,
1686         .clkdm_name     = "l4per_clkdm",
1687         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1688         .main_clk       = "func_48m_fclk",
1689         .prcm = {
1690                 .omap4 = {
1691                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1692                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1693                         .modulemode   = MODULEMODE_SWCTRL,
1694                 },
1695         },
1696 };
1697
1698 /* uart2 */
1699 static struct omap_hwmod omap54xx_uart2_hwmod = {
1700         .name           = "uart2",
1701         .class          = &omap54xx_uart_hwmod_class,
1702         .clkdm_name     = "l4per_clkdm",
1703         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1704         .main_clk       = "func_48m_fclk",
1705         .prcm = {
1706                 .omap4 = {
1707                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1708                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1709                         .modulemode   = MODULEMODE_SWCTRL,
1710                 },
1711         },
1712 };
1713
1714 /* uart3 */
1715 static struct omap_hwmod omap54xx_uart3_hwmod = {
1716         .name           = "uart3",
1717         .class          = &omap54xx_uart_hwmod_class,
1718         .clkdm_name     = "l4per_clkdm",
1719         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1720         .main_clk       = "func_48m_fclk",
1721         .prcm = {
1722                 .omap4 = {
1723                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1724                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1725                         .modulemode   = MODULEMODE_SWCTRL,
1726                 },
1727         },
1728 };
1729
1730 /* uart4 */
1731 static struct omap_hwmod omap54xx_uart4_hwmod = {
1732         .name           = "uart4",
1733         .class          = &omap54xx_uart_hwmod_class,
1734         .clkdm_name     = "l4per_clkdm",
1735         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1736         .main_clk       = "func_48m_fclk",
1737         .prcm = {
1738                 .omap4 = {
1739                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1740                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1741                         .modulemode   = MODULEMODE_SWCTRL,
1742                 },
1743         },
1744 };
1745
1746 /* uart5 */
1747 static struct omap_hwmod omap54xx_uart5_hwmod = {
1748         .name           = "uart5",
1749         .class          = &omap54xx_uart_hwmod_class,
1750         .clkdm_name     = "l4per_clkdm",
1751         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1752         .main_clk       = "func_48m_fclk",
1753         .prcm = {
1754                 .omap4 = {
1755                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1756                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1757                         .modulemode   = MODULEMODE_SWCTRL,
1758                 },
1759         },
1760 };
1761
1762 /* uart6 */
1763 static struct omap_hwmod omap54xx_uart6_hwmod = {
1764         .name           = "uart6",
1765         .class          = &omap54xx_uart_hwmod_class,
1766         .clkdm_name     = "l4per_clkdm",
1767         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1768         .main_clk       = "func_48m_fclk",
1769         .prcm = {
1770                 .omap4 = {
1771                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1772                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1773                         .modulemode   = MODULEMODE_SWCTRL,
1774                 },
1775         },
1776 };
1777
1778 /*
1779  * 'usb_host_hs' class
1780  * high-speed multi-port usb host controller
1781  */
1782
1783 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1784         .rev_offs       = 0x0000,
1785         .sysc_offs      = 0x0010,
1786         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1787                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1788         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1789                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1790                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1791         .sysc_fields    = &omap_hwmod_sysc_type2,
1792 };
1793
1794 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1795         .name   = "usb_host_hs",
1796         .sysc   = &omap54xx_usb_host_hs_sysc,
1797 };
1798
1799 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1800         .name           = "usb_host_hs",
1801         .class          = &omap54xx_usb_host_hs_hwmod_class,
1802         .clkdm_name     = "l3init_clkdm",
1803         /*
1804          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1805          * id: i660
1806          *
1807          * Description:
1808          * In the following configuration :
1809          * - USBHOST module is set to smart-idle mode
1810          * - PRCM asserts idle_req to the USBHOST module ( This typically
1811          *   happens when the system is going to a low power mode : all ports
1812          *   have been suspended, the master part of the USBHOST module has
1813          *   entered the standby state, and SW has cut the functional clocks)
1814          * - an USBHOST interrupt occurs before the module is able to answer
1815          *   idle_ack, typically a remote wakeup IRQ.
1816          * Then the USB HOST module will enter a deadlock situation where it
1817          * is no more accessible nor functional.
1818          *
1819          * Workaround:
1820          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1821          */
1822
1823         /*
1824          * Errata: USB host EHCI may stall when entering smart-standby mode
1825          * Id: i571
1826          *
1827          * Description:
1828          * When the USBHOST module is set to smart-standby mode, and when it is
1829          * ready to enter the standby state (i.e. all ports are suspended and
1830          * all attached devices are in suspend mode), then it can wrongly assert
1831          * the Mstandby signal too early while there are still some residual OCP
1832          * transactions ongoing. If this condition occurs, the internal state
1833          * machine may go to an undefined state and the USB link may be stuck
1834          * upon the next resume.
1835          *
1836          * Workaround:
1837          * Don't use smart standby; use only force standby,
1838          * hence HWMOD_SWSUP_MSTANDBY
1839          */
1840
1841         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1842         .main_clk       = "l3init_60m_fclk",
1843         .prcm = {
1844                 .omap4 = {
1845                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1846                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1847                         .modulemode   = MODULEMODE_SWCTRL,
1848                 },
1849         },
1850 };
1851
1852 /*
1853  * 'usb_tll_hs' class
1854  * usb_tll_hs module is the adapter on the usb_host_hs ports
1855  */
1856
1857 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1858         .rev_offs       = 0x0000,
1859         .sysc_offs      = 0x0010,
1860         .syss_offs      = 0x0014,
1861         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1862                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1863                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1864         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1865         .sysc_fields    = &omap_hwmod_sysc_type1,
1866 };
1867
1868 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1869         .name   = "usb_tll_hs",
1870         .sysc   = &omap54xx_usb_tll_hs_sysc,
1871 };
1872
1873 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1874         .name           = "usb_tll_hs",
1875         .class          = &omap54xx_usb_tll_hs_hwmod_class,
1876         .clkdm_name     = "l3init_clkdm",
1877         .main_clk       = "l4_root_clk_div",
1878         .prcm = {
1879                 .omap4 = {
1880                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1881                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1882                         .modulemode   = MODULEMODE_HWCTRL,
1883                 },
1884         },
1885 };
1886
1887 /*
1888  * 'usb_otg_ss' class
1889  * 2.0 super speed (usb_otg_ss) controller
1890  */
1891
1892 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1893         .rev_offs       = 0x0000,
1894         .sysc_offs      = 0x0010,
1895         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1896                            SYSC_HAS_SIDLEMODE),
1897         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1898                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1899                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1900         .sysc_fields    = &omap_hwmod_sysc_type2,
1901 };
1902
1903 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1904         .name   = "usb_otg_ss",
1905         .sysc   = &omap54xx_usb_otg_ss_sysc,
1906 };
1907
1908 /* usb_otg_ss */
1909 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1910         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1911 };
1912
1913 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1914         .name           = "usb_otg_ss",
1915         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1916         .clkdm_name     = "l3init_clkdm",
1917         .flags          = HWMOD_SWSUP_SIDLE,
1918         .main_clk       = "dpll_core_h13x2_ck",
1919         .prcm = {
1920                 .omap4 = {
1921                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1922                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1923                         .modulemode   = MODULEMODE_HWCTRL,
1924                 },
1925         },
1926         .opt_clks       = usb_otg_ss_opt_clks,
1927         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1928 };
1929
1930 /*
1931  * 'wd_timer' class
1932  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1933  * overflow condition
1934  */
1935
1936 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1937         .rev_offs       = 0x0000,
1938         .sysc_offs      = 0x0010,
1939         .syss_offs      = 0x0014,
1940         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1941                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1943                            SIDLE_SMART_WKUP),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1948         .name           = "wd_timer",
1949         .sysc           = &omap54xx_wd_timer_sysc,
1950         .pre_shutdown   = &omap2_wd_timer_disable,
1951 };
1952
1953 /* wd_timer2 */
1954 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1955         .name           = "wd_timer2",
1956         .class          = &omap54xx_wd_timer_hwmod_class,
1957         .clkdm_name     = "wkupaon_clkdm",
1958         .main_clk       = "sys_32k_ck",
1959         .prcm = {
1960                 .omap4 = {
1961                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1962                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1963                         .modulemode   = MODULEMODE_SWCTRL,
1964                 },
1965         },
1966 };
1967
1968 /*
1969  * 'ocp2scp' class
1970  * bridge to transform ocp interface protocol to scp (serial control port)
1971  * protocol
1972  */
1973 /* ocp2scp3 */
1974 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
1975 /* l4_cfg -> ocp2scp3 */
1976 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
1977         .master         = &omap54xx_l4_cfg_hwmod,
1978         .slave          = &omap54xx_ocp2scp3_hwmod,
1979         .clk            = "l4_root_clk_div",
1980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1981 };
1982
1983 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
1984         .name           = "ocp2scp3",
1985         .class          = &omap54xx_ocp2scp_hwmod_class,
1986         .clkdm_name     = "l3init_clkdm",
1987         .prcm = {
1988                 .omap4 = {
1989                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1990                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1991                         .modulemode   = MODULEMODE_HWCTRL,
1992                 },
1993         },
1994 };
1995
1996 /*
1997  * 'sata' class
1998  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
1999  */
2000
2001 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2002         .rev_offs       = 0x00fc,
2003         .sysc_offs      = 0x0000,
2004         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2005         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2006                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2007                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2008         .sysc_fields    = &omap_hwmod_sysc_type2,
2009 };
2010
2011 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2012         .name   = "sata",
2013         .sysc   = &omap54xx_sata_sysc,
2014 };
2015
2016 /* sata */
2017 static struct omap_hwmod omap54xx_sata_hwmod = {
2018         .name           = "sata",
2019         .class          = &omap54xx_sata_hwmod_class,
2020         .clkdm_name     = "l3init_clkdm",
2021         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2022         .main_clk       = "func_48m_fclk",
2023         .mpu_rt_idx     = 1,
2024         .prcm = {
2025                 .omap4 = {
2026                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2027                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2028                         .modulemode   = MODULEMODE_SWCTRL,
2029                 },
2030         },
2031 };
2032
2033 /* l4_cfg -> sata */
2034 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2035         .master         = &omap54xx_l4_cfg_hwmod,
2036         .slave          = &omap54xx_sata_hwmod,
2037         .clk            = "l3_iclk_div",
2038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2039 };
2040
2041 /*
2042  * Interfaces
2043  */
2044
2045 /* l3_main_1 -> dmm */
2046 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2047         .master         = &omap54xx_l3_main_1_hwmod,
2048         .slave          = &omap54xx_dmm_hwmod,
2049         .clk            = "l3_iclk_div",
2050         .user           = OCP_USER_SDMA,
2051 };
2052
2053 /* l3_main_3 -> l3_instr */
2054 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2055         .master         = &omap54xx_l3_main_3_hwmod,
2056         .slave          = &omap54xx_l3_instr_hwmod,
2057         .clk            = "l3_iclk_div",
2058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2059 };
2060
2061 /* l3_main_2 -> l3_main_1 */
2062 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2063         .master         = &omap54xx_l3_main_2_hwmod,
2064         .slave          = &omap54xx_l3_main_1_hwmod,
2065         .clk            = "l3_iclk_div",
2066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2067 };
2068
2069 /* l4_cfg -> l3_main_1 */
2070 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2071         .master         = &omap54xx_l4_cfg_hwmod,
2072         .slave          = &omap54xx_l3_main_1_hwmod,
2073         .clk            = "l3_iclk_div",
2074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2075 };
2076
2077 /* l4_cfg -> mmu_dsp */
2078 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2079         .master         = &omap54xx_l4_cfg_hwmod,
2080         .slave          = &omap54xx_mmu_dsp_hwmod,
2081         .clk            = "l4_root_clk_div",
2082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2083 };
2084
2085 /* mpu -> l3_main_1 */
2086 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2087         .master         = &omap54xx_mpu_hwmod,
2088         .slave          = &omap54xx_l3_main_1_hwmod,
2089         .clk            = "l3_iclk_div",
2090         .user           = OCP_USER_MPU,
2091 };
2092
2093 /* l3_main_1 -> l3_main_2 */
2094 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2095         .master         = &omap54xx_l3_main_1_hwmod,
2096         .slave          = &omap54xx_l3_main_2_hwmod,
2097         .clk            = "l3_iclk_div",
2098         .user           = OCP_USER_MPU,
2099 };
2100
2101 /* l4_cfg -> l3_main_2 */
2102 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2103         .master         = &omap54xx_l4_cfg_hwmod,
2104         .slave          = &omap54xx_l3_main_2_hwmod,
2105         .clk            = "l3_iclk_div",
2106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2107 };
2108
2109 /* l3_main_2 -> mmu_ipu */
2110 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2111         .master         = &omap54xx_l3_main_2_hwmod,
2112         .slave          = &omap54xx_mmu_ipu_hwmod,
2113         .clk            = "l3_iclk_div",
2114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2115 };
2116
2117 /* l3_main_1 -> l3_main_3 */
2118 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2119         .master         = &omap54xx_l3_main_1_hwmod,
2120         .slave          = &omap54xx_l3_main_3_hwmod,
2121         .clk            = "l3_iclk_div",
2122         .user           = OCP_USER_MPU,
2123 };
2124
2125 /* l3_main_2 -> l3_main_3 */
2126 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2127         .master         = &omap54xx_l3_main_2_hwmod,
2128         .slave          = &omap54xx_l3_main_3_hwmod,
2129         .clk            = "l3_iclk_div",
2130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2131 };
2132
2133 /* l4_cfg -> l3_main_3 */
2134 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2135         .master         = &omap54xx_l4_cfg_hwmod,
2136         .slave          = &omap54xx_l3_main_3_hwmod,
2137         .clk            = "l3_iclk_div",
2138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2139 };
2140
2141 /* l3_main_1 -> l4_abe */
2142 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2143         .master         = &omap54xx_l3_main_1_hwmod,
2144         .slave          = &omap54xx_l4_abe_hwmod,
2145         .clk            = "abe_iclk",
2146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2147 };
2148
2149 /* mpu -> l4_abe */
2150 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2151         .master         = &omap54xx_mpu_hwmod,
2152         .slave          = &omap54xx_l4_abe_hwmod,
2153         .clk            = "abe_iclk",
2154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2155 };
2156
2157 /* l3_main_1 -> l4_cfg */
2158 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2159         .master         = &omap54xx_l3_main_1_hwmod,
2160         .slave          = &omap54xx_l4_cfg_hwmod,
2161         .clk            = "l4_root_clk_div",
2162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2163 };
2164
2165 /* l3_main_2 -> l4_per */
2166 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2167         .master         = &omap54xx_l3_main_2_hwmod,
2168         .slave          = &omap54xx_l4_per_hwmod,
2169         .clk            = "l4_root_clk_div",
2170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2171 };
2172
2173 /* l3_main_1 -> l4_wkup */
2174 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2175         .master         = &omap54xx_l3_main_1_hwmod,
2176         .slave          = &omap54xx_l4_wkup_hwmod,
2177         .clk            = "wkupaon_iclk_mux",
2178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2179 };
2180
2181 /* mpu -> mpu_private */
2182 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2183         .master         = &omap54xx_mpu_hwmod,
2184         .slave          = &omap54xx_mpu_private_hwmod,
2185         .clk            = "l3_iclk_div",
2186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2187 };
2188
2189 /* l4_wkup -> counter_32k */
2190 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2191         .master         = &omap54xx_l4_wkup_hwmod,
2192         .slave          = &omap54xx_counter_32k_hwmod,
2193         .clk            = "wkupaon_iclk_mux",
2194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196
2197 /* l4_cfg -> dma_system */
2198 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2199         .master         = &omap54xx_l4_cfg_hwmod,
2200         .slave          = &omap54xx_dma_system_hwmod,
2201         .clk            = "l4_root_clk_div",
2202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2203 };
2204
2205 /* l4_abe -> dmic */
2206 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2207         .master         = &omap54xx_l4_abe_hwmod,
2208         .slave          = &omap54xx_dmic_hwmod,
2209         .clk            = "abe_iclk",
2210         .user           = OCP_USER_MPU,
2211 };
2212
2213 /* l3_main_2 -> dss */
2214 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2215         .master         = &omap54xx_l3_main_2_hwmod,
2216         .slave          = &omap54xx_dss_hwmod,
2217         .clk            = "l3_iclk_div",
2218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220
2221 /* l3_main_2 -> dss_dispc */
2222 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2223         .master         = &omap54xx_l3_main_2_hwmod,
2224         .slave          = &omap54xx_dss_dispc_hwmod,
2225         .clk            = "l3_iclk_div",
2226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2227 };
2228
2229 /* l3_main_2 -> dss_dsi1_a */
2230 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2231         .master         = &omap54xx_l3_main_2_hwmod,
2232         .slave          = &omap54xx_dss_dsi1_a_hwmod,
2233         .clk            = "l3_iclk_div",
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237 /* l3_main_2 -> dss_dsi1_c */
2238 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2239         .master         = &omap54xx_l3_main_2_hwmod,
2240         .slave          = &omap54xx_dss_dsi1_c_hwmod,
2241         .clk            = "l3_iclk_div",
2242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2243 };
2244
2245 /* l3_main_2 -> dss_hdmi */
2246 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2247         .master         = &omap54xx_l3_main_2_hwmod,
2248         .slave          = &omap54xx_dss_hdmi_hwmod,
2249         .clk            = "l3_iclk_div",
2250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2251 };
2252
2253 /* l3_main_2 -> dss_rfbi */
2254 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2255         .master         = &omap54xx_l3_main_2_hwmod,
2256         .slave          = &omap54xx_dss_rfbi_hwmod,
2257         .clk            = "l3_iclk_div",
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /* mpu -> emif1 */
2262 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2263         .master         = &omap54xx_mpu_hwmod,
2264         .slave          = &omap54xx_emif1_hwmod,
2265         .clk            = "dpll_core_h11x2_ck",
2266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268
2269 /* mpu -> emif2 */
2270 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2271         .master         = &omap54xx_mpu_hwmod,
2272         .slave          = &omap54xx_emif2_hwmod,
2273         .clk            = "dpll_core_h11x2_ck",
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* l4_wkup -> gpio1 */
2278 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2279         .master         = &omap54xx_l4_wkup_hwmod,
2280         .slave          = &omap54xx_gpio1_hwmod,
2281         .clk            = "wkupaon_iclk_mux",
2282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284
2285 /* l4_per -> gpio2 */
2286 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2287         .master         = &omap54xx_l4_per_hwmod,
2288         .slave          = &omap54xx_gpio2_hwmod,
2289         .clk            = "l4_root_clk_div",
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292
2293 /* l4_per -> gpio3 */
2294 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2295         .master         = &omap54xx_l4_per_hwmod,
2296         .slave          = &omap54xx_gpio3_hwmod,
2297         .clk            = "l4_root_clk_div",
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* l4_per -> gpio4 */
2302 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2303         .master         = &omap54xx_l4_per_hwmod,
2304         .slave          = &omap54xx_gpio4_hwmod,
2305         .clk            = "l4_root_clk_div",
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* l4_per -> gpio5 */
2310 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2311         .master         = &omap54xx_l4_per_hwmod,
2312         .slave          = &omap54xx_gpio5_hwmod,
2313         .clk            = "l4_root_clk_div",
2314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2315 };
2316
2317 /* l4_per -> gpio6 */
2318 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2319         .master         = &omap54xx_l4_per_hwmod,
2320         .slave          = &omap54xx_gpio6_hwmod,
2321         .clk            = "l4_root_clk_div",
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 /* l4_per -> gpio7 */
2326 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2327         .master         = &omap54xx_l4_per_hwmod,
2328         .slave          = &omap54xx_gpio7_hwmod,
2329         .clk            = "l4_root_clk_div",
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332
2333 /* l4_per -> gpio8 */
2334 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2335         .master         = &omap54xx_l4_per_hwmod,
2336         .slave          = &omap54xx_gpio8_hwmod,
2337         .clk            = "l4_root_clk_div",
2338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2339 };
2340
2341 /* l4_per -> i2c1 */
2342 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2343         .master         = &omap54xx_l4_per_hwmod,
2344         .slave          = &omap54xx_i2c1_hwmod,
2345         .clk            = "l4_root_clk_div",
2346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2347 };
2348
2349 /* l4_per -> i2c2 */
2350 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2351         .master         = &omap54xx_l4_per_hwmod,
2352         .slave          = &omap54xx_i2c2_hwmod,
2353         .clk            = "l4_root_clk_div",
2354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356
2357 /* l4_per -> i2c3 */
2358 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2359         .master         = &omap54xx_l4_per_hwmod,
2360         .slave          = &omap54xx_i2c3_hwmod,
2361         .clk            = "l4_root_clk_div",
2362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2363 };
2364
2365 /* l4_per -> i2c4 */
2366 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2367         .master         = &omap54xx_l4_per_hwmod,
2368         .slave          = &omap54xx_i2c4_hwmod,
2369         .clk            = "l4_root_clk_div",
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373 /* l4_per -> i2c5 */
2374 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2375         .master         = &omap54xx_l4_per_hwmod,
2376         .slave          = &omap54xx_i2c5_hwmod,
2377         .clk            = "l4_root_clk_div",
2378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380
2381 /* l4_wkup -> kbd */
2382 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2383         .master         = &omap54xx_l4_wkup_hwmod,
2384         .slave          = &omap54xx_kbd_hwmod,
2385         .clk            = "wkupaon_iclk_mux",
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389 /* l4_cfg -> mailbox */
2390 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2391         .master         = &omap54xx_l4_cfg_hwmod,
2392         .slave          = &omap54xx_mailbox_hwmod,
2393         .clk            = "l4_root_clk_div",
2394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2395 };
2396
2397 /* l4_abe -> mcbsp1 */
2398 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2399         .master         = &omap54xx_l4_abe_hwmod,
2400         .slave          = &omap54xx_mcbsp1_hwmod,
2401         .clk            = "abe_iclk",
2402         .user           = OCP_USER_MPU,
2403 };
2404
2405 /* l4_abe -> mcbsp2 */
2406 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2407         .master         = &omap54xx_l4_abe_hwmod,
2408         .slave          = &omap54xx_mcbsp2_hwmod,
2409         .clk            = "abe_iclk",
2410         .user           = OCP_USER_MPU,
2411 };
2412
2413 /* l4_abe -> mcbsp3 */
2414 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2415         .master         = &omap54xx_l4_abe_hwmod,
2416         .slave          = &omap54xx_mcbsp3_hwmod,
2417         .clk            = "abe_iclk",
2418         .user           = OCP_USER_MPU,
2419 };
2420
2421 /* l4_abe -> mcpdm */
2422 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2423         .master         = &omap54xx_l4_abe_hwmod,
2424         .slave          = &omap54xx_mcpdm_hwmod,
2425         .clk            = "abe_iclk",
2426         .user           = OCP_USER_MPU,
2427 };
2428
2429 /* l4_per -> mcspi1 */
2430 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2431         .master         = &omap54xx_l4_per_hwmod,
2432         .slave          = &omap54xx_mcspi1_hwmod,
2433         .clk            = "l4_root_clk_div",
2434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436
2437 /* l4_per -> mcspi2 */
2438 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2439         .master         = &omap54xx_l4_per_hwmod,
2440         .slave          = &omap54xx_mcspi2_hwmod,
2441         .clk            = "l4_root_clk_div",
2442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444
2445 /* l4_per -> mcspi3 */
2446 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2447         .master         = &omap54xx_l4_per_hwmod,
2448         .slave          = &omap54xx_mcspi3_hwmod,
2449         .clk            = "l4_root_clk_div",
2450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2451 };
2452
2453 /* l4_per -> mcspi4 */
2454 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2455         .master         = &omap54xx_l4_per_hwmod,
2456         .slave          = &omap54xx_mcspi4_hwmod,
2457         .clk            = "l4_root_clk_div",
2458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2459 };
2460
2461 /* l4_per -> mmc1 */
2462 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2463         .master         = &omap54xx_l4_per_hwmod,
2464         .slave          = &omap54xx_mmc1_hwmod,
2465         .clk            = "l3_iclk_div",
2466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2467 };
2468
2469 /* l4_per -> mmc2 */
2470 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2471         .master         = &omap54xx_l4_per_hwmod,
2472         .slave          = &omap54xx_mmc2_hwmod,
2473         .clk            = "l3_iclk_div",
2474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2475 };
2476
2477 /* l4_per -> mmc3 */
2478 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2479         .master         = &omap54xx_l4_per_hwmod,
2480         .slave          = &omap54xx_mmc3_hwmod,
2481         .clk            = "l4_root_clk_div",
2482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2483 };
2484
2485 /* l4_per -> mmc4 */
2486 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2487         .master         = &omap54xx_l4_per_hwmod,
2488         .slave          = &omap54xx_mmc4_hwmod,
2489         .clk            = "l4_root_clk_div",
2490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2491 };
2492
2493 /* l4_per -> mmc5 */
2494 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2495         .master         = &omap54xx_l4_per_hwmod,
2496         .slave          = &omap54xx_mmc5_hwmod,
2497         .clk            = "l4_root_clk_div",
2498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2499 };
2500
2501 /* l4_cfg -> mpu */
2502 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2503         .master         = &omap54xx_l4_cfg_hwmod,
2504         .slave          = &omap54xx_mpu_hwmod,
2505         .clk            = "l4_root_clk_div",
2506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2507 };
2508
2509 /* l4_cfg -> spinlock */
2510 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2511         .master         = &omap54xx_l4_cfg_hwmod,
2512         .slave          = &omap54xx_spinlock_hwmod,
2513         .clk            = "l4_root_clk_div",
2514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2515 };
2516
2517 /* l4_cfg -> ocp2scp1 */
2518 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2519         .master         = &omap54xx_l4_cfg_hwmod,
2520         .slave          = &omap54xx_ocp2scp1_hwmod,
2521         .clk            = "l4_root_clk_div",
2522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2523 };
2524
2525 /* l4_wkup -> timer1 */
2526 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2527         .master         = &omap54xx_l4_wkup_hwmod,
2528         .slave          = &omap54xx_timer1_hwmod,
2529         .clk            = "wkupaon_iclk_mux",
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532
2533 /* l4_per -> timer2 */
2534 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2535         .master         = &omap54xx_l4_per_hwmod,
2536         .slave          = &omap54xx_timer2_hwmod,
2537         .clk            = "l4_root_clk_div",
2538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2539 };
2540
2541 /* l4_per -> timer3 */
2542 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2543         .master         = &omap54xx_l4_per_hwmod,
2544         .slave          = &omap54xx_timer3_hwmod,
2545         .clk            = "l4_root_clk_div",
2546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2547 };
2548
2549 /* l4_per -> timer4 */
2550 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2551         .master         = &omap54xx_l4_per_hwmod,
2552         .slave          = &omap54xx_timer4_hwmod,
2553         .clk            = "l4_root_clk_div",
2554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2555 };
2556
2557 /* l4_abe -> timer5 */
2558 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2559         .master         = &omap54xx_l4_abe_hwmod,
2560         .slave          = &omap54xx_timer5_hwmod,
2561         .clk            = "abe_iclk",
2562         .user           = OCP_USER_MPU,
2563 };
2564
2565 /* l4_abe -> timer6 */
2566 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2567         .master         = &omap54xx_l4_abe_hwmod,
2568         .slave          = &omap54xx_timer6_hwmod,
2569         .clk            = "abe_iclk",
2570         .user           = OCP_USER_MPU,
2571 };
2572
2573 /* l4_abe -> timer7 */
2574 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2575         .master         = &omap54xx_l4_abe_hwmod,
2576         .slave          = &omap54xx_timer7_hwmod,
2577         .clk            = "abe_iclk",
2578         .user           = OCP_USER_MPU,
2579 };
2580
2581 /* l4_abe -> timer8 */
2582 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2583         .master         = &omap54xx_l4_abe_hwmod,
2584         .slave          = &omap54xx_timer8_hwmod,
2585         .clk            = "abe_iclk",
2586         .user           = OCP_USER_MPU,
2587 };
2588
2589 /* l4_per -> timer9 */
2590 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2591         .master         = &omap54xx_l4_per_hwmod,
2592         .slave          = &omap54xx_timer9_hwmod,
2593         .clk            = "l4_root_clk_div",
2594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 /* l4_per -> timer10 */
2598 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2599         .master         = &omap54xx_l4_per_hwmod,
2600         .slave          = &omap54xx_timer10_hwmod,
2601         .clk            = "l4_root_clk_div",
2602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2603 };
2604
2605 /* l4_per -> timer11 */
2606 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2607         .master         = &omap54xx_l4_per_hwmod,
2608         .slave          = &omap54xx_timer11_hwmod,
2609         .clk            = "l4_root_clk_div",
2610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2611 };
2612
2613 /* l4_per -> uart1 */
2614 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2615         .master         = &omap54xx_l4_per_hwmod,
2616         .slave          = &omap54xx_uart1_hwmod,
2617         .clk            = "l4_root_clk_div",
2618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2619 };
2620
2621 /* l4_per -> uart2 */
2622 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2623         .master         = &omap54xx_l4_per_hwmod,
2624         .slave          = &omap54xx_uart2_hwmod,
2625         .clk            = "l4_root_clk_div",
2626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2627 };
2628
2629 /* l4_per -> uart3 */
2630 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2631         .master         = &omap54xx_l4_per_hwmod,
2632         .slave          = &omap54xx_uart3_hwmod,
2633         .clk            = "l4_root_clk_div",
2634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2635 };
2636
2637 /* l4_per -> uart4 */
2638 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2639         .master         = &omap54xx_l4_per_hwmod,
2640         .slave          = &omap54xx_uart4_hwmod,
2641         .clk            = "l4_root_clk_div",
2642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2643 };
2644
2645 /* l4_per -> uart5 */
2646 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2647         .master         = &omap54xx_l4_per_hwmod,
2648         .slave          = &omap54xx_uart5_hwmod,
2649         .clk            = "l4_root_clk_div",
2650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2651 };
2652
2653 /* l4_per -> uart6 */
2654 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2655         .master         = &omap54xx_l4_per_hwmod,
2656         .slave          = &omap54xx_uart6_hwmod,
2657         .clk            = "l4_root_clk_div",
2658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2659 };
2660
2661 /* l4_cfg -> usb_host_hs */
2662 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2663         .master         = &omap54xx_l4_cfg_hwmod,
2664         .slave          = &omap54xx_usb_host_hs_hwmod,
2665         .clk            = "l3_iclk_div",
2666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 /* l4_cfg -> usb_tll_hs */
2670 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2671         .master         = &omap54xx_l4_cfg_hwmod,
2672         .slave          = &omap54xx_usb_tll_hs_hwmod,
2673         .clk            = "l4_root_clk_div",
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676
2677 /* l4_cfg -> usb_otg_ss */
2678 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2679         .master         = &omap54xx_l4_cfg_hwmod,
2680         .slave          = &omap54xx_usb_otg_ss_hwmod,
2681         .clk            = "dpll_core_h13x2_ck",
2682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2683 };
2684
2685 /* l4_wkup -> wd_timer2 */
2686 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2687         .master         = &omap54xx_l4_wkup_hwmod,
2688         .slave          = &omap54xx_wd_timer2_hwmod,
2689         .clk            = "wkupaon_iclk_mux",
2690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692
2693 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2694         &omap54xx_l3_main_1__dmm,
2695         &omap54xx_l3_main_3__l3_instr,
2696         &omap54xx_l3_main_2__l3_main_1,
2697         &omap54xx_l4_cfg__l3_main_1,
2698         &omap54xx_mpu__l3_main_1,
2699         &omap54xx_l3_main_1__l3_main_2,
2700         &omap54xx_l4_cfg__l3_main_2,
2701         &omap54xx_l3_main_1__l3_main_3,
2702         &omap54xx_l3_main_2__l3_main_3,
2703         &omap54xx_l4_cfg__l3_main_3,
2704         &omap54xx_l3_main_1__l4_abe,
2705         &omap54xx_mpu__l4_abe,
2706         &omap54xx_l3_main_1__l4_cfg,
2707         &omap54xx_l3_main_2__l4_per,
2708         &omap54xx_l3_main_1__l4_wkup,
2709         &omap54xx_mpu__mpu_private,
2710         &omap54xx_l4_wkup__counter_32k,
2711         &omap54xx_l4_cfg__dma_system,
2712         &omap54xx_l4_abe__dmic,
2713         &omap54xx_l4_cfg__mmu_dsp,
2714         &omap54xx_l3_main_2__dss,
2715         &omap54xx_l3_main_2__dss_dispc,
2716         &omap54xx_l3_main_2__dss_dsi1_a,
2717         &omap54xx_l3_main_2__dss_dsi1_c,
2718         &omap54xx_l3_main_2__dss_hdmi,
2719         &omap54xx_l3_main_2__dss_rfbi,
2720         &omap54xx_mpu__emif1,
2721         &omap54xx_mpu__emif2,
2722         &omap54xx_l4_wkup__gpio1,
2723         &omap54xx_l4_per__gpio2,
2724         &omap54xx_l4_per__gpio3,
2725         &omap54xx_l4_per__gpio4,
2726         &omap54xx_l4_per__gpio5,
2727         &omap54xx_l4_per__gpio6,
2728         &omap54xx_l4_per__gpio7,
2729         &omap54xx_l4_per__gpio8,
2730         &omap54xx_l4_per__i2c1,
2731         &omap54xx_l4_per__i2c2,
2732         &omap54xx_l4_per__i2c3,
2733         &omap54xx_l4_per__i2c4,
2734         &omap54xx_l4_per__i2c5,
2735         &omap54xx_l3_main_2__mmu_ipu,
2736         &omap54xx_l4_wkup__kbd,
2737         &omap54xx_l4_cfg__mailbox,
2738         &omap54xx_l4_abe__mcbsp1,
2739         &omap54xx_l4_abe__mcbsp2,
2740         &omap54xx_l4_abe__mcbsp3,
2741         &omap54xx_l4_abe__mcpdm,
2742         &omap54xx_l4_per__mcspi1,
2743         &omap54xx_l4_per__mcspi2,
2744         &omap54xx_l4_per__mcspi3,
2745         &omap54xx_l4_per__mcspi4,
2746         &omap54xx_l4_per__mmc1,
2747         &omap54xx_l4_per__mmc2,
2748         &omap54xx_l4_per__mmc3,
2749         &omap54xx_l4_per__mmc4,
2750         &omap54xx_l4_per__mmc5,
2751         &omap54xx_l4_cfg__mpu,
2752         &omap54xx_l4_cfg__spinlock,
2753         &omap54xx_l4_cfg__ocp2scp1,
2754         &omap54xx_l4_wkup__timer1,
2755         &omap54xx_l4_per__timer2,
2756         &omap54xx_l4_per__timer3,
2757         &omap54xx_l4_per__timer4,
2758         &omap54xx_l4_abe__timer5,
2759         &omap54xx_l4_abe__timer6,
2760         &omap54xx_l4_abe__timer7,
2761         &omap54xx_l4_abe__timer8,
2762         &omap54xx_l4_per__timer9,
2763         &omap54xx_l4_per__timer10,
2764         &omap54xx_l4_per__timer11,
2765         &omap54xx_l4_per__uart1,
2766         &omap54xx_l4_per__uart2,
2767         &omap54xx_l4_per__uart3,
2768         &omap54xx_l4_per__uart4,
2769         &omap54xx_l4_per__uart5,
2770         &omap54xx_l4_per__uart6,
2771         &omap54xx_l4_cfg__usb_host_hs,
2772         &omap54xx_l4_cfg__usb_tll_hs,
2773         &omap54xx_l4_cfg__usb_otg_ss,
2774         &omap54xx_l4_wkup__wd_timer2,
2775         &omap54xx_l4_cfg__ocp2scp3,
2776         &omap54xx_l4_cfg__sata,
2777         NULL,
2778 };
2779
2780 int __init omap54xx_hwmod_init(void)
2781 {
2782         omap_hwmod_init();
2783         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2784 }