]> git.ipfire.org Git - thirdparty/kernel/linux.git/blob - arch/arm/mach-omap2/omap_hwmod_7xx_data.c
projects / thirdparty / kernel / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branches 'clk-warn', 'clk-core', 'clk-spear' and 'clk-qcom-msm8998' into clk...
[thirdparty/kernel/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
24
25 #include <linux/omap-dma.h>
26
27 #include "omap_hwmod.h"
28 #include "omap_hwmod_common_data.h"
29 #include "cm1_7xx.h"
30 #include "cm2_7xx.h"
31 #include "prm7xx.h"
32 #include "i2c.h"
33 #include "wd_timer.h"
34 #include "soc.h"
35
36 /* Base offset for all DRA7XX interrupts external to MPUSS */
37 #define DRA7XX_IRQ_GIC_START 32
38
39 /* Base offset for all DRA7XX dma requests */
40 #define DRA7XX_DMA_REQ_START 1
41
42
43 /*
44 * IP blocks
45 */
46
47 /*
48 * 'dmm' class
49 * instance(s): dmm
50 */
51 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
52 .name = "dmm",
53 };
54
55 /* dmm */
56 static struct omap_hwmod dra7xx_dmm_hwmod = {
57 .name = "dmm",
58 .class = &dra7xx_dmm_hwmod_class,
59 .clkdm_name = "emif_clkdm",
60 .prcm = {
61 .omap4 = {
62 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
63 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
64 },
65 },
66 };
67
68 /*
69 * 'l3' class
70 * instance(s): l3_instr, l3_main_1, l3_main_2
71 */
72 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
73 .name = "l3",
74 };
75
76 /* l3_instr */
77 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
78 .name = "l3_instr",
79 .class = &dra7xx_l3_hwmod_class,
80 .clkdm_name = "l3instr_clkdm",
81 .prcm = {
82 .omap4 = {
83 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
84 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
85 .modulemode = MODULEMODE_HWCTRL,
86 },
87 },
88 };
89
90 /* l3_main_1 */
91 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
92 .name = "l3_main_1",
93 .class = &dra7xx_l3_hwmod_class,
94 .clkdm_name = "l3main1_clkdm",
95 .prcm = {
96 .omap4 = {
97 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
98 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
99 },
100 },
101 };
102
103 /* l3_main_2 */
104 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
105 .name = "l3_main_2",
106 .class = &dra7xx_l3_hwmod_class,
107 .clkdm_name = "l3instr_clkdm",
108 .prcm = {
109 .omap4 = {
110 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
111 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
112 .modulemode = MODULEMODE_HWCTRL,
113 },
114 },
115 };
116
117 /*
118 * 'l4' class
119 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
120 */
121 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
122 .name = "l4",
123 };
124
125 /* l4_cfg */
126 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
127 .name = "l4_cfg",
128 .class = &dra7xx_l4_hwmod_class,
129 .clkdm_name = "l4cfg_clkdm",
130 .prcm = {
131 .omap4 = {
132 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
133 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
134 },
135 },
136 };
137
138 /* l4_per1 */
139 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
140 .name = "l4_per1",
141 .class = &dra7xx_l4_hwmod_class,
142 .clkdm_name = "l4per_clkdm",
143 .prcm = {
144 .omap4 = {
145 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
146 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
147 },
148 },
149 };
150
151 /* l4_per2 */
152 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
153 .name = "l4_per2",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4per2_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
159 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
160 },
161 },
162 };
163
164 /* l4_per3 */
165 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
166 .name = "l4_per3",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per3_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
176
177 /* l4_wkup */
178 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
179 .name = "l4_wkup",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "wkupaon_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
185 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
186 },
187 },
188 };
189
190 /*
191 * 'atl' class
192 *
193 */
194
195 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
196 .name = "atl",
197 };
198
199 /* atl */
200 static struct omap_hwmod dra7xx_atl_hwmod = {
201 .name = "atl",
202 .class = &dra7xx_atl_hwmod_class,
203 .clkdm_name = "atl_clkdm",
204 .main_clk = "atl_gfclk_mux",
205 .prcm = {
206 .omap4 = {
207 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
208 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
209 .modulemode = MODULEMODE_SWCTRL,
210 },
211 },
212 };
213
214 /*
215 * 'bb2d' class
216 *
217 */
218
219 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
220 .name = "bb2d",
221 };
222
223 /* bb2d */
224 static struct omap_hwmod dra7xx_bb2d_hwmod = {
225 .name = "bb2d",
226 .class = &dra7xx_bb2d_hwmod_class,
227 .clkdm_name = "dss_clkdm",
228 .main_clk = "dpll_core_h24x2_ck",
229 .prcm = {
230 .omap4 = {
231 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
232 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
233 .modulemode = MODULEMODE_SWCTRL,
234 },
235 },
236 };
237
238 /*
239 * 'counter' class
240 *
241 */
242
243 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
244 .rev_offs = 0x0000,
245 .sysc_offs = 0x0010,
246 .sysc_flags = SYSC_HAS_SIDLEMODE,
247 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
248 SIDLE_SMART_WKUP),
249 .sysc_fields = &omap_hwmod_sysc_type1,
250 };
251
252 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
253 .name = "counter",
254 .sysc = &dra7xx_counter_sysc,
255 };
256
257 /* counter_32k */
258 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
259 .name = "counter_32k",
260 .class = &dra7xx_counter_hwmod_class,
261 .clkdm_name = "wkupaon_clkdm",
262 .flags = HWMOD_SWSUP_SIDLE,
263 .main_clk = "wkupaon_iclk_mux",
264 .prcm = {
265 .omap4 = {
266 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
267 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
268 },
269 },
270 };
271
272 /*
273 * 'ctrl_module' class
274 *
275 */
276
277 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
278 .name = "ctrl_module",
279 };
280
281 /* ctrl_module_wkup */
282 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
283 .name = "ctrl_module_wkup",
284 .class = &dra7xx_ctrl_module_hwmod_class,
285 .clkdm_name = "wkupaon_clkdm",
286 .prcm = {
287 .omap4 = {
288 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
289 },
290 },
291 };
292
293 /*
294 * 'gmac' class
295 * cpsw/gmac sub system
296 */
297 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
298 .rev_offs = 0x0,
299 .sysc_offs = 0x8,
300 .syss_offs = 0x4,
301 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
302 SYSS_HAS_RESET_STATUS),
303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
304 MSTANDBY_NO),
305 .sysc_fields = &omap_hwmod_sysc_type3,
306 };
307
308 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
309 .name = "gmac",
310 .sysc = &dra7xx_gmac_sysc,
311 };
312
313 static struct omap_hwmod dra7xx_gmac_hwmod = {
314 .name = "gmac",
315 .class = &dra7xx_gmac_hwmod_class,
316 .clkdm_name = "gmac_clkdm",
317 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
318 .main_clk = "dpll_gmac_ck",
319 .mpu_rt_idx = 1,
320 .prcm = {
321 .omap4 = {
322 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
323 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
324 .modulemode = MODULEMODE_SWCTRL,
325 },
326 },
327 };
328
329 /*
330 * 'mdio' class
331 */
332 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
333 .name = "davinci_mdio",
334 };
335
336 static struct omap_hwmod dra7xx_mdio_hwmod = {
337 .name = "davinci_mdio",
338 .class = &dra7xx_mdio_hwmod_class,
339 .clkdm_name = "gmac_clkdm",
340 .main_clk = "dpll_gmac_ck",
341 };
342
343 /*
344 * 'dcan' class
345 *
346 */
347
348 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
349 .name = "dcan",
350 };
351
352 /* dcan1 */
353 static struct omap_hwmod dra7xx_dcan1_hwmod = {
354 .name = "dcan1",
355 .class = &dra7xx_dcan_hwmod_class,
356 .clkdm_name = "wkupaon_clkdm",
357 .main_clk = "dcan1_sys_clk_mux",
358 .flags = HWMOD_CLKDM_NOAUTO,
359 .prcm = {
360 .omap4 = {
361 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
362 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
363 .modulemode = MODULEMODE_SWCTRL,
364 },
365 },
366 };
367
368 /* dcan2 */
369 static struct omap_hwmod dra7xx_dcan2_hwmod = {
370 .name = "dcan2",
371 .class = &dra7xx_dcan_hwmod_class,
372 .clkdm_name = "l4per2_clkdm",
373 .main_clk = "sys_clkin1",
374 .flags = HWMOD_CLKDM_NOAUTO,
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
378 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
379 .modulemode = MODULEMODE_SWCTRL,
380 },
381 },
382 };
383
384 /* pwmss */
385 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
386 .rev_offs = 0x0,
387 .sysc_offs = 0x4,
388 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
390 .sysc_fields = &omap_hwmod_sysc_type2,
391 };
392
393 /*
394 * epwmss class
395 */
396 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
397 .name = "epwmss",
398 .sysc = &dra7xx_epwmss_sysc,
399 };
400
401 /* epwmss0 */
402 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
403 .name = "epwmss0",
404 .class = &dra7xx_epwmss_hwmod_class,
405 .clkdm_name = "l4per2_clkdm",
406 .main_clk = "l4_root_clk_div",
407 .prcm = {
408 .omap4 = {
409 .modulemode = MODULEMODE_SWCTRL,
410 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
412 },
413 },
414 };
415
416 /* epwmss1 */
417 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
418 .name = "epwmss1",
419 .class = &dra7xx_epwmss_hwmod_class,
420 .clkdm_name = "l4per2_clkdm",
421 .main_clk = "l4_root_clk_div",
422 .prcm = {
423 .omap4 = {
424 .modulemode = MODULEMODE_SWCTRL,
425 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
427 },
428 },
429 };
430
431 /* epwmss2 */
432 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
433 .name = "epwmss2",
434 .class = &dra7xx_epwmss_hwmod_class,
435 .clkdm_name = "l4per2_clkdm",
436 .main_clk = "l4_root_clk_div",
437 .prcm = {
438 .omap4 = {
439 .modulemode = MODULEMODE_SWCTRL,
440 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
441 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
442 },
443 },
444 };
445
446 /*
447 * 'dma' class
448 *
449 */
450
451 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
452 .rev_offs = 0x0000,
453 .sysc_offs = 0x002c,
454 .syss_offs = 0x0028,
455 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
456 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
457 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
458 SYSS_HAS_RESET_STATUS),
459 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
460 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
461 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
462 .sysc_fields = &omap_hwmod_sysc_type1,
463 };
464
465 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
466 .name = "dma",
467 .sysc = &dra7xx_dma_sysc,
468 };
469
470 /* dma dev_attr */
471 static struct omap_dma_dev_attr dma_dev_attr = {
472 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
473 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
474 .lch_count = 32,
475 };
476
477 /* dma_system */
478 static struct omap_hwmod dra7xx_dma_system_hwmod = {
479 .name = "dma_system",
480 .class = &dra7xx_dma_hwmod_class,
481 .clkdm_name = "dma_clkdm",
482 .main_clk = "l3_iclk_div",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
491
492 /*
493 * 'tpcc' class
494 *
495 */
496 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
497 .name = "tpcc",
498 };
499
500 static struct omap_hwmod dra7xx_tpcc_hwmod = {
501 .name = "tpcc",
502 .class = &dra7xx_tpcc_hwmod_class,
503 .clkdm_name = "l3main1_clkdm",
504 .main_clk = "l3_iclk_div",
505 .prcm = {
506 .omap4 = {
507 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
508 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
509 },
510 },
511 };
512
513 /*
514 * 'tptc' class
515 *
516 */
517 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
518 .name = "tptc",
519 };
520
521 /* tptc0 */
522 static struct omap_hwmod dra7xx_tptc0_hwmod = {
523 .name = "tptc0",
524 .class = &dra7xx_tptc_hwmod_class,
525 .clkdm_name = "l3main1_clkdm",
526 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
527 .main_clk = "l3_iclk_div",
528 .prcm = {
529 .omap4 = {
530 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
531 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
532 .modulemode = MODULEMODE_HWCTRL,
533 },
534 },
535 };
536
537 /* tptc1 */
538 static struct omap_hwmod dra7xx_tptc1_hwmod = {
539 .name = "tptc1",
540 .class = &dra7xx_tptc_hwmod_class,
541 .clkdm_name = "l3main1_clkdm",
542 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
543 .main_clk = "l3_iclk_div",
544 .prcm = {
545 .omap4 = {
546 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
547 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
548 .modulemode = MODULEMODE_HWCTRL,
549 },
550 },
551 };
552
553 /*
554 * 'dss' class
555 *
556 */
557
558 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
559 .rev_offs = 0x0000,
560 .syss_offs = 0x0014,
561 .sysc_flags = SYSS_HAS_RESET_STATUS,
562 };
563
564 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
565 .name = "dss",
566 .sysc = &dra7xx_dss_sysc,
567 .reset = omap_dss_reset,
568 };
569
570 /* dss */
571 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
572 { .role = "dss_clk", .clk = "dss_dss_clk" },
573 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
574 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
575 { .role = "video2_clk", .clk = "dss_video2_clk" },
576 { .role = "video1_clk", .clk = "dss_video1_clk" },
577 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
578 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
579 };
580
581 static struct omap_hwmod dra7xx_dss_hwmod = {
582 .name = "dss_core",
583 .class = &dra7xx_dss_hwmod_class,
584 .clkdm_name = "dss_clkdm",
585 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
586 .main_clk = "dss_dss_clk",
587 .prcm = {
588 .omap4 = {
589 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
590 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
591 .modulemode = MODULEMODE_SWCTRL,
592 },
593 },
594 .opt_clks = dss_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
596 };
597
598 /*
599 * 'dispc' class
600 * display controller
601 */
602
603 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
604 .rev_offs = 0x0000,
605 .sysc_offs = 0x0010,
606 .syss_offs = 0x0014,
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
608 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
609 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
610 SYSS_HAS_RESET_STATUS),
611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
612 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
614 };
615
616 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
617 .name = "dispc",
618 .sysc = &dra7xx_dispc_sysc,
619 };
620
621 /* dss_dispc */
622 /* dss_dispc dev_attr */
623 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
624 .has_framedonetv_irq = 1,
625 .manager_count = 4,
626 };
627
628 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
629 .name = "dss_dispc",
630 .class = &dra7xx_dispc_hwmod_class,
631 .clkdm_name = "dss_clkdm",
632 .main_clk = "dss_dss_clk",
633 .prcm = {
634 .omap4 = {
635 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
636 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
637 },
638 },
639 .dev_attr = &dss_dispc_dev_attr,
640 .parent_hwmod = &dra7xx_dss_hwmod,
641 };
642
643 /*
644 * 'hdmi' class
645 * hdmi controller
646 */
647
648 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
649 .rev_offs = 0x0000,
650 .sysc_offs = 0x0010,
651 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
652 SYSC_HAS_SOFTRESET),
653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
654 SIDLE_SMART_WKUP),
655 .sysc_fields = &omap_hwmod_sysc_type2,
656 };
657
658 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
659 .name = "hdmi",
660 .sysc = &dra7xx_hdmi_sysc,
661 };
662
663 /* dss_hdmi */
664
665 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
666 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
667 };
668
669 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
670 .name = "dss_hdmi",
671 .class = &dra7xx_hdmi_hwmod_class,
672 .clkdm_name = "dss_clkdm",
673 .main_clk = "dss_48mhz_clk",
674 .prcm = {
675 .omap4 = {
676 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
677 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
678 },
679 },
680 .opt_clks = dss_hdmi_opt_clks,
681 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
682 .parent_hwmod = &dra7xx_dss_hwmod,
683 };
684
685 /* AES (the 'P' (public) device) */
686 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
687 .rev_offs = 0x0080,
688 .sysc_offs = 0x0084,
689 .syss_offs = 0x0088,
690 .sysc_flags = SYSS_HAS_RESET_STATUS,
691 };
692
693 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
694 .name = "aes",
695 .sysc = &dra7xx_aes_sysc,
696 .rev = 2,
697 };
698
699 /* AES1 */
700 static struct omap_hwmod dra7xx_aes1_hwmod = {
701 .name = "aes1",
702 .class = &dra7xx_aes_hwmod_class,
703 .clkdm_name = "l4sec_clkdm",
704 .main_clk = "l3_iclk_div",
705 .prcm = {
706 .omap4 = {
707 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
708 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
709 .modulemode = MODULEMODE_HWCTRL,
710 },
711 },
712 };
713
714 /* AES2 */
715 static struct omap_hwmod dra7xx_aes2_hwmod = {
716 .name = "aes2",
717 .class = &dra7xx_aes_hwmod_class,
718 .clkdm_name = "l4sec_clkdm",
719 .main_clk = "l3_iclk_div",
720 .prcm = {
721 .omap4 = {
722 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
723 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
724 .modulemode = MODULEMODE_HWCTRL,
725 },
726 },
727 };
728
729 /* sha0 HIB2 (the 'P' (public) device) */
730 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
731 .rev_offs = 0x100,
732 .sysc_offs = 0x110,
733 .syss_offs = 0x114,
734 .sysc_flags = SYSS_HAS_RESET_STATUS,
735 };
736
737 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
738 .name = "sham",
739 .sysc = &dra7xx_sha0_sysc,
740 .rev = 2,
741 };
742
743 struct omap_hwmod dra7xx_sha0_hwmod = {
744 .name = "sham",
745 .class = &dra7xx_sha0_hwmod_class,
746 .clkdm_name = "l4sec_clkdm",
747 .main_clk = "l3_iclk_div",
748 .prcm = {
749 .omap4 = {
750 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
751 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
752 .modulemode = MODULEMODE_HWCTRL,
753 },
754 },
755 };
756
757 /*
758 * 'elm' class
759 *
760 */
761
762 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
763 .rev_offs = 0x0000,
764 .sysc_offs = 0x0010,
765 .syss_offs = 0x0014,
766 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
767 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
768 SYSS_HAS_RESET_STATUS),
769 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
770 SIDLE_SMART_WKUP),
771 .sysc_fields = &omap_hwmod_sysc_type1,
772 };
773
774 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
775 .name = "elm",
776 .sysc = &dra7xx_elm_sysc,
777 };
778
779 /* elm */
780
781 static struct omap_hwmod dra7xx_elm_hwmod = {
782 .name = "elm",
783 .class = &dra7xx_elm_hwmod_class,
784 .clkdm_name = "l4per_clkdm",
785 .main_clk = "l3_iclk_div",
786 .prcm = {
787 .omap4 = {
788 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
789 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
790 },
791 },
792 };
793
794 /*
795 * 'gpio' class
796 *
797 */
798
799 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
800 .rev_offs = 0x0000,
801 .sysc_offs = 0x0010,
802 .syss_offs = 0x0114,
803 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
804 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
805 SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
807 SIDLE_SMART_WKUP),
808 .sysc_fields = &omap_hwmod_sysc_type1,
809 };
810
811 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
812 .name = "gpio",
813 .sysc = &dra7xx_gpio_sysc,
814 .rev = 2,
815 };
816
817 /* gpio1 */
818 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
819 { .role = "dbclk", .clk = "gpio1_dbclk" },
820 };
821
822 static struct omap_hwmod dra7xx_gpio1_hwmod = {
823 .name = "gpio1",
824 .class = &dra7xx_gpio_hwmod_class,
825 .clkdm_name = "wkupaon_clkdm",
826 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
827 .main_clk = "wkupaon_iclk_mux",
828 .prcm = {
829 .omap4 = {
830 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
831 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
832 .modulemode = MODULEMODE_HWCTRL,
833 },
834 },
835 .opt_clks = gpio1_opt_clks,
836 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
837 };
838
839 /* gpio2 */
840 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
841 { .role = "dbclk", .clk = "gpio2_dbclk" },
842 };
843
844 static struct omap_hwmod dra7xx_gpio2_hwmod = {
845 .name = "gpio2",
846 .class = &dra7xx_gpio_hwmod_class,
847 .clkdm_name = "l4per_clkdm",
848 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
849 .main_clk = "l3_iclk_div",
850 .prcm = {
851 .omap4 = {
852 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
853 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
854 .modulemode = MODULEMODE_HWCTRL,
855 },
856 },
857 .opt_clks = gpio2_opt_clks,
858 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
859 };
860
861 /* gpio3 */
862 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
863 { .role = "dbclk", .clk = "gpio3_dbclk" },
864 };
865
866 static struct omap_hwmod dra7xx_gpio3_hwmod = {
867 .name = "gpio3",
868 .class = &dra7xx_gpio_hwmod_class,
869 .clkdm_name = "l4per_clkdm",
870 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
871 .main_clk = "l3_iclk_div",
872 .prcm = {
873 .omap4 = {
874 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
875 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
876 .modulemode = MODULEMODE_HWCTRL,
877 },
878 },
879 .opt_clks = gpio3_opt_clks,
880 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
881 };
882
883 /* gpio4 */
884 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
885 { .role = "dbclk", .clk = "gpio4_dbclk" },
886 };
887
888 static struct omap_hwmod dra7xx_gpio4_hwmod = {
889 .name = "gpio4",
890 .class = &dra7xx_gpio_hwmod_class,
891 .clkdm_name = "l4per_clkdm",
892 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
893 .main_clk = "l3_iclk_div",
894 .prcm = {
895 .omap4 = {
896 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
897 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
898 .modulemode = MODULEMODE_HWCTRL,
899 },
900 },
901 .opt_clks = gpio4_opt_clks,
902 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
903 };
904
905 /* gpio5 */
906 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
907 { .role = "dbclk", .clk = "gpio5_dbclk" },
908 };
909
910 static struct omap_hwmod dra7xx_gpio5_hwmod = {
911 .name = "gpio5",
912 .class = &dra7xx_gpio_hwmod_class,
913 .clkdm_name = "l4per_clkdm",
914 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
915 .main_clk = "l3_iclk_div",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
919 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
920 .modulemode = MODULEMODE_HWCTRL,
921 },
922 },
923 .opt_clks = gpio5_opt_clks,
924 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
925 };
926
927 /* gpio6 */
928 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
929 { .role = "dbclk", .clk = "gpio6_dbclk" },
930 };
931
932 static struct omap_hwmod dra7xx_gpio6_hwmod = {
933 .name = "gpio6",
934 .class = &dra7xx_gpio_hwmod_class,
935 .clkdm_name = "l4per_clkdm",
936 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
937 .main_clk = "l3_iclk_div",
938 .prcm = {
939 .omap4 = {
940 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
941 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
942 .modulemode = MODULEMODE_HWCTRL,
943 },
944 },
945 .opt_clks = gpio6_opt_clks,
946 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
947 };
948
949 /* gpio7 */
950 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
951 { .role = "dbclk", .clk = "gpio7_dbclk" },
952 };
953
954 static struct omap_hwmod dra7xx_gpio7_hwmod = {
955 .name = "gpio7",
956 .class = &dra7xx_gpio_hwmod_class,
957 .clkdm_name = "l4per_clkdm",
958 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
959 .main_clk = "l3_iclk_div",
960 .prcm = {
961 .omap4 = {
962 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
963 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
964 .modulemode = MODULEMODE_HWCTRL,
965 },
966 },
967 .opt_clks = gpio7_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
969 };
970
971 /* gpio8 */
972 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
973 { .role = "dbclk", .clk = "gpio8_dbclk" },
974 };
975
976 static struct omap_hwmod dra7xx_gpio8_hwmod = {
977 .name = "gpio8",
978 .class = &dra7xx_gpio_hwmod_class,
979 .clkdm_name = "l4per_clkdm",
980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
981 .main_clk = "l3_iclk_div",
982 .prcm = {
983 .omap4 = {
984 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
985 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
986 .modulemode = MODULEMODE_HWCTRL,
987 },
988 },
989 .opt_clks = gpio8_opt_clks,
990 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
991 };
992
993 /*
994 * 'gpmc' class
995 *
996 */
997
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999 .rev_offs = 0x0000,
1000 .sysc_offs = 0x0010,
1001 .syss_offs = 0x0014,
1002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1005 .sysc_fields = &omap_hwmod_sysc_type1,
1006 };
1007
1008 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1009 .name = "gpmc",
1010 .sysc = &dra7xx_gpmc_sysc,
1011 };
1012
1013 /* gpmc */
1014
1015 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1016 .name = "gpmc",
1017 .class = &dra7xx_gpmc_hwmod_class,
1018 .clkdm_name = "l3main1_clkdm",
1019 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1020 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1021 .main_clk = "l3_iclk_div",
1022 .prcm = {
1023 .omap4 = {
1024 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1025 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1026 .modulemode = MODULEMODE_HWCTRL,
1027 },
1028 },
1029 };
1030
1031 /*
1032 * 'hdq1w' class
1033 *
1034 */
1035
1036 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1037 .rev_offs = 0x0000,
1038 .sysc_offs = 0x0014,
1039 .syss_offs = 0x0018,
1040 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1041 SYSS_HAS_RESET_STATUS),
1042 .sysc_fields = &omap_hwmod_sysc_type1,
1043 };
1044
1045 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1046 .name = "hdq1w",
1047 .sysc = &dra7xx_hdq1w_sysc,
1048 };
1049
1050 /* hdq1w */
1051
1052 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1053 .name = "hdq1w",
1054 .class = &dra7xx_hdq1w_hwmod_class,
1055 .clkdm_name = "l4per_clkdm",
1056 .flags = HWMOD_INIT_NO_RESET,
1057 .main_clk = "func_12m_fclk",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1062 .modulemode = MODULEMODE_SWCTRL,
1063 },
1064 },
1065 };
1066
1067 /*
1068 * 'i2c' class
1069 *
1070 */
1071
1072 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1073 .sysc_offs = 0x0010,
1074 .syss_offs = 0x0090,
1075 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1076 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1077 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1079 SIDLE_SMART_WKUP),
1080 .sysc_fields = &omap_hwmod_sysc_type1,
1081 };
1082
1083 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1084 .name = "i2c",
1085 .sysc = &dra7xx_i2c_sysc,
1086 .reset = &omap_i2c_reset,
1087 .rev = OMAP_I2C_IP_VERSION_2,
1088 };
1089
1090 /* i2c1 */
1091 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1092 .name = "i2c1",
1093 .class = &dra7xx_i2c_hwmod_class,
1094 .clkdm_name = "l4per_clkdm",
1095 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1096 .main_clk = "func_96m_fclk",
1097 .prcm = {
1098 .omap4 = {
1099 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1100 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1101 .modulemode = MODULEMODE_SWCTRL,
1102 },
1103 },
1104 };
1105
1106 /* i2c2 */
1107 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1108 .name = "i2c2",
1109 .class = &dra7xx_i2c_hwmod_class,
1110 .clkdm_name = "l4per_clkdm",
1111 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1112 .main_clk = "func_96m_fclk",
1113 .prcm = {
1114 .omap4 = {
1115 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1116 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1117 .modulemode = MODULEMODE_SWCTRL,
1118 },
1119 },
1120 };
1121
1122 /* i2c3 */
1123 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1124 .name = "i2c3",
1125 .class = &dra7xx_i2c_hwmod_class,
1126 .clkdm_name = "l4per_clkdm",
1127 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1128 .main_clk = "func_96m_fclk",
1129 .prcm = {
1130 .omap4 = {
1131 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1132 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1133 .modulemode = MODULEMODE_SWCTRL,
1134 },
1135 },
1136 };
1137
1138 /* i2c4 */
1139 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1140 .name = "i2c4",
1141 .class = &dra7xx_i2c_hwmod_class,
1142 .clkdm_name = "l4per_clkdm",
1143 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1144 .main_clk = "func_96m_fclk",
1145 .prcm = {
1146 .omap4 = {
1147 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1148 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1149 .modulemode = MODULEMODE_SWCTRL,
1150 },
1151 },
1152 };
1153
1154 /* i2c5 */
1155 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1156 .name = "i2c5",
1157 .class = &dra7xx_i2c_hwmod_class,
1158 .clkdm_name = "ipu_clkdm",
1159 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1160 .main_clk = "func_96m_fclk",
1161 .prcm = {
1162 .omap4 = {
1163 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1164 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1165 .modulemode = MODULEMODE_SWCTRL,
1166 },
1167 },
1168 };
1169
1170 /*
1171 * 'mailbox' class
1172 *
1173 */
1174
1175 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1176 .rev_offs = 0x0000,
1177 .sysc_offs = 0x0010,
1178 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1179 SYSC_HAS_SOFTRESET),
1180 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1181 .sysc_fields = &omap_hwmod_sysc_type2,
1182 };
1183
1184 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1185 .name = "mailbox",
1186 .sysc = &dra7xx_mailbox_sysc,
1187 };
1188
1189 /* mailbox1 */
1190 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1191 .name = "mailbox1",
1192 .class = &dra7xx_mailbox_hwmod_class,
1193 .clkdm_name = "l4cfg_clkdm",
1194 .prcm = {
1195 .omap4 = {
1196 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1197 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1198 },
1199 },
1200 };
1201
1202 /* mailbox2 */
1203 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1204 .name = "mailbox2",
1205 .class = &dra7xx_mailbox_hwmod_class,
1206 .clkdm_name = "l4cfg_clkdm",
1207 .prcm = {
1208 .omap4 = {
1209 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1210 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1211 },
1212 },
1213 };
1214
1215 /* mailbox3 */
1216 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1217 .name = "mailbox3",
1218 .class = &dra7xx_mailbox_hwmod_class,
1219 .clkdm_name = "l4cfg_clkdm",
1220 .prcm = {
1221 .omap4 = {
1222 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1223 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1224 },
1225 },
1226 };
1227
1228 /* mailbox4 */
1229 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1230 .name = "mailbox4",
1231 .class = &dra7xx_mailbox_hwmod_class,
1232 .clkdm_name = "l4cfg_clkdm",
1233 .prcm = {
1234 .omap4 = {
1235 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1236 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1237 },
1238 },
1239 };
1240
1241 /* mailbox5 */
1242 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1243 .name = "mailbox5",
1244 .class = &dra7xx_mailbox_hwmod_class,
1245 .clkdm_name = "l4cfg_clkdm",
1246 .prcm = {
1247 .omap4 = {
1248 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1249 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1250 },
1251 },
1252 };
1253
1254 /* mailbox6 */
1255 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1256 .name = "mailbox6",
1257 .class = &dra7xx_mailbox_hwmod_class,
1258 .clkdm_name = "l4cfg_clkdm",
1259 .prcm = {
1260 .omap4 = {
1261 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1262 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1263 },
1264 },
1265 };
1266
1267 /* mailbox7 */
1268 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1269 .name = "mailbox7",
1270 .class = &dra7xx_mailbox_hwmod_class,
1271 .clkdm_name = "l4cfg_clkdm",
1272 .prcm = {
1273 .omap4 = {
1274 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1275 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1276 },
1277 },
1278 };
1279
1280 /* mailbox8 */
1281 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1282 .name = "mailbox8",
1283 .class = &dra7xx_mailbox_hwmod_class,
1284 .clkdm_name = "l4cfg_clkdm",
1285 .prcm = {
1286 .omap4 = {
1287 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1288 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1289 },
1290 },
1291 };
1292
1293 /* mailbox9 */
1294 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1295 .name = "mailbox9",
1296 .class = &dra7xx_mailbox_hwmod_class,
1297 .clkdm_name = "l4cfg_clkdm",
1298 .prcm = {
1299 .omap4 = {
1300 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1301 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1302 },
1303 },
1304 };
1305
1306 /* mailbox10 */
1307 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1308 .name = "mailbox10",
1309 .class = &dra7xx_mailbox_hwmod_class,
1310 .clkdm_name = "l4cfg_clkdm",
1311 .prcm = {
1312 .omap4 = {
1313 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1314 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1315 },
1316 },
1317 };
1318
1319 /* mailbox11 */
1320 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1321 .name = "mailbox11",
1322 .class = &dra7xx_mailbox_hwmod_class,
1323 .clkdm_name = "l4cfg_clkdm",
1324 .prcm = {
1325 .omap4 = {
1326 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1327 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1328 },
1329 },
1330 };
1331
1332 /* mailbox12 */
1333 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1334 .name = "mailbox12",
1335 .class = &dra7xx_mailbox_hwmod_class,
1336 .clkdm_name = "l4cfg_clkdm",
1337 .prcm = {
1338 .omap4 = {
1339 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1340 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1341 },
1342 },
1343 };
1344
1345 /* mailbox13 */
1346 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1347 .name = "mailbox13",
1348 .class = &dra7xx_mailbox_hwmod_class,
1349 .clkdm_name = "l4cfg_clkdm",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1353 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1354 },
1355 },
1356 };
1357
1358 /*
1359 * 'mcspi' class
1360 *
1361 */
1362
1363 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1364 .rev_offs = 0x0000,
1365 .sysc_offs = 0x0010,
1366 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1367 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1368 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1369 SIDLE_SMART_WKUP),
1370 .sysc_fields = &omap_hwmod_sysc_type2,
1371 };
1372
1373 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1374 .name = "mcspi",
1375 .sysc = &dra7xx_mcspi_sysc,
1376 };
1377
1378 /* mcspi1 */
1379 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1380 .name = "mcspi1",
1381 .class = &dra7xx_mcspi_hwmod_class,
1382 .clkdm_name = "l4per_clkdm",
1383 .main_clk = "func_48m_fclk",
1384 .prcm = {
1385 .omap4 = {
1386 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1387 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1388 .modulemode = MODULEMODE_SWCTRL,
1389 },
1390 },
1391 };
1392
1393 /* mcspi2 */
1394 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1395 .name = "mcspi2",
1396 .class = &dra7xx_mcspi_hwmod_class,
1397 .clkdm_name = "l4per_clkdm",
1398 .main_clk = "func_48m_fclk",
1399 .prcm = {
1400 .omap4 = {
1401 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1402 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1403 .modulemode = MODULEMODE_SWCTRL,
1404 },
1405 },
1406 };
1407
1408 /* mcspi3 */
1409 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1410 .name = "mcspi3",
1411 .class = &dra7xx_mcspi_hwmod_class,
1412 .clkdm_name = "l4per_clkdm",
1413 .main_clk = "func_48m_fclk",
1414 .prcm = {
1415 .omap4 = {
1416 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1417 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1418 .modulemode = MODULEMODE_SWCTRL,
1419 },
1420 },
1421 };
1422
1423 /* mcspi4 */
1424 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1425 .name = "mcspi4",
1426 .class = &dra7xx_mcspi_hwmod_class,
1427 .clkdm_name = "l4per_clkdm",
1428 .main_clk = "func_48m_fclk",
1429 .prcm = {
1430 .omap4 = {
1431 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1432 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1433 .modulemode = MODULEMODE_SWCTRL,
1434 },
1435 },
1436 };
1437
1438 /*
1439 * 'mcasp' class
1440 *
1441 */
1442 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1443 .sysc_offs = 0x0004,
1444 .sysc_flags = SYSC_HAS_SIDLEMODE,
1445 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1446 .sysc_fields = &omap_hwmod_sysc_type3,
1447 };
1448
1449 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1450 .name = "mcasp",
1451 .sysc = &dra7xx_mcasp_sysc,
1452 };
1453
1454 /* mcasp1 */
1455 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1456 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1457 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1458 };
1459
1460 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1461 .name = "mcasp1",
1462 .class = &dra7xx_mcasp_hwmod_class,
1463 .clkdm_name = "ipu_clkdm",
1464 .main_clk = "mcasp1_aux_gfclk_mux",
1465 .flags = HWMOD_OPT_CLKS_NEEDED,
1466 .prcm = {
1467 .omap4 = {
1468 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1469 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1470 .modulemode = MODULEMODE_SWCTRL,
1471 },
1472 },
1473 .opt_clks = mcasp1_opt_clks,
1474 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1475 };
1476
1477 /* mcasp2 */
1478 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1479 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1480 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1481 };
1482
1483 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1484 .name = "mcasp2",
1485 .class = &dra7xx_mcasp_hwmod_class,
1486 .clkdm_name = "l4per2_clkdm",
1487 .main_clk = "mcasp2_aux_gfclk_mux",
1488 .flags = HWMOD_OPT_CLKS_NEEDED,
1489 .prcm = {
1490 .omap4 = {
1491 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1492 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1493 .modulemode = MODULEMODE_SWCTRL,
1494 },
1495 },
1496 .opt_clks = mcasp2_opt_clks,
1497 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1498 };
1499
1500 /* mcasp3 */
1501 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1502 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1503 };
1504
1505 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1506 .name = "mcasp3",
1507 .class = &dra7xx_mcasp_hwmod_class,
1508 .clkdm_name = "l4per2_clkdm",
1509 .main_clk = "mcasp3_aux_gfclk_mux",
1510 .flags = HWMOD_OPT_CLKS_NEEDED,
1511 .prcm = {
1512 .omap4 = {
1513 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1514 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1515 .modulemode = MODULEMODE_SWCTRL,
1516 },
1517 },
1518 .opt_clks = mcasp3_opt_clks,
1519 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1520 };
1521
1522 /* mcasp4 */
1523 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1524 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1525 };
1526
1527 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1528 .name = "mcasp4",
1529 .class = &dra7xx_mcasp_hwmod_class,
1530 .clkdm_name = "l4per2_clkdm",
1531 .main_clk = "mcasp4_aux_gfclk_mux",
1532 .flags = HWMOD_OPT_CLKS_NEEDED,
1533 .prcm = {
1534 .omap4 = {
1535 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1536 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1537 .modulemode = MODULEMODE_SWCTRL,
1538 },
1539 },
1540 .opt_clks = mcasp4_opt_clks,
1541 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1542 };
1543
1544 /* mcasp5 */
1545 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1546 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1547 };
1548
1549 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1550 .name = "mcasp5",
1551 .class = &dra7xx_mcasp_hwmod_class,
1552 .clkdm_name = "l4per2_clkdm",
1553 .main_clk = "mcasp5_aux_gfclk_mux",
1554 .flags = HWMOD_OPT_CLKS_NEEDED,
1555 .prcm = {
1556 .omap4 = {
1557 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1558 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1559 .modulemode = MODULEMODE_SWCTRL,
1560 },
1561 },
1562 .opt_clks = mcasp5_opt_clks,
1563 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1564 };
1565
1566 /* mcasp6 */
1567 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1568 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1569 };
1570
1571 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1572 .name = "mcasp6",
1573 .class = &dra7xx_mcasp_hwmod_class,
1574 .clkdm_name = "l4per2_clkdm",
1575 .main_clk = "mcasp6_aux_gfclk_mux",
1576 .flags = HWMOD_OPT_CLKS_NEEDED,
1577 .prcm = {
1578 .omap4 = {
1579 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1580 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1581 .modulemode = MODULEMODE_SWCTRL,
1582 },
1583 },
1584 .opt_clks = mcasp6_opt_clks,
1585 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1586 };
1587
1588 /* mcasp7 */
1589 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1590 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1591 };
1592
1593 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1594 .name = "mcasp7",
1595 .class = &dra7xx_mcasp_hwmod_class,
1596 .clkdm_name = "l4per2_clkdm",
1597 .main_clk = "mcasp7_aux_gfclk_mux",
1598 .flags = HWMOD_OPT_CLKS_NEEDED,
1599 .prcm = {
1600 .omap4 = {
1601 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1602 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1603 .modulemode = MODULEMODE_SWCTRL,
1604 },
1605 },
1606 .opt_clks = mcasp7_opt_clks,
1607 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1608 };
1609
1610 /* mcasp8 */
1611 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1612 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1613 };
1614
1615 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1616 .name = "mcasp8",
1617 .class = &dra7xx_mcasp_hwmod_class,
1618 .clkdm_name = "l4per2_clkdm",
1619 .main_clk = "mcasp8_aux_gfclk_mux",
1620 .flags = HWMOD_OPT_CLKS_NEEDED,
1621 .prcm = {
1622 .omap4 = {
1623 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1624 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1625 .modulemode = MODULEMODE_SWCTRL,
1626 },
1627 },
1628 .opt_clks = mcasp8_opt_clks,
1629 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1630 };
1631
1632 /*
1633 * 'mmc' class
1634 *
1635 */
1636
1637 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1638 .rev_offs = 0x0000,
1639 .sysc_offs = 0x0010,
1640 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1641 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1642 SYSC_HAS_SOFTRESET),
1643 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1644 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1645 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1646 .sysc_fields = &omap_hwmod_sysc_type2,
1647 };
1648
1649 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1650 .name = "mmc",
1651 .sysc = &dra7xx_mmc_sysc,
1652 };
1653
1654 /* mmc1 */
1655 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1656 { .role = "clk32k", .clk = "mmc1_clk32k" },
1657 };
1658
1659 /* mmc1 dev_attr */
1660 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1661 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1662 };
1663
1664 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1665 .name = "mmc1",
1666 .class = &dra7xx_mmc_hwmod_class,
1667 .clkdm_name = "l3init_clkdm",
1668 .main_clk = "mmc1_fclk_div",
1669 .prcm = {
1670 .omap4 = {
1671 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1672 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1673 .modulemode = MODULEMODE_SWCTRL,
1674 },
1675 },
1676 .opt_clks = mmc1_opt_clks,
1677 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1678 .dev_attr = &mmc1_dev_attr,
1679 };
1680
1681 /* mmc2 */
1682 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1683 { .role = "clk32k", .clk = "mmc2_clk32k" },
1684 };
1685
1686 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1687 .name = "mmc2",
1688 .class = &dra7xx_mmc_hwmod_class,
1689 .clkdm_name = "l3init_clkdm",
1690 .main_clk = "mmc2_fclk_div",
1691 .prcm = {
1692 .omap4 = {
1693 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1694 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1695 .modulemode = MODULEMODE_SWCTRL,
1696 },
1697 },
1698 .opt_clks = mmc2_opt_clks,
1699 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1700 };
1701
1702 /* mmc3 */
1703 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1704 { .role = "clk32k", .clk = "mmc3_clk32k" },
1705 };
1706
1707 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1708 .name = "mmc3",
1709 .class = &dra7xx_mmc_hwmod_class,
1710 .clkdm_name = "l4per_clkdm",
1711 .main_clk = "mmc3_gfclk_div",
1712 .prcm = {
1713 .omap4 = {
1714 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1715 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1716 .modulemode = MODULEMODE_SWCTRL,
1717 },
1718 },
1719 .opt_clks = mmc3_opt_clks,
1720 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1721 };
1722
1723 /* mmc4 */
1724 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1725 { .role = "clk32k", .clk = "mmc4_clk32k" },
1726 };
1727
1728 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1729 .name = "mmc4",
1730 .class = &dra7xx_mmc_hwmod_class,
1731 .clkdm_name = "l4per_clkdm",
1732 .main_clk = "mmc4_gfclk_div",
1733 .prcm = {
1734 .omap4 = {
1735 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1736 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1737 .modulemode = MODULEMODE_SWCTRL,
1738 },
1739 },
1740 .opt_clks = mmc4_opt_clks,
1741 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1742 };
1743
1744 /*
1745 * 'mpu' class
1746 *
1747 */
1748
1749 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1750 .name = "mpu",
1751 };
1752
1753 /* mpu */
1754 static struct omap_hwmod dra7xx_mpu_hwmod = {
1755 .name = "mpu",
1756 .class = &dra7xx_mpu_hwmod_class,
1757 .clkdm_name = "mpu_clkdm",
1758 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1759 .main_clk = "dpll_mpu_m2_ck",
1760 .prcm = {
1761 .omap4 = {
1762 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1763 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1764 },
1765 },
1766 };
1767
1768 /*
1769 * 'ocp2scp' class
1770 *
1771 */
1772
1773 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1774 .rev_offs = 0x0000,
1775 .sysc_offs = 0x0010,
1776 .syss_offs = 0x0014,
1777 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1778 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1779 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1780 .sysc_fields = &omap_hwmod_sysc_type1,
1781 };
1782
1783 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1784 .name = "ocp2scp",
1785 .sysc = &dra7xx_ocp2scp_sysc,
1786 };
1787
1788 /* ocp2scp1 */
1789 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1790 .name = "ocp2scp1",
1791 .class = &dra7xx_ocp2scp_hwmod_class,
1792 .clkdm_name = "l3init_clkdm",
1793 .main_clk = "l4_root_clk_div",
1794 .prcm = {
1795 .omap4 = {
1796 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1797 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1798 .modulemode = MODULEMODE_HWCTRL,
1799 },
1800 },
1801 };
1802
1803 /* ocp2scp3 */
1804 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1805 .name = "ocp2scp3",
1806 .class = &dra7xx_ocp2scp_hwmod_class,
1807 .clkdm_name = "l3init_clkdm",
1808 .main_clk = "l4_root_clk_div",
1809 .prcm = {
1810 .omap4 = {
1811 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1812 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1813 .modulemode = MODULEMODE_HWCTRL,
1814 },
1815 },
1816 };
1817
1818 /*
1819 * 'PCIE' class
1820 *
1821 */
1822
1823 /*
1824 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1825 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1826 * associated with an IP automatically leaving the driver to handle that
1827 * by itself. This does not work for PCIeSS which needs the reset lines
1828 * deasserted for the driver to start accessing registers.
1829 *
1830 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1831 * lines after asserting them.
1832 */
1833 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1834 {
1835 int i;
1836
1837 for (i = 0; i < oh->rst_lines_cnt; i++) {
1838 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1839 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1840 }
1841
1842 return 0;
1843 }
1844
1845 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1846 .name = "pcie",
1847 .reset = dra7xx_pciess_reset,
1848 };
1849
1850 /* pcie1 */
1851 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1852 { .name = "pcie", .rst_shift = 0 },
1853 };
1854
1855 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1856 .name = "pcie1",
1857 .class = &dra7xx_pciess_hwmod_class,
1858 .clkdm_name = "pcie_clkdm",
1859 .rst_lines = dra7xx_pciess1_resets,
1860 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1861 .main_clk = "l4_root_clk_div",
1862 .prcm = {
1863 .omap4 = {
1864 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1865 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1866 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1867 .modulemode = MODULEMODE_SWCTRL,
1868 },
1869 },
1870 };
1871
1872 /* pcie2 */
1873 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1874 { .name = "pcie", .rst_shift = 1 },
1875 };
1876
1877 /* pcie2 */
1878 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1879 .name = "pcie2",
1880 .class = &dra7xx_pciess_hwmod_class,
1881 .clkdm_name = "pcie_clkdm",
1882 .rst_lines = dra7xx_pciess2_resets,
1883 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1884 .main_clk = "l4_root_clk_div",
1885 .prcm = {
1886 .omap4 = {
1887 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1888 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1889 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1890 .modulemode = MODULEMODE_SWCTRL,
1891 },
1892 },
1893 };
1894
1895 /*
1896 * 'qspi' class
1897 *
1898 */
1899
1900 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1901 .sysc_offs = 0x0010,
1902 .sysc_flags = SYSC_HAS_SIDLEMODE,
1903 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1904 SIDLE_SMART_WKUP),
1905 .sysc_fields = &omap_hwmod_sysc_type2,
1906 };
1907
1908 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1909 .name = "qspi",
1910 .sysc = &dra7xx_qspi_sysc,
1911 };
1912
1913 /* qspi */
1914 static struct omap_hwmod dra7xx_qspi_hwmod = {
1915 .name = "qspi",
1916 .class = &dra7xx_qspi_hwmod_class,
1917 .clkdm_name = "l4per2_clkdm",
1918 .main_clk = "qspi_gfclk_div",
1919 .prcm = {
1920 .omap4 = {
1921 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1922 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1923 .modulemode = MODULEMODE_SWCTRL,
1924 },
1925 },
1926 };
1927
1928 /*
1929 * 'rtcss' class
1930 *
1931 */
1932 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1933 .sysc_offs = 0x0078,
1934 .sysc_flags = SYSC_HAS_SIDLEMODE,
1935 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1936 SIDLE_SMART_WKUP),
1937 .sysc_fields = &omap_hwmod_sysc_type3,
1938 };
1939
1940 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1941 .name = "rtcss",
1942 .sysc = &dra7xx_rtcss_sysc,
1943 .unlock = &omap_hwmod_rtc_unlock,
1944 .lock = &omap_hwmod_rtc_lock,
1945 };
1946
1947 /* rtcss */
1948 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1949 .name = "rtcss",
1950 .class = &dra7xx_rtcss_hwmod_class,
1951 .clkdm_name = "rtc_clkdm",
1952 .main_clk = "sys_32k_ck",
1953 .prcm = {
1954 .omap4 = {
1955 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1956 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1957 .modulemode = MODULEMODE_SWCTRL,
1958 },
1959 },
1960 };
1961
1962 /*
1963 * 'sata' class
1964 *
1965 */
1966
1967 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1968 .sysc_offs = 0x0000,
1969 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1970 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1971 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1972 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1973 .sysc_fields = &omap_hwmod_sysc_type2,
1974 };
1975
1976 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1977 .name = "sata",
1978 .sysc = &dra7xx_sata_sysc,
1979 };
1980
1981 /* sata */
1982
1983 static struct omap_hwmod dra7xx_sata_hwmod = {
1984 .name = "sata",
1985 .class = &dra7xx_sata_hwmod_class,
1986 .clkdm_name = "l3init_clkdm",
1987 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1988 .main_clk = "func_48m_fclk",
1989 .mpu_rt_idx = 1,
1990 .prcm = {
1991 .omap4 = {
1992 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1993 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1994 .modulemode = MODULEMODE_SWCTRL,
1995 },
1996 },
1997 };
1998
1999 /*
2000 * 'smartreflex' class
2001 *
2002 */
2003
2004 /* The IP is not compliant to type1 / type2 scheme */
2005 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2006 .sysc_offs = 0x0038,
2007 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2009 SIDLE_SMART_WKUP),
2010 .sysc_fields = &omap36xx_sr_sysc_fields,
2011 };
2012
2013 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2014 .name = "smartreflex",
2015 .sysc = &dra7xx_smartreflex_sysc,
2016 .rev = 2,
2017 };
2018
2019 /* smartreflex_core */
2020 /* smartreflex_core dev_attr */
2021 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2022 .sensor_voltdm_name = "core",
2023 };
2024
2025 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2026 .name = "smartreflex_core",
2027 .class = &dra7xx_smartreflex_hwmod_class,
2028 .clkdm_name = "coreaon_clkdm",
2029 .main_clk = "wkupaon_iclk_mux",
2030 .prcm = {
2031 .omap4 = {
2032 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2033 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2034 .modulemode = MODULEMODE_SWCTRL,
2035 },
2036 },
2037 .dev_attr = &smartreflex_core_dev_attr,
2038 };
2039
2040 /* smartreflex_mpu */
2041 /* smartreflex_mpu dev_attr */
2042 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2043 .sensor_voltdm_name = "mpu",
2044 };
2045
2046 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2047 .name = "smartreflex_mpu",
2048 .class = &dra7xx_smartreflex_hwmod_class,
2049 .clkdm_name = "coreaon_clkdm",
2050 .main_clk = "wkupaon_iclk_mux",
2051 .prcm = {
2052 .omap4 = {
2053 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2054 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2055 .modulemode = MODULEMODE_SWCTRL,
2056 },
2057 },
2058 .dev_attr = &smartreflex_mpu_dev_attr,
2059 };
2060
2061 /*
2062 * 'spinlock' class
2063 *
2064 */
2065
2066 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2067 .rev_offs = 0x0000,
2068 .sysc_offs = 0x0010,
2069 .syss_offs = 0x0014,
2070 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2071 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2072 SYSS_HAS_RESET_STATUS),
2073 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2074 .sysc_fields = &omap_hwmod_sysc_type1,
2075 };
2076
2077 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2078 .name = "spinlock",
2079 .sysc = &dra7xx_spinlock_sysc,
2080 };
2081
2082 /* spinlock */
2083 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2084 .name = "spinlock",
2085 .class = &dra7xx_spinlock_hwmod_class,
2086 .clkdm_name = "l4cfg_clkdm",
2087 .main_clk = "l3_iclk_div",
2088 .prcm = {
2089 .omap4 = {
2090 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2091 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2092 },
2093 },
2094 };
2095
2096 /*
2097 * 'timer' class
2098 *
2099 * This class contains several variants: ['timer_1ms', 'timer_secure',
2100 * 'timer']
2101 */
2102
2103 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2104 .rev_offs = 0x0000,
2105 .sysc_offs = 0x0010,
2106 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2107 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2108 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2109 SIDLE_SMART_WKUP),
2110 .sysc_fields = &omap_hwmod_sysc_type2,
2111 };
2112
2113 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2114 .name = "timer",
2115 .sysc = &dra7xx_timer_1ms_sysc,
2116 };
2117
2118 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2119 .rev_offs = 0x0000,
2120 .sysc_offs = 0x0010,
2121 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2122 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2123 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2124 SIDLE_SMART_WKUP),
2125 .sysc_fields = &omap_hwmod_sysc_type2,
2126 };
2127
2128 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2129 .name = "timer",
2130 .sysc = &dra7xx_timer_sysc,
2131 };
2132
2133 /* timer1 */
2134 static struct omap_hwmod dra7xx_timer1_hwmod = {
2135 .name = "timer1",
2136 .class = &dra7xx_timer_1ms_hwmod_class,
2137 .clkdm_name = "wkupaon_clkdm",
2138 .main_clk = "timer1_gfclk_mux",
2139 .prcm = {
2140 .omap4 = {
2141 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2142 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2143 .modulemode = MODULEMODE_SWCTRL,
2144 },
2145 },
2146 };
2147
2148 /* timer2 */
2149 static struct omap_hwmod dra7xx_timer2_hwmod = {
2150 .name = "timer2",
2151 .class = &dra7xx_timer_1ms_hwmod_class,
2152 .clkdm_name = "l4per_clkdm",
2153 .main_clk = "timer2_gfclk_mux",
2154 .prcm = {
2155 .omap4 = {
2156 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2157 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2158 .modulemode = MODULEMODE_SWCTRL,
2159 },
2160 },
2161 };
2162
2163 /* timer3 */
2164 static struct omap_hwmod dra7xx_timer3_hwmod = {
2165 .name = "timer3",
2166 .class = &dra7xx_timer_hwmod_class,
2167 .clkdm_name = "l4per_clkdm",
2168 .main_clk = "timer3_gfclk_mux",
2169 .prcm = {
2170 .omap4 = {
2171 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2172 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2173 .modulemode = MODULEMODE_SWCTRL,
2174 },
2175 },
2176 };
2177
2178 /* timer4 */
2179 static struct omap_hwmod dra7xx_timer4_hwmod = {
2180 .name = "timer4",
2181 .class = &dra7xx_timer_hwmod_class,
2182 .clkdm_name = "l4per_clkdm",
2183 .main_clk = "timer4_gfclk_mux",
2184 .prcm = {
2185 .omap4 = {
2186 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2187 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2188 .modulemode = MODULEMODE_SWCTRL,
2189 },
2190 },
2191 };
2192
2193 /* timer5 */
2194 static struct omap_hwmod dra7xx_timer5_hwmod = {
2195 .name = "timer5",
2196 .class = &dra7xx_timer_hwmod_class,
2197 .clkdm_name = "ipu_clkdm",
2198 .main_clk = "timer5_gfclk_mux",
2199 .prcm = {
2200 .omap4 = {
2201 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2202 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2203 .modulemode = MODULEMODE_SWCTRL,
2204 },
2205 },
2206 };
2207
2208 /* timer6 */
2209 static struct omap_hwmod dra7xx_timer6_hwmod = {
2210 .name = "timer6",
2211 .class = &dra7xx_timer_hwmod_class,
2212 .clkdm_name = "ipu_clkdm",
2213 .main_clk = "timer6_gfclk_mux",
2214 .prcm = {
2215 .omap4 = {
2216 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2217 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2218 .modulemode = MODULEMODE_SWCTRL,
2219 },
2220 },
2221 };
2222
2223 /* timer7 */
2224 static struct omap_hwmod dra7xx_timer7_hwmod = {
2225 .name = "timer7",
2226 .class = &dra7xx_timer_hwmod_class,
2227 .clkdm_name = "ipu_clkdm",
2228 .main_clk = "timer7_gfclk_mux",
2229 .prcm = {
2230 .omap4 = {
2231 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2232 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2233 .modulemode = MODULEMODE_SWCTRL,
2234 },
2235 },
2236 };
2237
2238 /* timer8 */
2239 static struct omap_hwmod dra7xx_timer8_hwmod = {
2240 .name = "timer8",
2241 .class = &dra7xx_timer_hwmod_class,
2242 .clkdm_name = "ipu_clkdm",
2243 .main_clk = "timer8_gfclk_mux",
2244 .prcm = {
2245 .omap4 = {
2246 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2247 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2248 .modulemode = MODULEMODE_SWCTRL,
2249 },
2250 },
2251 };
2252
2253 /* timer9 */
2254 static struct omap_hwmod dra7xx_timer9_hwmod = {
2255 .name = "timer9",
2256 .class = &dra7xx_timer_hwmod_class,
2257 .clkdm_name = "l4per_clkdm",
2258 .main_clk = "timer9_gfclk_mux",
2259 .prcm = {
2260 .omap4 = {
2261 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2262 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2263 .modulemode = MODULEMODE_SWCTRL,
2264 },
2265 },
2266 };
2267
2268 /* timer10 */
2269 static struct omap_hwmod dra7xx_timer10_hwmod = {
2270 .name = "timer10",
2271 .class = &dra7xx_timer_1ms_hwmod_class,
2272 .clkdm_name = "l4per_clkdm",
2273 .main_clk = "timer10_gfclk_mux",
2274 .prcm = {
2275 .omap4 = {
2276 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2277 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2278 .modulemode = MODULEMODE_SWCTRL,
2279 },
2280 },
2281 };
2282
2283 /* timer11 */
2284 static struct omap_hwmod dra7xx_timer11_hwmod = {
2285 .name = "timer11",
2286 .class = &dra7xx_timer_hwmod_class,
2287 .clkdm_name = "l4per_clkdm",
2288 .main_clk = "timer11_gfclk_mux",
2289 .prcm = {
2290 .omap4 = {
2291 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2292 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2293 .modulemode = MODULEMODE_SWCTRL,
2294 },
2295 },
2296 };
2297
2298 /* timer12 */
2299 static struct omap_hwmod dra7xx_timer12_hwmod = {
2300 .name = "timer12",
2301 .class = &dra7xx_timer_hwmod_class,
2302 .clkdm_name = "wkupaon_clkdm",
2303 .main_clk = "secure_32k_clk_src_ck",
2304 .prcm = {
2305 .omap4 = {
2306 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2307 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2308 },
2309 },
2310 };
2311
2312 /* timer13 */
2313 static struct omap_hwmod dra7xx_timer13_hwmod = {
2314 .name = "timer13",
2315 .class = &dra7xx_timer_hwmod_class,
2316 .clkdm_name = "l4per3_clkdm",
2317 .main_clk = "timer13_gfclk_mux",
2318 .prcm = {
2319 .omap4 = {
2320 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2321 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2322 .modulemode = MODULEMODE_SWCTRL,
2323 },
2324 },
2325 };
2326
2327 /* timer14 */
2328 static struct omap_hwmod dra7xx_timer14_hwmod = {
2329 .name = "timer14",
2330 .class = &dra7xx_timer_hwmod_class,
2331 .clkdm_name = "l4per3_clkdm",
2332 .main_clk = "timer14_gfclk_mux",
2333 .prcm = {
2334 .omap4 = {
2335 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2336 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2337 .modulemode = MODULEMODE_SWCTRL,
2338 },
2339 },
2340 };
2341
2342 /* timer15 */
2343 static struct omap_hwmod dra7xx_timer15_hwmod = {
2344 .name = "timer15",
2345 .class = &dra7xx_timer_hwmod_class,
2346 .clkdm_name = "l4per3_clkdm",
2347 .main_clk = "timer15_gfclk_mux",
2348 .prcm = {
2349 .omap4 = {
2350 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2351 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2352 .modulemode = MODULEMODE_SWCTRL,
2353 },
2354 },
2355 };
2356
2357 /* timer16 */
2358 static struct omap_hwmod dra7xx_timer16_hwmod = {
2359 .name = "timer16",
2360 .class = &dra7xx_timer_hwmod_class,
2361 .clkdm_name = "l4per3_clkdm",
2362 .main_clk = "timer16_gfclk_mux",
2363 .prcm = {
2364 .omap4 = {
2365 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2366 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2367 .modulemode = MODULEMODE_SWCTRL,
2368 },
2369 },
2370 };
2371
2372 /*
2373 * 'uart' class
2374 *
2375 */
2376
2377 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2378 .rev_offs = 0x0050,
2379 .sysc_offs = 0x0054,
2380 .syss_offs = 0x0058,
2381 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2382 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2383 SYSS_HAS_RESET_STATUS),
2384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2385 SIDLE_SMART_WKUP),
2386 .sysc_fields = &omap_hwmod_sysc_type1,
2387 };
2388
2389 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2390 .name = "uart",
2391 .sysc = &dra7xx_uart_sysc,
2392 };
2393
2394 /* uart1 */
2395 static struct omap_hwmod dra7xx_uart1_hwmod = {
2396 .name = "uart1",
2397 .class = &dra7xx_uart_hwmod_class,
2398 .clkdm_name = "l4per_clkdm",
2399 .main_clk = "uart1_gfclk_mux",
2400 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2401 .prcm = {
2402 .omap4 = {
2403 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2404 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2405 .modulemode = MODULEMODE_SWCTRL,
2406 },
2407 },
2408 };
2409
2410 /* uart2 */
2411 static struct omap_hwmod dra7xx_uart2_hwmod = {
2412 .name = "uart2",
2413 .class = &dra7xx_uart_hwmod_class,
2414 .clkdm_name = "l4per_clkdm",
2415 .main_clk = "uart2_gfclk_mux",
2416 .flags = HWMOD_SWSUP_SIDLE_ACT,
2417 .prcm = {
2418 .omap4 = {
2419 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2420 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2421 .modulemode = MODULEMODE_SWCTRL,
2422 },
2423 },
2424 };
2425
2426 /* uart3 */
2427 static struct omap_hwmod dra7xx_uart3_hwmod = {
2428 .name = "uart3",
2429 .class = &dra7xx_uart_hwmod_class,
2430 .clkdm_name = "l4per_clkdm",
2431 .main_clk = "uart3_gfclk_mux",
2432 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2433 .prcm = {
2434 .omap4 = {
2435 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2436 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2437 .modulemode = MODULEMODE_SWCTRL,
2438 },
2439 },
2440 };
2441
2442 /* uart4 */
2443 static struct omap_hwmod dra7xx_uart4_hwmod = {
2444 .name = "uart4",
2445 .class = &dra7xx_uart_hwmod_class,
2446 .clkdm_name = "l4per_clkdm",
2447 .main_clk = "uart4_gfclk_mux",
2448 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2449 .prcm = {
2450 .omap4 = {
2451 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2452 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2453 .modulemode = MODULEMODE_SWCTRL,
2454 },
2455 },
2456 };
2457
2458 /* uart5 */
2459 static struct omap_hwmod dra7xx_uart5_hwmod = {
2460 .name = "uart5",
2461 .class = &dra7xx_uart_hwmod_class,
2462 .clkdm_name = "l4per_clkdm",
2463 .main_clk = "uart5_gfclk_mux",
2464 .flags = HWMOD_SWSUP_SIDLE_ACT,
2465 .prcm = {
2466 .omap4 = {
2467 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2468 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2469 .modulemode = MODULEMODE_SWCTRL,
2470 },
2471 },
2472 };
2473
2474 /* uart6 */
2475 static struct omap_hwmod dra7xx_uart6_hwmod = {
2476 .name = "uart6",
2477 .class = &dra7xx_uart_hwmod_class,
2478 .clkdm_name = "ipu_clkdm",
2479 .main_clk = "uart6_gfclk_mux",
2480 .flags = HWMOD_SWSUP_SIDLE_ACT,
2481 .prcm = {
2482 .omap4 = {
2483 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2484 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2485 .modulemode = MODULEMODE_SWCTRL,
2486 },
2487 },
2488 };
2489
2490 /* uart7 */
2491 static struct omap_hwmod dra7xx_uart7_hwmod = {
2492 .name = "uart7",
2493 .class = &dra7xx_uart_hwmod_class,
2494 .clkdm_name = "l4per2_clkdm",
2495 .main_clk = "uart7_gfclk_mux",
2496 .flags = HWMOD_SWSUP_SIDLE_ACT,
2497 .prcm = {
2498 .omap4 = {
2499 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2500 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2501 .modulemode = MODULEMODE_SWCTRL,
2502 },
2503 },
2504 };
2505
2506 /* uart8 */
2507 static struct omap_hwmod dra7xx_uart8_hwmod = {
2508 .name = "uart8",
2509 .class = &dra7xx_uart_hwmod_class,
2510 .clkdm_name = "l4per2_clkdm",
2511 .main_clk = "uart8_gfclk_mux",
2512 .flags = HWMOD_SWSUP_SIDLE_ACT,
2513 .prcm = {
2514 .omap4 = {
2515 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2516 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2517 .modulemode = MODULEMODE_SWCTRL,
2518 },
2519 },
2520 };
2521
2522 /* uart9 */
2523 static struct omap_hwmod dra7xx_uart9_hwmod = {
2524 .name = "uart9",
2525 .class = &dra7xx_uart_hwmod_class,
2526 .clkdm_name = "l4per2_clkdm",
2527 .main_clk = "uart9_gfclk_mux",
2528 .flags = HWMOD_SWSUP_SIDLE_ACT,
2529 .prcm = {
2530 .omap4 = {
2531 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2532 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2533 .modulemode = MODULEMODE_SWCTRL,
2534 },
2535 },
2536 };
2537
2538 /* uart10 */
2539 static struct omap_hwmod dra7xx_uart10_hwmod = {
2540 .name = "uart10",
2541 .class = &dra7xx_uart_hwmod_class,
2542 .clkdm_name = "wkupaon_clkdm",
2543 .main_clk = "uart10_gfclk_mux",
2544 .flags = HWMOD_SWSUP_SIDLE_ACT,
2545 .prcm = {
2546 .omap4 = {
2547 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2548 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2549 .modulemode = MODULEMODE_SWCTRL,
2550 },
2551 },
2552 };
2553
2554 /* DES (the 'P' (public) device) */
2555 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2556 .rev_offs = 0x0030,
2557 .sysc_offs = 0x0034,
2558 .syss_offs = 0x0038,
2559 .sysc_flags = SYSS_HAS_RESET_STATUS,
2560 };
2561
2562 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2563 .name = "des",
2564 .sysc = &dra7xx_des_sysc,
2565 };
2566
2567 /* DES */
2568 static struct omap_hwmod dra7xx_des_hwmod = {
2569 .name = "des",
2570 .class = &dra7xx_des_hwmod_class,
2571 .clkdm_name = "l4sec_clkdm",
2572 .main_clk = "l3_iclk_div",
2573 .prcm = {
2574 .omap4 = {
2575 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2576 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2577 .modulemode = MODULEMODE_HWCTRL,
2578 },
2579 },
2580 };
2581
2582 /* rng */
2583 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2584 .rev_offs = 0x1fe0,
2585 .sysc_offs = 0x1fe4,
2586 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2587 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2588 .sysc_fields = &omap_hwmod_sysc_type1,
2589 };
2590
2591 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2592 .name = "rng",
2593 .sysc = &dra7xx_rng_sysc,
2594 };
2595
2596 static struct omap_hwmod dra7xx_rng_hwmod = {
2597 .name = "rng",
2598 .class = &dra7xx_rng_hwmod_class,
2599 .flags = HWMOD_SWSUP_SIDLE,
2600 .clkdm_name = "l4sec_clkdm",
2601 .prcm = {
2602 .omap4 = {
2603 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2604 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2605 .modulemode = MODULEMODE_HWCTRL,
2606 },
2607 },
2608 };
2609
2610 /*
2611 * 'usb_otg_ss' class
2612 *
2613 */
2614
2615 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2616 .rev_offs = 0x0000,
2617 .sysc_offs = 0x0010,
2618 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2619 SYSC_HAS_SIDLEMODE),
2620 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2621 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2622 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2623 .sysc_fields = &omap_hwmod_sysc_type2,
2624 };
2625
2626 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2627 .name = "usb_otg_ss",
2628 .sysc = &dra7xx_usb_otg_ss_sysc,
2629 };
2630
2631 /* usb_otg_ss1 */
2632 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2633 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2634 };
2635
2636 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2637 .name = "usb_otg_ss1",
2638 .class = &dra7xx_usb_otg_ss_hwmod_class,
2639 .clkdm_name = "l3init_clkdm",
2640 .main_clk = "dpll_core_h13x2_ck",
2641 .flags = HWMOD_CLKDM_NOAUTO,
2642 .prcm = {
2643 .omap4 = {
2644 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2645 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2646 .modulemode = MODULEMODE_HWCTRL,
2647 },
2648 },
2649 .opt_clks = usb_otg_ss1_opt_clks,
2650 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2651 };
2652
2653 /* usb_otg_ss2 */
2654 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2655 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2656 };
2657
2658 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2659 .name = "usb_otg_ss2",
2660 .class = &dra7xx_usb_otg_ss_hwmod_class,
2661 .clkdm_name = "l3init_clkdm",
2662 .main_clk = "dpll_core_h13x2_ck",
2663 .flags = HWMOD_CLKDM_NOAUTO,
2664 .prcm = {
2665 .omap4 = {
2666 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2667 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2668 .modulemode = MODULEMODE_HWCTRL,
2669 },
2670 },
2671 .opt_clks = usb_otg_ss2_opt_clks,
2672 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2673 };
2674
2675 /* usb_otg_ss3 */
2676 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2677 .name = "usb_otg_ss3",
2678 .class = &dra7xx_usb_otg_ss_hwmod_class,
2679 .clkdm_name = "l3init_clkdm",
2680 .main_clk = "dpll_core_h13x2_ck",
2681 .prcm = {
2682 .omap4 = {
2683 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2684 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2685 .modulemode = MODULEMODE_HWCTRL,
2686 },
2687 },
2688 };
2689
2690 /* usb_otg_ss4 */
2691 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2692 .name = "usb_otg_ss4",
2693 .class = &dra7xx_usb_otg_ss_hwmod_class,
2694 .clkdm_name = "l3init_clkdm",
2695 .main_clk = "dpll_core_h13x2_ck",
2696 .prcm = {
2697 .omap4 = {
2698 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2699 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2700 .modulemode = MODULEMODE_HWCTRL,
2701 },
2702 },
2703 };
2704
2705 /*
2706 * 'vcp' class
2707 *
2708 */
2709
2710 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2711 .name = "vcp",
2712 };
2713
2714 /* vcp1 */
2715 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2716 .name = "vcp1",
2717 .class = &dra7xx_vcp_hwmod_class,
2718 .clkdm_name = "l3main1_clkdm",
2719 .main_clk = "l3_iclk_div",
2720 .prcm = {
2721 .omap4 = {
2722 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2723 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2724 },
2725 },
2726 };
2727
2728 /* vcp2 */
2729 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2730 .name = "vcp2",
2731 .class = &dra7xx_vcp_hwmod_class,
2732 .clkdm_name = "l3main1_clkdm",
2733 .main_clk = "l3_iclk_div",
2734 .prcm = {
2735 .omap4 = {
2736 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2737 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2738 },
2739 },
2740 };
2741
2742 /*
2743 * 'wd_timer' class
2744 *
2745 */
2746
2747 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2748 .rev_offs = 0x0000,
2749 .sysc_offs = 0x0010,
2750 .syss_offs = 0x0014,
2751 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2752 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2754 SIDLE_SMART_WKUP),
2755 .sysc_fields = &omap_hwmod_sysc_type1,
2756 };
2757
2758 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2759 .name = "wd_timer",
2760 .sysc = &dra7xx_wd_timer_sysc,
2761 .pre_shutdown = &omap2_wd_timer_disable,
2762 .reset = &omap2_wd_timer_reset,
2763 };
2764
2765 /* wd_timer2 */
2766 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2767 .name = "wd_timer2",
2768 .class = &dra7xx_wd_timer_hwmod_class,
2769 .clkdm_name = "wkupaon_clkdm",
2770 .main_clk = "sys_32k_ck",
2771 .prcm = {
2772 .omap4 = {
2773 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2774 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2775 .modulemode = MODULEMODE_SWCTRL,
2776 },
2777 },
2778 };
2779
2780
2781 /*
2782 * Interfaces
2783 */
2784
2785 /* l3_main_1 -> dmm */
2786 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2787 .master = &dra7xx_l3_main_1_hwmod,
2788 .slave = &dra7xx_dmm_hwmod,
2789 .clk = "l3_iclk_div",
2790 .user = OCP_USER_SDMA,
2791 };
2792
2793 /* l3_main_2 -> l3_instr */
2794 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2795 .master = &dra7xx_l3_main_2_hwmod,
2796 .slave = &dra7xx_l3_instr_hwmod,
2797 .clk = "l3_iclk_div",
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799 };
2800
2801 /* l4_cfg -> l3_main_1 */
2802 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2803 .master = &dra7xx_l4_cfg_hwmod,
2804 .slave = &dra7xx_l3_main_1_hwmod,
2805 .clk = "l3_iclk_div",
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807 };
2808
2809 /* mpu -> l3_main_1 */
2810 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2811 .master = &dra7xx_mpu_hwmod,
2812 .slave = &dra7xx_l3_main_1_hwmod,
2813 .clk = "l3_iclk_div",
2814 .user = OCP_USER_MPU,
2815 };
2816
2817 /* l3_main_1 -> l3_main_2 */
2818 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2819 .master = &dra7xx_l3_main_1_hwmod,
2820 .slave = &dra7xx_l3_main_2_hwmod,
2821 .clk = "l3_iclk_div",
2822 .user = OCP_USER_MPU,
2823 };
2824
2825 /* l4_cfg -> l3_main_2 */
2826 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2827 .master = &dra7xx_l4_cfg_hwmod,
2828 .slave = &dra7xx_l3_main_2_hwmod,
2829 .clk = "l3_iclk_div",
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831 };
2832
2833 /* l3_main_1 -> l4_cfg */
2834 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2835 .master = &dra7xx_l3_main_1_hwmod,
2836 .slave = &dra7xx_l4_cfg_hwmod,
2837 .clk = "l3_iclk_div",
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2839 };
2840
2841 /* l3_main_1 -> l4_per1 */
2842 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2843 .master = &dra7xx_l3_main_1_hwmod,
2844 .slave = &dra7xx_l4_per1_hwmod,
2845 .clk = "l3_iclk_div",
2846 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847 };
2848
2849 /* l3_main_1 -> l4_per2 */
2850 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2851 .master = &dra7xx_l3_main_1_hwmod,
2852 .slave = &dra7xx_l4_per2_hwmod,
2853 .clk = "l3_iclk_div",
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855 };
2856
2857 /* l3_main_1 -> l4_per3 */
2858 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2859 .master = &dra7xx_l3_main_1_hwmod,
2860 .slave = &dra7xx_l4_per3_hwmod,
2861 .clk = "l3_iclk_div",
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863 };
2864
2865 /* l3_main_1 -> l4_wkup */
2866 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2867 .master = &dra7xx_l3_main_1_hwmod,
2868 .slave = &dra7xx_l4_wkup_hwmod,
2869 .clk = "wkupaon_iclk_mux",
2870 .user = OCP_USER_MPU | OCP_USER_SDMA,
2871 };
2872
2873 /* l4_per2 -> atl */
2874 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2875 .master = &dra7xx_l4_per2_hwmod,
2876 .slave = &dra7xx_atl_hwmod,
2877 .clk = "l3_iclk_div",
2878 .user = OCP_USER_MPU | OCP_USER_SDMA,
2879 };
2880
2881 /* l3_main_1 -> bb2d */
2882 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2883 .master = &dra7xx_l3_main_1_hwmod,
2884 .slave = &dra7xx_bb2d_hwmod,
2885 .clk = "l3_iclk_div",
2886 .user = OCP_USER_MPU | OCP_USER_SDMA,
2887 };
2888
2889 /* l4_wkup -> counter_32k */
2890 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2891 .master = &dra7xx_l4_wkup_hwmod,
2892 .slave = &dra7xx_counter_32k_hwmod,
2893 .clk = "wkupaon_iclk_mux",
2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
2895 };
2896
2897 /* l4_wkup -> ctrl_module_wkup */
2898 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2899 .master = &dra7xx_l4_wkup_hwmod,
2900 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2901 .clk = "wkupaon_iclk_mux",
2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
2903 };
2904
2905 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2906 .master = &dra7xx_l4_per2_hwmod,
2907 .slave = &dra7xx_gmac_hwmod,
2908 .clk = "dpll_gmac_ck",
2909 .user = OCP_USER_MPU,
2910 };
2911
2912 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2913 .master = &dra7xx_gmac_hwmod,
2914 .slave = &dra7xx_mdio_hwmod,
2915 .user = OCP_USER_MPU,
2916 };
2917
2918 /* l4_wkup -> dcan1 */
2919 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2920 .master = &dra7xx_l4_wkup_hwmod,
2921 .slave = &dra7xx_dcan1_hwmod,
2922 .clk = "wkupaon_iclk_mux",
2923 .user = OCP_USER_MPU | OCP_USER_SDMA,
2924 };
2925
2926 /* l4_per2 -> dcan2 */
2927 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2928 .master = &dra7xx_l4_per2_hwmod,
2929 .slave = &dra7xx_dcan2_hwmod,
2930 .clk = "l3_iclk_div",
2931 .user = OCP_USER_MPU | OCP_USER_SDMA,
2932 };
2933
2934 /* l4_cfg -> dma_system */
2935 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2936 .master = &dra7xx_l4_cfg_hwmod,
2937 .slave = &dra7xx_dma_system_hwmod,
2938 .clk = "l3_iclk_div",
2939 .user = OCP_USER_MPU | OCP_USER_SDMA,
2940 };
2941
2942 /* l3_main_1 -> tpcc */
2943 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2944 .master = &dra7xx_l3_main_1_hwmod,
2945 .slave = &dra7xx_tpcc_hwmod,
2946 .clk = "l3_iclk_div",
2947 .user = OCP_USER_MPU,
2948 };
2949
2950 /* l3_main_1 -> tptc0 */
2951 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2952 .master = &dra7xx_l3_main_1_hwmod,
2953 .slave = &dra7xx_tptc0_hwmod,
2954 .clk = "l3_iclk_div",
2955 .user = OCP_USER_MPU,
2956 };
2957
2958 /* l3_main_1 -> tptc1 */
2959 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2960 .master = &dra7xx_l3_main_1_hwmod,
2961 .slave = &dra7xx_tptc1_hwmod,
2962 .clk = "l3_iclk_div",
2963 .user = OCP_USER_MPU,
2964 };
2965
2966 /* l3_main_1 -> dss */
2967 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2968 .master = &dra7xx_l3_main_1_hwmod,
2969 .slave = &dra7xx_dss_hwmod,
2970 .clk = "l3_iclk_div",
2971 .user = OCP_USER_MPU | OCP_USER_SDMA,
2972 };
2973
2974 /* l3_main_1 -> dispc */
2975 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2976 .master = &dra7xx_l3_main_1_hwmod,
2977 .slave = &dra7xx_dss_dispc_hwmod,
2978 .clk = "l3_iclk_div",
2979 .user = OCP_USER_MPU | OCP_USER_SDMA,
2980 };
2981
2982 /* l3_main_1 -> dispc */
2983 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2984 .master = &dra7xx_l3_main_1_hwmod,
2985 .slave = &dra7xx_dss_hdmi_hwmod,
2986 .clk = "l3_iclk_div",
2987 .user = OCP_USER_MPU | OCP_USER_SDMA,
2988 };
2989
2990 /* l3_main_1 -> aes1 */
2991 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2992 .master = &dra7xx_l3_main_1_hwmod,
2993 .slave = &dra7xx_aes1_hwmod,
2994 .clk = "l3_iclk_div",
2995 .user = OCP_USER_MPU | OCP_USER_SDMA,
2996 };
2997
2998 /* l3_main_1 -> aes2 */
2999 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3000 .master = &dra7xx_l3_main_1_hwmod,
3001 .slave = &dra7xx_aes2_hwmod,
3002 .clk = "l3_iclk_div",
3003 .user = OCP_USER_MPU | OCP_USER_SDMA,
3004 };
3005
3006 /* l3_main_1 -> sha0 */
3007 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3008 .master = &dra7xx_l3_main_1_hwmod,
3009 .slave = &dra7xx_sha0_hwmod,
3010 .clk = "l3_iclk_div",
3011 .user = OCP_USER_MPU | OCP_USER_SDMA,
3012 };
3013
3014 /* l4_per2 -> mcasp1 */
3015 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3016 .master = &dra7xx_l4_per2_hwmod,
3017 .slave = &dra7xx_mcasp1_hwmod,
3018 .clk = "l4_root_clk_div",
3019 .user = OCP_USER_MPU | OCP_USER_SDMA,
3020 };
3021
3022 /* l3_main_1 -> mcasp1 */
3023 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3024 .master = &dra7xx_l3_main_1_hwmod,
3025 .slave = &dra7xx_mcasp1_hwmod,
3026 .clk = "l3_iclk_div",
3027 .user = OCP_USER_MPU | OCP_USER_SDMA,
3028 };
3029
3030 /* l4_per2 -> mcasp2 */
3031 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3032 .master = &dra7xx_l4_per2_hwmod,
3033 .slave = &dra7xx_mcasp2_hwmod,
3034 .clk = "l4_root_clk_div",
3035 .user = OCP_USER_MPU | OCP_USER_SDMA,
3036 };
3037
3038 /* l3_main_1 -> mcasp2 */
3039 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3040 .master = &dra7xx_l3_main_1_hwmod,
3041 .slave = &dra7xx_mcasp2_hwmod,
3042 .clk = "l3_iclk_div",
3043 .user = OCP_USER_MPU | OCP_USER_SDMA,
3044 };
3045
3046 /* l4_per2 -> mcasp3 */
3047 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3048 .master = &dra7xx_l4_per2_hwmod,
3049 .slave = &dra7xx_mcasp3_hwmod,
3050 .clk = "l4_root_clk_div",
3051 .user = OCP_USER_MPU | OCP_USER_SDMA,
3052 };
3053
3054 /* l3_main_1 -> mcasp3 */
3055 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3056 .master = &dra7xx_l3_main_1_hwmod,
3057 .slave = &dra7xx_mcasp3_hwmod,
3058 .clk = "l3_iclk_div",
3059 .user = OCP_USER_MPU | OCP_USER_SDMA,
3060 };
3061
3062 /* l4_per2 -> mcasp4 */
3063 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3064 .master = &dra7xx_l4_per2_hwmod,
3065 .slave = &dra7xx_mcasp4_hwmod,
3066 .clk = "l4_root_clk_div",
3067 .user = OCP_USER_MPU | OCP_USER_SDMA,
3068 };
3069
3070 /* l4_per2 -> mcasp5 */
3071 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3072 .master = &dra7xx_l4_per2_hwmod,
3073 .slave = &dra7xx_mcasp5_hwmod,
3074 .clk = "l4_root_clk_div",
3075 .user = OCP_USER_MPU | OCP_USER_SDMA,
3076 };
3077
3078 /* l4_per2 -> mcasp6 */
3079 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3080 .master = &dra7xx_l4_per2_hwmod,
3081 .slave = &dra7xx_mcasp6_hwmod,
3082 .clk = "l4_root_clk_div",
3083 .user = OCP_USER_MPU | OCP_USER_SDMA,
3084 };
3085
3086 /* l4_per2 -> mcasp7 */
3087 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3088 .master = &dra7xx_l4_per2_hwmod,
3089 .slave = &dra7xx_mcasp7_hwmod,
3090 .clk = "l4_root_clk_div",
3091 .user = OCP_USER_MPU | OCP_USER_SDMA,
3092 };
3093
3094 /* l4_per2 -> mcasp8 */
3095 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3096 .master = &dra7xx_l4_per2_hwmod,
3097 .slave = &dra7xx_mcasp8_hwmod,
3098 .clk = "l4_root_clk_div",
3099 .user = OCP_USER_MPU | OCP_USER_SDMA,
3100 };
3101
3102 /* l4_per1 -> elm */
3103 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3104 .master = &dra7xx_l4_per1_hwmod,
3105 .slave = &dra7xx_elm_hwmod,
3106 .clk = "l3_iclk_div",
3107 .user = OCP_USER_MPU | OCP_USER_SDMA,
3108 };
3109
3110 /* l4_wkup -> gpio1 */
3111 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3112 .master = &dra7xx_l4_wkup_hwmod,
3113 .slave = &dra7xx_gpio1_hwmod,
3114 .clk = "wkupaon_iclk_mux",
3115 .user = OCP_USER_MPU | OCP_USER_SDMA,
3116 };
3117
3118 /* l4_per1 -> gpio2 */
3119 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3120 .master = &dra7xx_l4_per1_hwmod,
3121 .slave = &dra7xx_gpio2_hwmod,
3122 .clk = "l3_iclk_div",
3123 .user = OCP_USER_MPU | OCP_USER_SDMA,
3124 };
3125
3126 /* l4_per1 -> gpio3 */
3127 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3128 .master = &dra7xx_l4_per1_hwmod,
3129 .slave = &dra7xx_gpio3_hwmod,
3130 .clk = "l3_iclk_div",
3131 .user = OCP_USER_MPU | OCP_USER_SDMA,
3132 };
3133
3134 /* l4_per1 -> gpio4 */
3135 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3136 .master = &dra7xx_l4_per1_hwmod,
3137 .slave = &dra7xx_gpio4_hwmod,
3138 .clk = "l3_iclk_div",
3139 .user = OCP_USER_MPU | OCP_USER_SDMA,
3140 };
3141
3142 /* l4_per1 -> gpio5 */
3143 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3144 .master = &dra7xx_l4_per1_hwmod,
3145 .slave = &dra7xx_gpio5_hwmod,
3146 .clk = "l3_iclk_div",
3147 .user = OCP_USER_MPU | OCP_USER_SDMA,
3148 };
3149
3150 /* l4_per1 -> gpio6 */
3151 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3152 .master = &dra7xx_l4_per1_hwmod,
3153 .slave = &dra7xx_gpio6_hwmod,
3154 .clk = "l3_iclk_div",
3155 .user = OCP_USER_MPU | OCP_USER_SDMA,
3156 };
3157
3158 /* l4_per1 -> gpio7 */
3159 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3160 .master = &dra7xx_l4_per1_hwmod,
3161 .slave = &dra7xx_gpio7_hwmod,
3162 .clk = "l3_iclk_div",
3163 .user = OCP_USER_MPU | OCP_USER_SDMA,
3164 };
3165
3166 /* l4_per1 -> gpio8 */
3167 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3168 .master = &dra7xx_l4_per1_hwmod,
3169 .slave = &dra7xx_gpio8_hwmod,
3170 .clk = "l3_iclk_div",
3171 .user = OCP_USER_MPU | OCP_USER_SDMA,
3172 };
3173
3174 /* l3_main_1 -> gpmc */
3175 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3176 .master = &dra7xx_l3_main_1_hwmod,
3177 .slave = &dra7xx_gpmc_hwmod,
3178 .clk = "l3_iclk_div",
3179 .user = OCP_USER_MPU | OCP_USER_SDMA,
3180 };
3181
3182 /* l4_per1 -> hdq1w */
3183 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3184 .master = &dra7xx_l4_per1_hwmod,
3185 .slave = &dra7xx_hdq1w_hwmod,
3186 .clk = "l3_iclk_div",
3187 .user = OCP_USER_MPU | OCP_USER_SDMA,
3188 };
3189
3190 /* l4_per1 -> i2c1 */
3191 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3192 .master = &dra7xx_l4_per1_hwmod,
3193 .slave = &dra7xx_i2c1_hwmod,
3194 .clk = "l3_iclk_div",
3195 .user = OCP_USER_MPU | OCP_USER_SDMA,
3196 };
3197
3198 /* l4_per1 -> i2c2 */
3199 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3200 .master = &dra7xx_l4_per1_hwmod,
3201 .slave = &dra7xx_i2c2_hwmod,
3202 .clk = "l3_iclk_div",
3203 .user = OCP_USER_MPU | OCP_USER_SDMA,
3204 };
3205
3206 /* l4_per1 -> i2c3 */
3207 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3208 .master = &dra7xx_l4_per1_hwmod,
3209 .slave = &dra7xx_i2c3_hwmod,
3210 .clk = "l3_iclk_div",
3211 .user = OCP_USER_MPU | OCP_USER_SDMA,
3212 };
3213
3214 /* l4_per1 -> i2c4 */
3215 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3216 .master = &dra7xx_l4_per1_hwmod,
3217 .slave = &dra7xx_i2c4_hwmod,
3218 .clk = "l3_iclk_div",
3219 .user = OCP_USER_MPU | OCP_USER_SDMA,
3220 };
3221
3222 /* l4_per1 -> i2c5 */
3223 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3224 .master = &dra7xx_l4_per1_hwmod,
3225 .slave = &dra7xx_i2c5_hwmod,
3226 .clk = "l3_iclk_div",
3227 .user = OCP_USER_MPU | OCP_USER_SDMA,
3228 };
3229
3230 /* l4_cfg -> mailbox1 */
3231 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3232 .master = &dra7xx_l4_cfg_hwmod,
3233 .slave = &dra7xx_mailbox1_hwmod,
3234 .clk = "l3_iclk_div",
3235 .user = OCP_USER_MPU | OCP_USER_SDMA,
3236 };
3237
3238 /* l4_per3 -> mailbox2 */
3239 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3240 .master = &dra7xx_l4_per3_hwmod,
3241 .slave = &dra7xx_mailbox2_hwmod,
3242 .clk = "l3_iclk_div",
3243 .user = OCP_USER_MPU | OCP_USER_SDMA,
3244 };
3245
3246 /* l4_per3 -> mailbox3 */
3247 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3248 .master = &dra7xx_l4_per3_hwmod,
3249 .slave = &dra7xx_mailbox3_hwmod,
3250 .clk = "l3_iclk_div",
3251 .user = OCP_USER_MPU | OCP_USER_SDMA,
3252 };
3253
3254 /* l4_per3 -> mailbox4 */
3255 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3256 .master = &dra7xx_l4_per3_hwmod,
3257 .slave = &dra7xx_mailbox4_hwmod,
3258 .clk = "l3_iclk_div",
3259 .user = OCP_USER_MPU | OCP_USER_SDMA,
3260 };
3261
3262 /* l4_per3 -> mailbox5 */
3263 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3264 .master = &dra7xx_l4_per3_hwmod,
3265 .slave = &dra7xx_mailbox5_hwmod,
3266 .clk = "l3_iclk_div",
3267 .user = OCP_USER_MPU | OCP_USER_SDMA,
3268 };
3269
3270 /* l4_per3 -> mailbox6 */
3271 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3272 .master = &dra7xx_l4_per3_hwmod,
3273 .slave = &dra7xx_mailbox6_hwmod,
3274 .clk = "l3_iclk_div",
3275 .user = OCP_USER_MPU | OCP_USER_SDMA,
3276 };
3277
3278 /* l4_per3 -> mailbox7 */
3279 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3280 .master = &dra7xx_l4_per3_hwmod,
3281 .slave = &dra7xx_mailbox7_hwmod,
3282 .clk = "l3_iclk_div",
3283 .user = OCP_USER_MPU | OCP_USER_SDMA,
3284 };
3285
3286 /* l4_per3 -> mailbox8 */
3287 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3288 .master = &dra7xx_l4_per3_hwmod,
3289 .slave = &dra7xx_mailbox8_hwmod,
3290 .clk = "l3_iclk_div",
3291 .user = OCP_USER_MPU | OCP_USER_SDMA,
3292 };
3293
3294 /* l4_per3 -> mailbox9 */
3295 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3296 .master = &dra7xx_l4_per3_hwmod,
3297 .slave = &dra7xx_mailbox9_hwmod,
3298 .clk = "l3_iclk_div",
3299 .user = OCP_USER_MPU | OCP_USER_SDMA,
3300 };
3301
3302 /* l4_per3 -> mailbox10 */
3303 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3304 .master = &dra7xx_l4_per3_hwmod,
3305 .slave = &dra7xx_mailbox10_hwmod,
3306 .clk = "l3_iclk_div",
3307 .user = OCP_USER_MPU | OCP_USER_SDMA,
3308 };
3309
3310 /* l4_per3 -> mailbox11 */
3311 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3312 .master = &dra7xx_l4_per3_hwmod,
3313 .slave = &dra7xx_mailbox11_hwmod,
3314 .clk = "l3_iclk_div",
3315 .user = OCP_USER_MPU | OCP_USER_SDMA,
3316 };
3317
3318 /* l4_per3 -> mailbox12 */
3319 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3320 .master = &dra7xx_l4_per3_hwmod,
3321 .slave = &dra7xx_mailbox12_hwmod,
3322 .clk = "l3_iclk_div",
3323 .user = OCP_USER_MPU | OCP_USER_SDMA,
3324 };
3325
3326 /* l4_per3 -> mailbox13 */
3327 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3328 .master = &dra7xx_l4_per3_hwmod,
3329 .slave = &dra7xx_mailbox13_hwmod,
3330 .clk = "l3_iclk_div",
3331 .user = OCP_USER_MPU | OCP_USER_SDMA,
3332 };
3333
3334 /* l4_per1 -> mcspi1 */
3335 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3336 .master = &dra7xx_l4_per1_hwmod,
3337 .slave = &dra7xx_mcspi1_hwmod,
3338 .clk = "l3_iclk_div",
3339 .user = OCP_USER_MPU | OCP_USER_SDMA,
3340 };
3341
3342 /* l4_per1 -> mcspi2 */
3343 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3344 .master = &dra7xx_l4_per1_hwmod,
3345 .slave = &dra7xx_mcspi2_hwmod,
3346 .clk = "l3_iclk_div",
3347 .user = OCP_USER_MPU | OCP_USER_SDMA,
3348 };
3349
3350 /* l4_per1 -> mcspi3 */
3351 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3352 .master = &dra7xx_l4_per1_hwmod,
3353 .slave = &dra7xx_mcspi3_hwmod,
3354 .clk = "l3_iclk_div",
3355 .user = OCP_USER_MPU | OCP_USER_SDMA,
3356 };
3357
3358 /* l4_per1 -> mcspi4 */
3359 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3360 .master = &dra7xx_l4_per1_hwmod,
3361 .slave = &dra7xx_mcspi4_hwmod,
3362 .clk = "l3_iclk_div",
3363 .user = OCP_USER_MPU | OCP_USER_SDMA,
3364 };
3365
3366 /* l4_per1 -> mmc1 */
3367 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3368 .master = &dra7xx_l4_per1_hwmod,
3369 .slave = &dra7xx_mmc1_hwmod,
3370 .clk = "l3_iclk_div",
3371 .user = OCP_USER_MPU | OCP_USER_SDMA,
3372 };
3373
3374 /* l4_per1 -> mmc2 */
3375 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3376 .master = &dra7xx_l4_per1_hwmod,
3377 .slave = &dra7xx_mmc2_hwmod,
3378 .clk = "l3_iclk_div",
3379 .user = OCP_USER_MPU | OCP_USER_SDMA,
3380 };
3381
3382 /* l4_per1 -> mmc3 */
3383 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3384 .master = &dra7xx_l4_per1_hwmod,
3385 .slave = &dra7xx_mmc3_hwmod,
3386 .clk = "l3_iclk_div",
3387 .user = OCP_USER_MPU | OCP_USER_SDMA,
3388 };
3389
3390 /* l4_per1 -> mmc4 */
3391 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3392 .master = &dra7xx_l4_per1_hwmod,
3393 .slave = &dra7xx_mmc4_hwmod,
3394 .clk = "l3_iclk_div",
3395 .user = OCP_USER_MPU | OCP_USER_SDMA,
3396 };
3397
3398 /* l4_cfg -> mpu */
3399 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3400 .master = &dra7xx_l4_cfg_hwmod,
3401 .slave = &dra7xx_mpu_hwmod,
3402 .clk = "l3_iclk_div",
3403 .user = OCP_USER_MPU | OCP_USER_SDMA,
3404 };
3405
3406 /* l4_cfg -> ocp2scp1 */
3407 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3408 .master = &dra7xx_l4_cfg_hwmod,
3409 .slave = &dra7xx_ocp2scp1_hwmod,
3410 .clk = "l4_root_clk_div",
3411 .user = OCP_USER_MPU | OCP_USER_SDMA,
3412 };
3413
3414 /* l4_cfg -> ocp2scp3 */
3415 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3416 .master = &dra7xx_l4_cfg_hwmod,
3417 .slave = &dra7xx_ocp2scp3_hwmod,
3418 .clk = "l4_root_clk_div",
3419 .user = OCP_USER_MPU | OCP_USER_SDMA,
3420 };
3421
3422 /* l3_main_1 -> pciess1 */
3423 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3424 .master = &dra7xx_l3_main_1_hwmod,
3425 .slave = &dra7xx_pciess1_hwmod,
3426 .clk = "l3_iclk_div",
3427 .user = OCP_USER_MPU | OCP_USER_SDMA,
3428 };
3429
3430 /* l4_cfg -> pciess1 */
3431 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3432 .master = &dra7xx_l4_cfg_hwmod,
3433 .slave = &dra7xx_pciess1_hwmod,
3434 .clk = "l4_root_clk_div",
3435 .user = OCP_USER_MPU | OCP_USER_SDMA,
3436 };
3437
3438 /* l3_main_1 -> pciess2 */
3439 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3440 .master = &dra7xx_l3_main_1_hwmod,
3441 .slave = &dra7xx_pciess2_hwmod,
3442 .clk = "l3_iclk_div",
3443 .user = OCP_USER_MPU | OCP_USER_SDMA,
3444 };
3445
3446 /* l4_cfg -> pciess2 */
3447 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3448 .master = &dra7xx_l4_cfg_hwmod,
3449 .slave = &dra7xx_pciess2_hwmod,
3450 .clk = "l4_root_clk_div",
3451 .user = OCP_USER_MPU | OCP_USER_SDMA,
3452 };
3453
3454 /* l3_main_1 -> qspi */
3455 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3456 .master = &dra7xx_l3_main_1_hwmod,
3457 .slave = &dra7xx_qspi_hwmod,
3458 .clk = "l3_iclk_div",
3459 .user = OCP_USER_MPU | OCP_USER_SDMA,
3460 };
3461
3462 /* l4_per3 -> rtcss */
3463 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3464 .master = &dra7xx_l4_per3_hwmod,
3465 .slave = &dra7xx_rtcss_hwmod,
3466 .clk = "l4_root_clk_div",
3467 .user = OCP_USER_MPU | OCP_USER_SDMA,
3468 };
3469
3470 /* l4_cfg -> sata */
3471 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3472 .master = &dra7xx_l4_cfg_hwmod,
3473 .slave = &dra7xx_sata_hwmod,
3474 .clk = "l3_iclk_div",
3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3476 };
3477
3478 /* l4_cfg -> smartreflex_core */
3479 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3480 .master = &dra7xx_l4_cfg_hwmod,
3481 .slave = &dra7xx_smartreflex_core_hwmod,
3482 .clk = "l4_root_clk_div",
3483 .user = OCP_USER_MPU | OCP_USER_SDMA,
3484 };
3485
3486 /* l4_cfg -> smartreflex_mpu */
3487 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3488 .master = &dra7xx_l4_cfg_hwmod,
3489 .slave = &dra7xx_smartreflex_mpu_hwmod,
3490 .clk = "l4_root_clk_div",
3491 .user = OCP_USER_MPU | OCP_USER_SDMA,
3492 };
3493
3494 /* l4_cfg -> spinlock */
3495 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3496 .master = &dra7xx_l4_cfg_hwmod,
3497 .slave = &dra7xx_spinlock_hwmod,
3498 .clk = "l3_iclk_div",
3499 .user = OCP_USER_MPU | OCP_USER_SDMA,
3500 };
3501
3502 /* l4_wkup -> timer1 */
3503 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3504 .master = &dra7xx_l4_wkup_hwmod,
3505 .slave = &dra7xx_timer1_hwmod,
3506 .clk = "wkupaon_iclk_mux",
3507 .user = OCP_USER_MPU | OCP_USER_SDMA,
3508 };
3509
3510 /* l4_per1 -> timer2 */
3511 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3512 .master = &dra7xx_l4_per1_hwmod,
3513 .slave = &dra7xx_timer2_hwmod,
3514 .clk = "l3_iclk_div",
3515 .user = OCP_USER_MPU | OCP_USER_SDMA,
3516 };
3517
3518 /* l4_per1 -> timer3 */
3519 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3520 .master = &dra7xx_l4_per1_hwmod,
3521 .slave = &dra7xx_timer3_hwmod,
3522 .clk = "l3_iclk_div",
3523 .user = OCP_USER_MPU | OCP_USER_SDMA,
3524 };
3525
3526 /* l4_per1 -> timer4 */
3527 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3528 .master = &dra7xx_l4_per1_hwmod,
3529 .slave = &dra7xx_timer4_hwmod,
3530 .clk = "l3_iclk_div",
3531 .user = OCP_USER_MPU | OCP_USER_SDMA,
3532 };
3533
3534 /* l4_per3 -> timer5 */
3535 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3536 .master = &dra7xx_l4_per3_hwmod,
3537 .slave = &dra7xx_timer5_hwmod,
3538 .clk = "l3_iclk_div",
3539 .user = OCP_USER_MPU | OCP_USER_SDMA,
3540 };
3541
3542 /* l4_per3 -> timer6 */
3543 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3544 .master = &dra7xx_l4_per3_hwmod,
3545 .slave = &dra7xx_timer6_hwmod,
3546 .clk = "l3_iclk_div",
3547 .user = OCP_USER_MPU | OCP_USER_SDMA,
3548 };
3549
3550 /* l4_per3 -> timer7 */
3551 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3552 .master = &dra7xx_l4_per3_hwmod,
3553 .slave = &dra7xx_timer7_hwmod,
3554 .clk = "l3_iclk_div",
3555 .user = OCP_USER_MPU | OCP_USER_SDMA,
3556 };
3557
3558 /* l4_per3 -> timer8 */
3559 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3560 .master = &dra7xx_l4_per3_hwmod,
3561 .slave = &dra7xx_timer8_hwmod,
3562 .clk = "l3_iclk_div",
3563 .user = OCP_USER_MPU | OCP_USER_SDMA,
3564 };
3565
3566 /* l4_per1 -> timer9 */
3567 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3568 .master = &dra7xx_l4_per1_hwmod,
3569 .slave = &dra7xx_timer9_hwmod,
3570 .clk = "l3_iclk_div",
3571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3572 };
3573
3574 /* l4_per1 -> timer10 */
3575 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3576 .master = &dra7xx_l4_per1_hwmod,
3577 .slave = &dra7xx_timer10_hwmod,
3578 .clk = "l3_iclk_div",
3579 .user = OCP_USER_MPU | OCP_USER_SDMA,
3580 };
3581
3582 /* l4_per1 -> timer11 */
3583 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3584 .master = &dra7xx_l4_per1_hwmod,
3585 .slave = &dra7xx_timer11_hwmod,
3586 .clk = "l3_iclk_div",
3587 .user = OCP_USER_MPU | OCP_USER_SDMA,
3588 };
3589
3590 /* l4_wkup -> timer12 */
3591 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3592 .master = &dra7xx_l4_wkup_hwmod,
3593 .slave = &dra7xx_timer12_hwmod,
3594 .clk = "wkupaon_iclk_mux",
3595 .user = OCP_USER_MPU | OCP_USER_SDMA,
3596 };
3597
3598 /* l4_per3 -> timer13 */
3599 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3600 .master = &dra7xx_l4_per3_hwmod,
3601 .slave = &dra7xx_timer13_hwmod,
3602 .clk = "l3_iclk_div",
3603 .user = OCP_USER_MPU | OCP_USER_SDMA,
3604 };
3605
3606 /* l4_per3 -> timer14 */
3607 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3608 .master = &dra7xx_l4_per3_hwmod,
3609 .slave = &dra7xx_timer14_hwmod,
3610 .clk = "l3_iclk_div",
3611 .user = OCP_USER_MPU | OCP_USER_SDMA,
3612 };
3613
3614 /* l4_per3 -> timer15 */
3615 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3616 .master = &dra7xx_l4_per3_hwmod,
3617 .slave = &dra7xx_timer15_hwmod,
3618 .clk = "l3_iclk_div",
3619 .user = OCP_USER_MPU | OCP_USER_SDMA,
3620 };
3621
3622 /* l4_per3 -> timer16 */
3623 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3624 .master = &dra7xx_l4_per3_hwmod,
3625 .slave = &dra7xx_timer16_hwmod,
3626 .clk = "l3_iclk_div",
3627 .user = OCP_USER_MPU | OCP_USER_SDMA,
3628 };
3629
3630 /* l4_per1 -> uart1 */
3631 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3632 .master = &dra7xx_l4_per1_hwmod,
3633 .slave = &dra7xx_uart1_hwmod,
3634 .clk = "l3_iclk_div",
3635 .user = OCP_USER_MPU | OCP_USER_SDMA,
3636 };
3637
3638 /* l4_per1 -> uart2 */
3639 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3640 .master = &dra7xx_l4_per1_hwmod,
3641 .slave = &dra7xx_uart2_hwmod,
3642 .clk = "l3_iclk_div",
3643 .user = OCP_USER_MPU | OCP_USER_SDMA,
3644 };
3645
3646 /* l4_per1 -> uart3 */
3647 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3648 .master = &dra7xx_l4_per1_hwmod,
3649 .slave = &dra7xx_uart3_hwmod,
3650 .clk = "l3_iclk_div",
3651 .user = OCP_USER_MPU | OCP_USER_SDMA,
3652 };
3653
3654 /* l4_per1 -> uart4 */
3655 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3656 .master = &dra7xx_l4_per1_hwmod,
3657 .slave = &dra7xx_uart4_hwmod,
3658 .clk = "l3_iclk_div",
3659 .user = OCP_USER_MPU | OCP_USER_SDMA,
3660 };
3661
3662 /* l4_per1 -> uart5 */
3663 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3664 .master = &dra7xx_l4_per1_hwmod,
3665 .slave = &dra7xx_uart5_hwmod,
3666 .clk = "l3_iclk_div",
3667 .user = OCP_USER_MPU | OCP_USER_SDMA,
3668 };
3669
3670 /* l4_per1 -> uart6 */
3671 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3672 .master = &dra7xx_l4_per1_hwmod,
3673 .slave = &dra7xx_uart6_hwmod,
3674 .clk = "l3_iclk_div",
3675 .user = OCP_USER_MPU | OCP_USER_SDMA,
3676 };
3677
3678 /* l4_per2 -> uart7 */
3679 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3680 .master = &dra7xx_l4_per2_hwmod,
3681 .slave = &dra7xx_uart7_hwmod,
3682 .clk = "l3_iclk_div",
3683 .user = OCP_USER_MPU | OCP_USER_SDMA,
3684 };
3685
3686 /* l4_per1 -> des */
3687 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3688 .master = &dra7xx_l4_per1_hwmod,
3689 .slave = &dra7xx_des_hwmod,
3690 .clk = "l3_iclk_div",
3691 .user = OCP_USER_MPU | OCP_USER_SDMA,
3692 };
3693
3694 /* l4_per2 -> uart8 */
3695 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3696 .master = &dra7xx_l4_per2_hwmod,
3697 .slave = &dra7xx_uart8_hwmod,
3698 .clk = "l3_iclk_div",
3699 .user = OCP_USER_MPU | OCP_USER_SDMA,
3700 };
3701
3702 /* l4_per2 -> uart9 */
3703 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3704 .master = &dra7xx_l4_per2_hwmod,
3705 .slave = &dra7xx_uart9_hwmod,
3706 .clk = "l3_iclk_div",
3707 .user = OCP_USER_MPU | OCP_USER_SDMA,
3708 };
3709
3710 /* l4_wkup -> uart10 */
3711 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3712 .master = &dra7xx_l4_wkup_hwmod,
3713 .slave = &dra7xx_uart10_hwmod,
3714 .clk = "wkupaon_iclk_mux",
3715 .user = OCP_USER_MPU | OCP_USER_SDMA,
3716 };
3717
3718 /* l4_per1 -> rng */
3719 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3720 .master = &dra7xx_l4_per1_hwmod,
3721 .slave = &dra7xx_rng_hwmod,
3722 .user = OCP_USER_MPU,
3723 };
3724
3725 /* l4_per3 -> usb_otg_ss1 */
3726 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3727 .master = &dra7xx_l4_per3_hwmod,
3728 .slave = &dra7xx_usb_otg_ss1_hwmod,
3729 .clk = "dpll_core_h13x2_ck",
3730 .user = OCP_USER_MPU | OCP_USER_SDMA,
3731 };
3732
3733 /* l4_per3 -> usb_otg_ss2 */
3734 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3735 .master = &dra7xx_l4_per3_hwmod,
3736 .slave = &dra7xx_usb_otg_ss2_hwmod,
3737 .clk = "dpll_core_h13x2_ck",
3738 .user = OCP_USER_MPU | OCP_USER_SDMA,
3739 };
3740
3741 /* l4_per3 -> usb_otg_ss3 */
3742 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3743 .master = &dra7xx_l4_per3_hwmod,
3744 .slave = &dra7xx_usb_otg_ss3_hwmod,
3745 .clk = "dpll_core_h13x2_ck",
3746 .user = OCP_USER_MPU | OCP_USER_SDMA,
3747 };
3748
3749 /* l4_per3 -> usb_otg_ss4 */
3750 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3751 .master = &dra7xx_l4_per3_hwmod,
3752 .slave = &dra7xx_usb_otg_ss4_hwmod,
3753 .clk = "dpll_core_h13x2_ck",
3754 .user = OCP_USER_MPU | OCP_USER_SDMA,
3755 };
3756
3757 /* l3_main_1 -> vcp1 */
3758 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3759 .master = &dra7xx_l3_main_1_hwmod,
3760 .slave = &dra7xx_vcp1_hwmod,
3761 .clk = "l3_iclk_div",
3762 .user = OCP_USER_MPU | OCP_USER_SDMA,
3763 };
3764
3765 /* l4_per2 -> vcp1 */
3766 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3767 .master = &dra7xx_l4_per2_hwmod,
3768 .slave = &dra7xx_vcp1_hwmod,
3769 .clk = "l3_iclk_div",
3770 .user = OCP_USER_MPU | OCP_USER_SDMA,
3771 };
3772
3773 /* l3_main_1 -> vcp2 */
3774 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3775 .master = &dra7xx_l3_main_1_hwmod,
3776 .slave = &dra7xx_vcp2_hwmod,
3777 .clk = "l3_iclk_div",
3778 .user = OCP_USER_MPU | OCP_USER_SDMA,
3779 };
3780
3781 /* l4_per2 -> vcp2 */
3782 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3783 .master = &dra7xx_l4_per2_hwmod,
3784 .slave = &dra7xx_vcp2_hwmod,
3785 .clk = "l3_iclk_div",
3786 .user = OCP_USER_MPU | OCP_USER_SDMA,
3787 };
3788
3789 /* l4_wkup -> wd_timer2 */
3790 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3791 .master = &dra7xx_l4_wkup_hwmod,
3792 .slave = &dra7xx_wd_timer2_hwmod,
3793 .clk = "wkupaon_iclk_mux",
3794 .user = OCP_USER_MPU | OCP_USER_SDMA,
3795 };
3796
3797 /* l4_per2 -> epwmss0 */
3798 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3799 .master = &dra7xx_l4_per2_hwmod,
3800 .slave = &dra7xx_epwmss0_hwmod,
3801 .clk = "l4_root_clk_div",
3802 .user = OCP_USER_MPU,
3803 };
3804
3805 /* l4_per2 -> epwmss1 */
3806 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3807 .master = &dra7xx_l4_per2_hwmod,
3808 .slave = &dra7xx_epwmss1_hwmod,
3809 .clk = "l4_root_clk_div",
3810 .user = OCP_USER_MPU,
3811 };
3812
3813 /* l4_per2 -> epwmss2 */
3814 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3815 .master = &dra7xx_l4_per2_hwmod,
3816 .slave = &dra7xx_epwmss2_hwmod,
3817 .clk = "l4_root_clk_div",
3818 .user = OCP_USER_MPU,
3819 };
3820
3821 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3822 &dra7xx_l3_main_1__dmm,
3823 &dra7xx_l3_main_2__l3_instr,
3824 &dra7xx_l4_cfg__l3_main_1,
3825 &dra7xx_mpu__l3_main_1,
3826 &dra7xx_l3_main_1__l3_main_2,
3827 &dra7xx_l4_cfg__l3_main_2,
3828 &dra7xx_l3_main_1__l4_cfg,
3829 &dra7xx_l3_main_1__l4_per1,
3830 &dra7xx_l3_main_1__l4_per2,
3831 &dra7xx_l3_main_1__l4_per3,
3832 &dra7xx_l3_main_1__l4_wkup,
3833 &dra7xx_l4_per2__atl,
3834 &dra7xx_l3_main_1__bb2d,
3835 &dra7xx_l4_wkup__counter_32k,
3836 &dra7xx_l4_wkup__ctrl_module_wkup,
3837 &dra7xx_l4_wkup__dcan1,
3838 &dra7xx_l4_per2__dcan2,
3839 &dra7xx_l4_per2__cpgmac0,
3840 &dra7xx_l4_per2__mcasp1,
3841 &dra7xx_l3_main_1__mcasp1,
3842 &dra7xx_l4_per2__mcasp2,
3843 &dra7xx_l3_main_1__mcasp2,
3844 &dra7xx_l4_per2__mcasp3,
3845 &dra7xx_l3_main_1__mcasp3,
3846 &dra7xx_l4_per2__mcasp4,
3847 &dra7xx_l4_per2__mcasp5,
3848 &dra7xx_l4_per2__mcasp6,
3849 &dra7xx_l4_per2__mcasp7,
3850 &dra7xx_l4_per2__mcasp8,
3851 &dra7xx_gmac__mdio,
3852 &dra7xx_l4_cfg__dma_system,
3853 &dra7xx_l3_main_1__tpcc,
3854 &dra7xx_l3_main_1__tptc0,
3855 &dra7xx_l3_main_1__tptc1,
3856 &dra7xx_l3_main_1__dss,
3857 &dra7xx_l3_main_1__dispc,
3858 &dra7xx_l3_main_1__hdmi,
3859 &dra7xx_l3_main_1__aes1,
3860 &dra7xx_l3_main_1__aes2,
3861 &dra7xx_l3_main_1__sha0,
3862 &dra7xx_l4_per1__elm,
3863 &dra7xx_l4_wkup__gpio1,
3864 &dra7xx_l4_per1__gpio2,
3865 &dra7xx_l4_per1__gpio3,
3866 &dra7xx_l4_per1__gpio4,
3867 &dra7xx_l4_per1__gpio5,
3868 &dra7xx_l4_per1__gpio6,
3869 &dra7xx_l4_per1__gpio7,
3870 &dra7xx_l4_per1__gpio8,
3871 &dra7xx_l3_main_1__gpmc,
3872 &dra7xx_l4_per1__hdq1w,
3873 &dra7xx_l4_per1__i2c1,
3874 &dra7xx_l4_per1__i2c2,
3875 &dra7xx_l4_per1__i2c3,
3876 &dra7xx_l4_per1__i2c4,
3877 &dra7xx_l4_per1__i2c5,
3878 &dra7xx_l4_cfg__mailbox1,
3879 &dra7xx_l4_per3__mailbox2,
3880 &dra7xx_l4_per3__mailbox3,
3881 &dra7xx_l4_per3__mailbox4,
3882 &dra7xx_l4_per3__mailbox5,
3883 &dra7xx_l4_per3__mailbox6,
3884 &dra7xx_l4_per3__mailbox7,
3885 &dra7xx_l4_per3__mailbox8,
3886 &dra7xx_l4_per3__mailbox9,
3887 &dra7xx_l4_per3__mailbox10,
3888 &dra7xx_l4_per3__mailbox11,
3889 &dra7xx_l4_per3__mailbox12,
3890 &dra7xx_l4_per3__mailbox13,
3891 &dra7xx_l4_per1__mcspi1,
3892 &dra7xx_l4_per1__mcspi2,
3893 &dra7xx_l4_per1__mcspi3,
3894 &dra7xx_l4_per1__mcspi4,
3895 &dra7xx_l4_per1__mmc1,
3896 &dra7xx_l4_per1__mmc2,
3897 &dra7xx_l4_per1__mmc3,
3898 &dra7xx_l4_per1__mmc4,
3899 &dra7xx_l4_cfg__mpu,
3900 &dra7xx_l4_cfg__ocp2scp1,
3901 &dra7xx_l4_cfg__ocp2scp3,
3902 &dra7xx_l3_main_1__pciess1,
3903 &dra7xx_l4_cfg__pciess1,
3904 &dra7xx_l3_main_1__pciess2,
3905 &dra7xx_l4_cfg__pciess2,
3906 &dra7xx_l3_main_1__qspi,
3907 &dra7xx_l4_cfg__sata,
3908 &dra7xx_l4_cfg__smartreflex_core,
3909 &dra7xx_l4_cfg__smartreflex_mpu,
3910 &dra7xx_l4_cfg__spinlock,
3911 &dra7xx_l4_wkup__timer1,
3912 &dra7xx_l4_per1__timer2,
3913 &dra7xx_l4_per1__timer3,
3914 &dra7xx_l4_per1__timer4,
3915 &dra7xx_l4_per3__timer5,
3916 &dra7xx_l4_per3__timer6,
3917 &dra7xx_l4_per3__timer7,
3918 &dra7xx_l4_per3__timer8,
3919 &dra7xx_l4_per1__timer9,
3920 &dra7xx_l4_per1__timer10,
3921 &dra7xx_l4_per1__timer11,
3922 &dra7xx_l4_per3__timer13,
3923 &dra7xx_l4_per3__timer14,
3924 &dra7xx_l4_per3__timer15,
3925 &dra7xx_l4_per3__timer16,
3926 &dra7xx_l4_per1__uart1,
3927 &dra7xx_l4_per1__uart2,
3928 &dra7xx_l4_per1__uart3,
3929 &dra7xx_l4_per1__uart4,
3930 &dra7xx_l4_per1__uart5,
3931 &dra7xx_l4_per1__uart6,
3932 &dra7xx_l4_per2__uart7,
3933 &dra7xx_l4_per2__uart8,
3934 &dra7xx_l4_per2__uart9,
3935 &dra7xx_l4_wkup__uart10,
3936 &dra7xx_l4_per1__des,
3937 &dra7xx_l4_per3__usb_otg_ss1,
3938 &dra7xx_l4_per3__usb_otg_ss2,
3939 &dra7xx_l4_per3__usb_otg_ss3,
3940 &dra7xx_l3_main_1__vcp1,
3941 &dra7xx_l4_per2__vcp1,
3942 &dra7xx_l3_main_1__vcp2,
3943 &dra7xx_l4_per2__vcp2,
3944 &dra7xx_l4_wkup__wd_timer2,
3945 &dra7xx_l4_per2__epwmss0,
3946 &dra7xx_l4_per2__epwmss1,
3947 &dra7xx_l4_per2__epwmss2,
3948 NULL,
3949 };
3950
3951 /* GP-only hwmod links */
3952 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3953 &dra7xx_l4_wkup__timer12,
3954 &dra7xx_l4_per1__rng,
3955 NULL,
3956 };
3957
3958 /* SoC variant specific hwmod links */
3959 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
3960 &dra7xx_l4_per3__usb_otg_ss4,
3961 NULL,
3962 };
3963
3964 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
3965 NULL,
3966 };
3967
3968 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3969 &dra7xx_l4_per3__usb_otg_ss4,
3970 NULL,
3971 };
3972
3973 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3974 NULL,
3975 };
3976
3977 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
3978 &dra7xx_l4_per3__rtcss,
3979 NULL,
3980 };
3981
3982 int __init dra7xx_hwmod_init(void)
3983 {
3984 int ret;
3985
3986 omap_hwmod_init();
3987 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3988
3989 if (!ret && soc_is_dra74x()) {
3990 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3991 if (!ret)
3992 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
3993 } else if (!ret && soc_is_dra72x()) {
3994 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3995 if (!ret && !of_machine_is_compatible("ti,dra718"))
3996 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
3997 } else if (!ret && soc_is_dra76x()) {
3998 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
3999
4000 if (!ret && soc_is_dra76x_acd()) {
4001 ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
4002 } else if (!ret && soc_is_dra76x_abz()) {
4003 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4004 }
4005 }
4006
4007 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4008 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4009
4010 return ret;
4011 }
A mirror of Linus' kernel repository