1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Based on original Kirkwood support which is
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
14 #include <asm/cache.h>
16 #include <u-boot/md5.h>
17 #include <asm/arch/cpu.h>
21 void reset_cpu(unsigned long ignored
)
23 struct orion5x_cpu_registers
*cpureg
=
24 (struct orion5x_cpu_registers
*)ORION5X_CPU_REG_BASE
;
26 writel(readl(&cpureg
->rstoutn_mask
) | (1 << 2),
27 &cpureg
->rstoutn_mask
);
28 writel(readl(&cpureg
->sys_soft_rst
) | 1,
29 &cpureg
->sys_soft_rst
);
35 * Compute Window Size field value from size expressed in bytes
36 * Used with the Base register to set the address window size and location.
37 * Must be programmed from LSB to MSB as sequence of ones followed by
38 * sequence of zeros. The number of ones specifies the size of the window in
39 * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
41 * 1) A sizeval equal to 0x0 specifies 4 GiB.
42 * 2) A return value of 0x0 specifies 64 KiB.
44 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval
)
47 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
48 * For sizeval > 0 this is equivalent to:
49 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
51 sizeval
= (sizeval
- 1) >> 16;
54 * Propagate 'one' bits to the right by 'oring' them.
55 * We need only treat bits 15-0.
57 sizeval
|= sizeval
>> 1; /* 'Or' bit 15 onto bit 14 */
58 sizeval
|= sizeval
>> 2; /* 'Or' bits 15-14 onto bits 13-12 */
59 sizeval
|= sizeval
>> 4; /* 'Or' bits 15-12 onto bits 11-8 */
60 sizeval
|= sizeval
>> 8; /* 'Or' bits 15-8 onto bits 7-0*/
66 * orion5x_config_adr_windows - Configure address Windows
68 * There are 8 address windows supported by Orion5x Soc to addess different
69 * devices. Each window can be configured for size, BAR and remap addr
70 * Below configuration is standard for most of the cases
72 * If remap function not used, remap_lo must be set as base
76 * 1) in order to avoid windows with inconsistent control and base values
77 * (which could prevent access to BOOTCS and hence execution from FLASH)
78 * always disable window before writing the base value then reenable it
79 * by writing the control value.
81 * 2) in order to avoid losing access to BOOTCS when disabling window 7,
82 * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
83 * then configure windows 6 for its own target.
85 * Reference Documentation:
86 * Mbus-L to Mbus Bridge Registers Configuration.
87 * (Sec 25.1 and 25.3 of Datasheet)
89 int orion5x_config_adr_windows(void)
91 struct orion5x_win_registers
*winregs
=
92 (struct orion5x_win_registers
*)ORION5X_CPU_WIN_BASE
;
94 /* Disable window 0, configure it for its intended target, enable it. */
95 writel(0, &winregs
[0].ctrl
);
96 writel(ORION5X_ADR_PCIE_MEM
, &winregs
[0].base
);
97 writel(ORION5X_ADR_PCIE_MEM_REMAP_LO
, &winregs
[0].remap_lo
);
98 writel(ORION5X_ADR_PCIE_MEM_REMAP_HI
, &winregs
[0].remap_hi
);
99 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM
,
100 ORION5X_TARGET_PCIE
, ORION5X_ATTR_PCIE_MEM
,
101 ORION5X_WIN_ENABLE
), &winregs
[0].ctrl
);
102 /* Disable window 1, configure it for its intended target, enable it. */
103 writel(0, &winregs
[1].ctrl
);
104 writel(ORION5X_ADR_PCIE_IO
, &winregs
[1].base
);
105 writel(ORION5X_ADR_PCIE_IO_REMAP_LO
, &winregs
[1].remap_lo
);
106 writel(ORION5X_ADR_PCIE_IO_REMAP_HI
, &winregs
[1].remap_hi
);
107 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO
,
108 ORION5X_TARGET_PCIE
, ORION5X_ATTR_PCIE_IO
,
109 ORION5X_WIN_ENABLE
), &winregs
[1].ctrl
);
110 /* Disable window 2, configure it for its intended target, enable it. */
111 writel(0, &winregs
[2].ctrl
);
112 writel(ORION5X_ADR_PCI_MEM
, &winregs
[2].base
);
113 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM
,
114 ORION5X_TARGET_PCI
, ORION5X_ATTR_PCI_MEM
,
115 ORION5X_WIN_ENABLE
), &winregs
[2].ctrl
);
116 /* Disable window 3, configure it for its intended target, enable it. */
117 writel(0, &winregs
[3].ctrl
);
118 writel(ORION5X_ADR_PCI_IO
, &winregs
[3].base
);
119 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO
,
120 ORION5X_TARGET_PCI
, ORION5X_ATTR_PCI_IO
,
121 ORION5X_WIN_ENABLE
), &winregs
[3].ctrl
);
122 /* Disable window 4, configure it for its intended target, enable it. */
123 writel(0, &winregs
[4].ctrl
);
124 writel(ORION5X_ADR_DEV_CS0
, &winregs
[4].base
);
125 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0
,
126 ORION5X_TARGET_DEVICE
, ORION5X_ATTR_DEV_CS0
,
127 ORION5X_WIN_ENABLE
), &winregs
[4].ctrl
);
128 /* Disable window 5, configure it for its intended target, enable it. */
129 writel(0, &winregs
[5].ctrl
);
130 writel(ORION5X_ADR_DEV_CS1
, &winregs
[5].base
);
131 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1
,
132 ORION5X_TARGET_DEVICE
, ORION5X_ATTR_DEV_CS1
,
133 ORION5X_WIN_ENABLE
), &winregs
[5].ctrl
);
134 /* Disable window 6, configure it for FLASH, enable it. */
135 writel(0, &winregs
[6].ctrl
);
136 writel(ORION5X_ADR_BOOTROM
, &winregs
[6].base
);
137 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM
,
138 ORION5X_TARGET_DEVICE
, ORION5X_ATTR_BOOTROM
,
139 ORION5X_WIN_ENABLE
), &winregs
[6].ctrl
);
140 /* Disable window 7, configure it for FLASH, enable it. */
141 writel(0, &winregs
[7].ctrl
);
142 writel(ORION5X_ADR_BOOTROM
, &winregs
[7].base
);
143 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM
,
144 ORION5X_TARGET_DEVICE
, ORION5X_ATTR_BOOTROM
,
145 ORION5X_WIN_ENABLE
), &winregs
[7].ctrl
);
146 /* Disable window 6, configure it for its intended target, enable it. */
147 writel(0, &winregs
[6].ctrl
);
148 writel(ORION5X_ADR_DEV_CS2
, &winregs
[6].base
);
149 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2
,
150 ORION5X_TARGET_DEVICE
, ORION5X_ATTR_DEV_CS2
,
151 ORION5X_WIN_ENABLE
), &winregs
[6].ctrl
);
157 * Orion5x identification is done through PCIE space.
160 u32
orion5x_device_id(void)
162 return readl(PCIE_DEV_ID_OFF
) >> 16;
165 u32
orion5x_device_rev(void)
167 return readl(PCIE_DEV_REV_OFF
) & 0xff;
170 #if defined(CONFIG_DISPLAY_CPUINFO)
172 /* Display device and revision IDs.
173 * This function must cover all known device/revision
174 * combinations, not only the one for which u-boot is
175 * compiled; this way, one can identify actual HW in
176 * case of a mismatch.
178 int print_cpuinfo(void)
180 char dev_str
[7]; /* room enough for 0x0000 plus null byte */
181 char rev_str
[5]; /* room enough for 0x00 plus null byte */
182 char *dev_name
= NULL
;
183 char *rev_name
= NULL
;
185 u32 dev
= orion5x_device_id();
186 u32 rev
= orion5x_device_rev();
188 if (dev
== MV88F5181_DEV_ID
) {
189 dev_name
= "MV88F5181";
190 if (rev
== MV88F5181_REV_B1
)
192 else if (rev
== MV88F5181L_REV_A1
) {
193 dev_name
= "MV88F5181L";
195 } else if (rev
== MV88F5181L_REV_A0
) {
196 dev_name
= "MV88F5181L";
199 } else if (dev
== MV88F5182_DEV_ID
) {
200 dev_name
= "MV88F5182";
201 if (rev
== MV88F5182_REV_A2
)
203 } else if (dev
== MV88F5281_DEV_ID
) {
204 dev_name
= "MV88F5281";
205 if (rev
== MV88F5281_REV_D2
)
207 else if (rev
== MV88F5281_REV_D1
)
209 else if (rev
== MV88F5281_REV_D0
)
211 } else if (dev
== MV88F6183_DEV_ID
) {
212 dev_name
= "MV88F6183";
213 if (rev
== MV88F6183_REV_B0
)
216 if (dev_name
== NULL
) {
217 sprintf(dev_str
, "0x%04x", dev
);
220 if (rev_name
== NULL
) {
221 sprintf(rev_str
, "0x%02x", rev
);
225 printf("SoC: Orion5x %s-%s\n", dev_name
, rev_name
);
229 #endif /* CONFIG_DISPLAY_CPUINFO */
231 #ifdef CONFIG_ARCH_CPU_INIT
232 int arch_cpu_init(void)
234 /* Enable and invalidate L2 cache in write through mode */
235 invalidate_l2_cache();
237 #ifdef CONFIG_SPL_BUILD
238 orion5x_config_adr_windows();
243 #endif /* CONFIG_ARCH_CPU_INIT */
246 * SOC specific misc init
248 #if defined(CONFIG_ARCH_MISC_INIT)
249 int arch_misc_init(void)
253 /*CPU streaming & write allocate */
254 temp
= readfr_extra_feature_reg();
255 temp
&= ~(1 << 28); /* disable wr alloc */
256 writefr_extra_feature_reg(temp
);
258 temp
= readfr_extra_feature_reg();
259 temp
&= ~(1 << 29); /* streaming disabled */
260 writefr_extra_feature_reg(temp
);
262 /* L2Cache settings */
263 temp
= readfr_extra_feature_reg();
264 /* Disable L2C pre fetch - Set bit 24 */
266 /* enable L2C - Set bit 22 */
268 writefr_extra_feature_reg(temp
);
271 /* Change reset vector to address 0x0 */
273 set_cr(temp
& ~CR_V
);
275 /* Set CPIOs and MPPs - values provided by board
277 writel(ORION5X_MPP0_7
, ORION5X_MPP_BASE
+0x00);
278 writel(ORION5X_MPP8_15
, ORION5X_MPP_BASE
+0x04);
279 writel(ORION5X_MPP16_23
, ORION5X_MPP_BASE
+0x50);
280 writel(ORION5X_GPIO_OUT_VALUE
, ORION5X_GPIO_BASE
+0x00);
281 writel(ORION5X_GPIO_OUT_ENABLE
, ORION5X_GPIO_BASE
+0x04);
282 writel(ORION5X_GPIO_IN_POLARITY
, ORION5X_GPIO_BASE
+0x0c);
284 /* initialize timer */
288 #endif /* CONFIG_ARCH_MISC_INIT */
291 int cpu_eth_init(bd_t
*bis
)
293 mvgbe_initialize(bis
);