arch/arm/mach-rmobile/include/mach/r8a7791.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * arch/arm/include/asm/arch-rmobile/r8a7791.h
   4  *
   5  * Copyright (C) 2013,2014 Renesas Electronics Corporation
   6  */
   7
   8 #ifndef __ASM_ARCH_R8A7791_H
   9 #define __ASM_ARCH_R8A7791_H
  10
  11 #include "rcar-base.h"
  12 /*
  13  * R-Car (R8A7791) I/O Addresses
  14  */
  15
  16 /* SDHI */
  17 #define CFG_SYS_SH_SDHI_NR_CHANNEL 3
  18
  19 #define DBSC3_1_QOS_R0_BASE     0xE67A1000
  20 #define DBSC3_1_QOS_R1_BASE     0xE67A1100
  21 #define DBSC3_1_QOS_R2_BASE     0xE67A1200
  22 #define DBSC3_1_QOS_R3_BASE     0xE67A1300
  23 #define DBSC3_1_QOS_R4_BASE     0xE67A1400
  24 #define DBSC3_1_QOS_R5_BASE     0xE67A1500
  25 #define DBSC3_1_QOS_R6_BASE     0xE67A1600
  26 #define DBSC3_1_QOS_R7_BASE     0xE67A1700
  27 #define DBSC3_1_QOS_R8_BASE     0xE67A1800
  28 #define DBSC3_1_QOS_R9_BASE     0xE67A1900
  29 #define DBSC3_1_QOS_R10_BASE    0xE67A1A00
  30 #define DBSC3_1_QOS_R11_BASE    0xE67A1B00
  31 #define DBSC3_1_QOS_R12_BASE    0xE67A1C00
  32 #define DBSC3_1_QOS_R13_BASE    0xE67A1D00
  33 #define DBSC3_1_QOS_R14_BASE    0xE67A1E00
  34 #define DBSC3_1_QOS_R15_BASE    0xE67A1F00
  35 #define DBSC3_1_QOS_W0_BASE     0xE67A2000
  36 #define DBSC3_1_QOS_W1_BASE     0xE67A2100
  37 #define DBSC3_1_QOS_W2_BASE     0xE67A2200
  38 #define DBSC3_1_QOS_W3_BASE     0xE67A2300
  39 #define DBSC3_1_QOS_W4_BASE     0xE67A2400
  40 #define DBSC3_1_QOS_W5_BASE     0xE67A2500
  41 #define DBSC3_1_QOS_W6_BASE     0xE67A2600
  42 #define DBSC3_1_QOS_W7_BASE     0xE67A2700
  43 #define DBSC3_1_QOS_W8_BASE     0xE67A2800
  44 #define DBSC3_1_QOS_W9_BASE     0xE67A2900
  45 #define DBSC3_1_QOS_W10_BASE    0xE67A2A00
  46 #define DBSC3_1_QOS_W11_BASE    0xE67A2B00
  47 #define DBSC3_1_QOS_W12_BASE    0xE67A2C00
  48 #define DBSC3_1_QOS_W13_BASE    0xE67A2D00
  49 #define DBSC3_1_QOS_W14_BASE    0xE67A2E00
  50 #define DBSC3_1_QOS_W15_BASE    0xE67A2F00
  51 #define DBSC3_1_DBADJ2          0xE67A00C8
  52
  53 /* Module stop control/status register bits */
  54 #define MSTP0_BITS      0x00640801
  55 #define MSTP1_BITS      0x9B6C9B5A
  56 #define MSTP2_BITS      0x100D21FC
  57 #define MSTP3_BITS      0xF08CD810
  58 #define MSTP4_BITS      0x800001C4
  59 #define MSTP5_BITS      0x44C00046
  60 #define MSTP7_BITS      0x05BFE618
  61 #define MSTP8_BITS      0x40C0FE85
  62 #define MSTP9_BITS      0xFF979FFF
  63 #define MSTP10_BITS     0xFFFEFFE0
  64 #define MSTP11_BITS     0x000001C0
  65
  66 #define R8A7791_CUT_ES2X        2
  67 #define IS_R8A7791_ES2()        \
  68         (renesas_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
  69
  70 #endif /* __ASM_ARCH_R8A7791_H */