arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
   4  *
   5  * Copyright (C) 2015 Renesas Electronics Corporation
   6  */
   7
   8 #ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
   9 #define __ASM_ARCH_RCAR_GEN3_BASE_H
  10
  11 /*
  12  * R-Car (R8A7750) I/O Addresses
  13  */
  14 #define RWDT_BASE               0xE6020000
  15 #define SWDT_BASE               0xE6030000
  16 #define LBSC_BASE               0xEE220200
  17 #define TMU_BASE                0xE61E0000
  18 #define GPIO5_BASE              0xE6055000
  19
  20 /* SCIF */
  21 #define SCIF0_BASE              0xE6E60000
  22 #define SCIF1_BASE              0xE6E68000
  23 #define SCIF2_BASE              0xE6E88000
  24 #define SCIF3_BASE              0xE6C50000
  25 #define SCIF4_BASE              0xE6C40000
  26 #define SCIF5_BASE              0xE6F30000
  27
  28 /* Module stop status register */
  29 #define MSTPSR0                 0xE6150030
  30 #define MSTPSR1                 0xE6150038
  31 #define MSTPSR2                 0xE6150040
  32 #define MSTPSR3                 0xE6150048
  33 #define MSTPSR4                 0xE615004C
  34 #define MSTPSR5                 0xE615003C
  35 #define MSTPSR6                 0xE61501C0
  36 #define MSTPSR7                 0xE61501C4
  37 #define MSTPSR8                 0xE61509A0
  38 #define MSTPSR9                 0xE61509A4
  39 #define MSTPSR10                0xE61509A8
  40 #define MSTPSR11                0xE61509AC
  41
  42 /* Realtime module stop control register */
  43 #define RMSTPCR0                0xE6150110
  44 #define RMSTPCR1                0xE6150114
  45 #define RMSTPCR2                0xE6150118
  46 #define RMSTPCR3                0xE615011C
  47 #define RMSTPCR4                0xE6150120
  48 #define RMSTPCR5                0xE6150124
  49 #define RMSTPCR6                0xE6150128
  50 #define RMSTPCR7                0xE615012C
  51 #define RMSTPCR8                0xE6150980
  52 #define RMSTPCR9                0xE6150984
  53 #define RMSTPCR10               0xE6150988
  54 #define RMSTPCR11               0xE615098C
  55
  56 /* System module stop control register */
  57 #define SMSTPCR0                0xE6150130
  58 #define SMSTPCR1                0xE6150134
  59 #define SMSTPCR2                0xE6150138
  60 #define SMSTPCR3                0xE615013C
  61 #define SMSTPCR4                0xE6150140
  62 #define SMSTPCR5                0xE6150144
  63 #define SMSTPCR6                0xE6150148
  64 #define SMSTPCR7                0xE615014C
  65 #define SMSTPCR8                0xE6150990
  66 #define SMSTPCR9                0xE6150994
  67 #define SMSTPCR10               0xE6150998
  68 #define SMSTPCR11               0xE615099C
  69
  70 /* PFC */
  71 #define PFC_PUEN5       0xE6060414
  72 #define PUEN_SSI_SDATA4 BIT(17)
  73 #define PFC_PUEN6       0xE6060418
  74 #define PUEN_USB1_OVC   (1 << 2)
  75 #define PUEN_USB1_PWEN  (1 << 1)
  76
  77 #ifndef __ASSEMBLY__
  78 #include <asm/types.h>
  79 #include <linux/bitops.h>
  80
  81 /* RWDT */
  82 struct rcar_rwdt {
  83         u32 rwtcnt;
  84         u32 rwtcsra;
  85         u32 rwtcsrb;
  86 };
  87
  88 /* SWDT */
  89 struct rcar_swdt {
  90         u32 swtcnt;
  91         u32 swtcsra;
  92         u32 swtcsrb;
  93 };
  94 #endif
  95
  96 #endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */