arch/arm/mach-rmobile/include/mach/sh_sdhi.h

   1 /*
   2  * drivers/mmc/sh-sdhi.h
   3  *
   4  * SD/MMC driver for Renesas rmobile ARM SoCs
   5  *
   6  * Copyright (C) 2013-2017 Renesas Electronics Corporation
   7  * Copyright (C) 2008-2009 Renesas Solutions Corp.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0
  10  */
  11
  12 #ifndef _SH_SDHI_H
  13 #define _SH_SDHI_H
  14
  15 #define SDHI_CMD                        (0x0000 >> 1)
  16 #define SDHI_PORTSEL                    (0x0004 >> 1)
  17 #define SDHI_ARG0                       (0x0008 >> 1)
  18 #define SDHI_ARG1                       (0x000C >> 1)
  19 #define SDHI_STOP                       (0x0010 >> 1)
  20 #define SDHI_SECCNT                     (0x0014 >> 1)
  21 #define SDHI_RSP00                      (0x0018 >> 1)
  22 #define SDHI_RSP01                      (0x001C >> 1)
  23 #define SDHI_RSP02                      (0x0020 >> 1)
  24 #define SDHI_RSP03                      (0x0024 >> 1)
  25 #define SDHI_RSP04                      (0x0028 >> 1)
  26 #define SDHI_RSP05                      (0x002C >> 1)
  27 #define SDHI_RSP06                      (0x0030 >> 1)
  28 #define SDHI_RSP07                      (0x0034 >> 1)
  29 #define SDHI_INFO1                      (0x0038 >> 1)
  30 #define SDHI_INFO2                      (0x003C >> 1)
  31 #define SDHI_INFO1_MASK                 (0x0040 >> 1)
  32 #define SDHI_INFO2_MASK                 (0x0044 >> 1)
  33 #define SDHI_CLK_CTRL                   (0x0048 >> 1)
  34 #define SDHI_SIZE                       (0x004C >> 1)
  35 #define SDHI_OPTION                     (0x0050 >> 1)
  36 #define SDHI_ERR_STS1                   (0x0058 >> 1)
  37 #define SDHI_ERR_STS2                   (0x005C >> 1)
  38 #define SDHI_BUF0                       (0x0060 >> 1)
  39 #define SDHI_SDIO_MODE                  (0x0068 >> 1)
  40 #define SDHI_SDIO_INFO1                 (0x006C >> 1)
  41 #define SDHI_SDIO_INFO1_MASK            (0x0070 >> 1)
  42 #define SDHI_CC_EXT_MODE                (0x01B0 >> 1)
  43 #define SDHI_SOFT_RST                   (0x01C0 >> 1)
  44 #define SDHI_VERSION                    (0x01C4 >> 1)
  45 #define SDHI_HOST_MODE                  (0x01C8 >> 1)
  46 #define SDHI_SDIF_MODE                  (0x01CC >> 1)
  47 #define SDHI_EXT_SWAP                   (0x01E0 >> 1)
  48 #define SDHI_SD_DMACR                   (0x0324 >> 1)
  49
  50 /* SDHI CMD VALUE */
  51 #define CMD_MASK                        0x0000ffff
  52 #define SDHI_APP                        0x0040
  53 #define SDHI_MMC_SEND_OP_COND           0x0701
  54 #define SDHI_SD_APP_SEND_SCR            0x0073
  55 #define SDHI_SD_SWITCH                  0x1C06
  56 #define SDHI_MMC_SEND_EXT_CSD           0x1C08
  57
  58 /* SDHI_PORTSEL */
  59 #define USE_1PORT                       (1 << 8) /* 1 port */
  60
  61 /* SDHI_ARG */
  62 #define ARG0_MASK                       0x0000ffff
  63 #define ARG1_MASK                       0x0000ffff
  64
  65 /* SDHI_STOP */
  66 #define STOP_SEC_ENABLE                 (1 << 8)
  67
  68 /* SDHI_INFO1 */
  69 #define INFO1_RESP_END                  (1 << 0)
  70 #define INFO1_ACCESS_END                (1 << 2)
  71 #define INFO1_CARD_RE                   (1 << 3)
  72 #define INFO1_CARD_IN                   (1 << 4)
  73 #define INFO1_ISD0CD                    (1 << 5)
  74 #define INFO1_WRITE_PRO                 (1 << 7)
  75 #define INFO1_DATA3_CARD_RE             (1 << 8)
  76 #define INFO1_DATA3_CARD_IN             (1 << 9)
  77 #define INFO1_DATA3                     (1 << 10)
  78
  79 /* SDHI_INFO2 */
  80 #define INFO2_CMD_ERROR                 (1 << 0)
  81 #define INFO2_CRC_ERROR                 (1 << 1)
  82 #define INFO2_END_ERROR                 (1 << 2)
  83 #define INFO2_TIMEOUT                   (1 << 3)
  84 #define INFO2_BUF_ILL_WRITE             (1 << 4)
  85 #define INFO2_BUF_ILL_READ              (1 << 5)
  86 #define INFO2_RESP_TIMEOUT              (1 << 6)
  87 #define INFO2_SDDAT0                    (1 << 7)
  88 #define INFO2_BRE_ENABLE                (1 << 8)
  89 #define INFO2_BWE_ENABLE                (1 << 9)
  90 #define INFO2_CBUSY                     (1 << 14)
  91 #define INFO2_ILA                       (1 << 15)
  92 #define INFO2_ALL_ERR                   (0x807f)
  93
  94 /* SDHI_INFO1_MASK */
  95 #define INFO1M_RESP_END                 (1 << 0)
  96 #define INFO1M_ACCESS_END               (1 << 2)
  97 #define INFO1M_CARD_RE                  (1 << 3)
  98 #define INFO1M_CARD_IN                  (1 << 4)
  99 #define INFO1M_DATA3_CARD_RE            (1 << 8)
 100 #define INFO1M_DATA3_CARD_IN            (1 << 9)
 101 #define INFO1M_ALL                      (0xffff)
 102 #define INFO1M_SET                      (INFO1M_RESP_END |      \
 103                                         INFO1M_ACCESS_END |     \
 104                                         INFO1M_DATA3_CARD_RE |  \
 105                                         INFO1M_DATA3_CARD_IN)
 106
 107 /* SDHI_INFO2_MASK */
 108 #define INFO2M_CMD_ERROR                (1 << 0)
 109 #define INFO2M_CRC_ERROR                (1 << 1)
 110 #define INFO2M_END_ERROR                (1 << 2)
 111 #define INFO2M_TIMEOUT                  (1 << 3)
 112 #define INFO2M_BUF_ILL_WRITE            (1 << 4)
 113 #define INFO2M_BUF_ILL_READ             (1 << 5)
 114 #define INFO2M_RESP_TIMEOUT             (1 << 6)
 115 #define INFO2M_BRE_ENABLE               (1 << 8)
 116 #define INFO2M_BWE_ENABLE               (1 << 9)
 117 #define INFO2M_ILA                      (1 << 15)
 118 #define INFO2M_ALL                      (0xffff)
 119 #define INFO2M_ALL_ERR                  (0x807f)
 120
 121 /* SDHI_CLK_CTRL */
 122 #define CLK_ENABLE                      (1 << 8)
 123
 124 /* SDHI_OPTION */
 125 #define OPT_BUS_WIDTH_M                 (5 << 13)       /* 101b (15-13bit) */
 126 #define OPT_BUS_WIDTH_1                 (4 << 13)       /* bus width = 1 bit */
 127 #define OPT_BUS_WIDTH_4                 (0 << 13)       /* bus width = 4 bit */
 128 #define OPT_BUS_WIDTH_8                 (1 << 13)       /* bus width = 8 bit */
 129
 130 /* SDHI_ERR_STS1 */
 131 #define ERR_STS1_CRC_ERROR              ((1 << 11) | (1 << 10) | (1 << 9) | \
 132                                         (1 << 8) | (1 << 5))
 133 #define ERR_STS1_CMD_ERROR              ((1 << 4) | (1 << 3) | (1 << 2) | \
 134                                         (1 << 1) | (1 << 0))
 135
 136 /* SDHI_ERR_STS2 */
 137 #define ERR_STS2_RES_TIMEOUT            (1 << 0)
 138 #define ERR_STS2_RES_STOP_TIMEOUT       ((1 << 0) | (1 << 1))
 139 #define ERR_STS2_SYS_ERROR              ((1 << 6) | (1 << 5) | (1 << 4) | \
 140                                         (1 << 3) | (1 << 2) | (1 << 1) | \
 141                                         (1 << 0))
 142
 143 /* SDHI_SDIO_MODE */
 144 #define SDIO_MODE_ON                    (1 << 0)
 145 #define SDIO_MODE_OFF                   (0 << 0)
 146
 147 /* SDHI_SDIO_INFO1 */
 148 #define SDIO_INFO1_IOIRQ                (1 << 0)
 149 #define SDIO_INFO1_EXPUB52              (1 << 14)
 150 #define SDIO_INFO1_EXWT                 (1 << 15)
 151
 152 /* SDHI_SDIO_INFO1_MASK */
 153 #define SDIO_INFO1M_CLEAR               ((1 << 1) | (1 << 2))
 154 #define SDIO_INFO1M_ON                  ((1 << 15) | (1 << 14) | (1 << 2) | \
 155                                          (1 << 1) | (1 << 0))
 156
 157 /* SDHI_EXT_SWAP */
 158 #define SET_SWAP                        ((1 << 6) | (1 << 7))   /* SWAP */
 159
 160 /* SDHI_SOFT_RST */
 161 #define SOFT_RST_ON                     (0 << 0)
 162 #define SOFT_RST_OFF                    (1 << 0)
 163
 164 #define CLKDEV_SD_DATA                  25000000        /* 25 MHz */
 165 #define CLKDEV_HS_DATA                  50000000        /* 50 MHz */
 166 #define CLKDEV_MMC_DATA                 20000000        /* 20MHz */
 167 #define CLKDEV_INIT                     400000          /* 100 - 400 KHz */
 168
 169 /* For quirk */
 170 #define SH_SDHI_QUIRK_16BIT_BUF         BIT(0)
 171 #define SH_SDHI_QUIRK_64BIT_BUF         BIT(1)
 172
 173 int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
 174
 175 #endif /* _SH_SDHI_H */