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rockchip: make boot_mode related codes reused across all platforms
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1 if ARCH_ROCKCHIP
2
3 config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
5 select CPU_V7
6 select SUPPORT_SPL
7 select SPL
8 help
9 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
10 including NEON and GPU, Mali-400 graphics, several DDR3 options
11 and video codec support. Peripherals include Gigabit Ethernet,
12 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
13
14 config ROCKCHIP_RK3188
15 bool "Support Rockchip RK3188"
16 select CPU_V7
17 select SPL_BOARD_INIT if SPL
18 select SUPPORT_SPL
19 select SPL
20 select SPL_CLK
21 select SPL_PINCTRL
22 select SPL_REGMAP
23 select SPL_SYSCON
24 select SPL_RAM
25 select SPL_DRIVERS_MISC_SUPPORT
26 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
27 select BOARD_LATE_INIT
28 select ROCKCHIP_BROM_HELPER
29 help
30 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
31 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
32 video interfaces, several memory options and video codec support.
33 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
34 UART, SPI, I2C and PWMs.
35
36 config ROCKCHIP_RK322X
37 bool "Support Rockchip RK3228/RK3229"
38 select CPU_V7
39 select SUPPORT_SPL
40 select SPL
41 select ROCKCHIP_BROM_HELPER
42 select DEBUG_UART_BOARD_INIT
43 help
44 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
45 including NEON and GPU, Mali-400 graphics, several DDR3 options
46 and video codec support. Peripherals include Gigabit Ethernet,
47 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
48
49 config ROCKCHIP_RK3288
50 bool "Support Rockchip RK3288"
51 select CPU_V7
52 select SPL_BOARD_INIT if SPL
53 select SUPPORT_SPL
54 select SPL
55 help
56 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
57 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
58 video interfaces supporting HDMI and eDP, several DDR3 options
59 and video codec support. Peripherals include Gigabit Ethernet,
60 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
61
62 config ROCKCHIP_RK3328
63 bool "Support Rockchip RK3328"
64 select ARM64
65 help
66 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
67 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
68 video interfaces supporting HDMI and eDP, several DDR3 options
69 and video codec support. Peripherals include Gigabit Ethernet,
70 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
71
72 config ROCKCHIP_RK3368
73 bool "Support Rockchip RK3368"
74 select ARM64
75 select SUPPORT_SPL
76 select SUPPORT_TPL
77 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
78 select TPL_NEEDS_SEPARATE_STACK if TPL
79 imply SPL_SEPARATE_BSS
80 imply SPL_SERIAL_SUPPORT
81 imply TPL_SERIAL_SUPPORT
82 select DEBUG_UART_BOARD_INIT
83 select SYS_NS16550
84 help
85 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
86 into a big and little cluster with 4 cores each) Cortex-A53 including
87 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
88 (for the little cluster), PowerVR G6110 based graphics, one video
89 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
90 video codec support.
91
92 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
93 I2S, UARTs, SPI, I2C and PWMs.
94
95 if ROCKCHIP_RK3368
96
97 config TPL_LDSCRIPT
98 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
99
100 config TPL_TEXT_BASE
101 default 0xff8c1000
102
103 config TPL_MAX_SIZE
104 default 28672
105
106 config TPL_STACK
107 default 0xff8cffff
108
109 endif
110
111 config ROCKCHIP_RK3399
112 bool "Support Rockchip RK3399"
113 select ARM64
114 select SUPPORT_SPL
115 select SPL
116 select SPL_SEPARATE_BSS
117 select SPL_SERIAL_SUPPORT
118 select SPL_DRIVERS_MISC_SUPPORT
119 select DEBUG_UART_BOARD_INIT
120 select BOARD_LATE_INIT
121 help
122 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
123 and quad-core Cortex-A53.
124 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
125 video interfaces supporting HDMI and eDP, several DDR3 options
126 and video codec support. Peripherals include Gigabit Ethernet,
127 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
128
129 config ROCKCHIP_RV1108
130 bool "Support Rockchip RV1108"
131 select CPU_V7
132 help
133 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
134 and a DSP.
135
136 config SPL_ROCKCHIP_BACK_TO_BROM
137 bool "SPL returns to bootrom"
138 default y if ROCKCHIP_RK3036
139 select ROCKCHIP_BROM_HELPER
140 depends on SPL
141 help
142 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
143 SPL will return to the boot rom, which will then load the U-Boot
144 binary to keep going on.
145
146 config TPL_ROCKCHIP_BACK_TO_BROM
147 bool "TPL returns to bootrom"
148 default y if ROCKCHIP_RK3368
149 select ROCKCHIP_BROM_HELPER
150 depends on TPL
151 help
152 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
153 SPL will return to the boot rom, which will then load the U-Boot
154 binary to keep going on.
155
156 config ROCKCHIP_BOOT_MODE_REG
157 hex "Rockchip boot mode flag register address"
158 default 0x200081c8 if ROCKCHIP_RK3036
159 default 0x20004040 if ROCKCHIP_RK3188
160 default 0x110005c8 if ROCKCHIP_RK322X
161 default 0xff730094 if ROCKCHIP_RK3288
162 default 0xff738200 if ROCKCHIP_RK3368
163 default 0xff320300 if ROCKCHIP_RK3399
164 default 0x10300580 if ROCKCHIP_RV1108
165 default 0
166 help
167 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
168 according to the value from this register.
169
170 config ROCKCHIP_SPL_RESERVE_IRAM
171 hex "Size of IRAM reserved in SPL"
172 default 0x4000
173 help
174 SPL may need reserve memory for firmware loaded by SPL, whose load
175 address is in IRAM and may overlay with SPL text area if not
176 reserved.
177
178 config ROCKCHIP_BROM_HELPER
179 bool
180
181 config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
182 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
183 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
184 help
185 Some Rockchip BROM variants (e.g. on the RK3188) load the
186 first stage in segments and enter multiple times. E.g. on
187 the RK3188, the first 1KB of the first stage are loaded
188 first and entered; after returning to the BROM, the
189 remainder of the first stage is loaded, but the BROM
190 re-enters at the same address/to the same code as previously.
191
192 This enables support code in the BOOT0 hook for the SPL stage
193 to allow multiple entries.
194
195 config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
196 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
197 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
198 help
199 Some Rockchip BROM variants (e.g. on the RK3188) load the
200 first stage in segments and enter multiple times. E.g. on
201 the RK3188, the first 1KB of the first stage are loaded
202 first and entered; after returning to the BROM, the
203 remainder of the first stage is loaded, but the BROM
204 re-enters at the same address/to the same code as previously.
205
206 This enables support code in the BOOT0 hook for the TPL stage
207 to allow multiple entries.
208
209 config SPL_MMC_SUPPORT
210 default y if !SPL_ROCKCHIP_BACK_TO_BROM
211
212 source "arch/arm/mach-rockchip/rk3036/Kconfig"
213 source "arch/arm/mach-rockchip/rk3188/Kconfig"
214 source "arch/arm/mach-rockchip/rk322x/Kconfig"
215 source "arch/arm/mach-rockchip/rk3288/Kconfig"
216 source "arch/arm/mach-rockchip/rk3328/Kconfig"
217 source "arch/arm/mach-rockchip/rk3368/Kconfig"
218 source "arch/arm/mach-rockchip/rk3399/Kconfig"
219 source "arch/arm/mach-rockchip/rv1108/Kconfig"
220 endif