arch/arm/mach-rockchip/rk3128-board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   4  */
   5 #include <common.h>
   6 #include <clk.h>
   7 #include <dm.h>
   8 #include <ram.h>
   9 #include <syscon.h>
  10 #include <asm/io.h>
  11 #include <asm/arch-rockchip/clock.h>
  12 #include <asm/arch-rockchip/periph.h>
  13 #include <asm/arch-rockchip/grf_rk3128.h>
  14 #include <asm/arch-rockchip/boot_mode.h>
  15 #include <power/regulator.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 __weak int rk_board_late_init(void)
  20 {
  21         return 0;
  22 }
  23
  24 int board_late_init(void)
  25 {
  26         setup_boot_mode();
  27
  28         return rk_board_late_init();
  29 }
  30
  31 int board_init(void)
  32 {
  33         int ret = 0;
  34
  35         ret = regulators_enable_boot_on(false);
  36         if (ret) {
  37                 debug("%s: Cannot enable boot on regulator\n", __func__);
  38                 return ret;
  39         }
  40
  41         return 0;
  42 }
  43
  44 int dram_init_banksize(void)
  45 {
  46         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  47         gd->bd->bi_dram[0].size = 0x8400000;
  48         /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
  49         gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  50                                 + gd->bd->bi_dram[0].size + 0xe00000;
  51         gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  52                                 + gd->ram_size - gd->bd->bi_dram[1].start;
  53
  54         return 0;
  55 }
  56
  57 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  58 void enable_caches(void)
  59 {
  60         /* Enable D-cache. I-cache is already enabled in start.S */
  61         dcache_enable();
  62 }
  63 #endif
  64
  65 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  66 #include <usb.h>
  67 #include <usb/dwc2_udc.h>
  68
  69 static struct dwc2_plat_otg_data rk3128_otg_data = {
  70         .rx_fifo_sz     = 512,
  71         .np_tx_fifo_sz  = 16,
  72         .tx_fifo_sz     = 128,
  73 };
  74
  75 int board_usb_init(int index, enum usb_init_type init)
  76 {
  77         int node;
  78         const char *mode;
  79         bool matched = false;
  80         const void *blob = gd->fdt_blob;
  81
  82         /* find the usb_otg node */
  83         node = fdt_node_offset_by_compatible(blob, -1,
  84                                              "rockchip,rk3128-usb");
  85
  86         while (node > 0) {
  87                 mode = fdt_getprop(blob, node, "dr_mode", NULL);
  88                 if (mode && strcmp(mode, "otg") == 0) {
  89                         matched = true;
  90                         break;
  91                 }
  92
  93                 node = fdt_node_offset_by_compatible(blob, node,
  94                                                      "rockchip,rk3128-usb");
  95         }
  96         if (!matched) {
  97                 debug("Not found usb_otg device\n");
  98                 return -ENODEV;
  99         }
 100         rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
 101
 102         return dwc2_udc_probe(&rk3128_otg_data);
 103 }
 104
 105 int board_usb_cleanup(int index, enum usb_init_type init)
 106 {
 107         return 0;
 108 }
 109 #endif
 110
 111 #if CONFIG_IS_ENABLED(FASTBOOT)
 112 int fastboot_set_reboot_flag(void)
 113 {
 114         printf("Setting reboot to fastboot flag ...\n");
 115         /* Set boot mode to fastboot */
 116         writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
 117
 118         return 0;
 119 }
 120 #endif