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rockchip: timer: make register sizes explicit
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1 /*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <ram.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/periph.h>
13 #include <asm/arch/grf_rk322x.h>
14 #include <asm/arch/boot_mode.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define GRF_BASE 0x11000000
19
20 static void setup_boot_mode(void)
21 {
22 struct rk322x_grf *const grf = (void *)GRF_BASE;
23 int boot_mode = readl(&grf->os_reg[4]);
24
25 debug("boot mode %x.\n", boot_mode);
26
27 /* Clear boot mode */
28 writel(BOOT_NORMAL, &grf->os_reg[4]);
29
30 switch (boot_mode) {
31 case BOOT_FASTBOOT:
32 printf("enter fastboot!\n");
33 setenv("preboot", "setenv preboot; fastboot usb0");
34 break;
35 case BOOT_UMS:
36 printf("enter UMS!\n");
37 setenv("preboot", "setenv preboot; ums mmc 0");
38 break;
39 }
40 }
41
42 __weak int rk_board_late_init(void)
43 {
44 return 0;
45 }
46
47 int board_late_init(void)
48 {
49 setup_boot_mode();
50
51 return rk_board_late_init();
52 }
53
54 int board_init(void)
55 {
56 #include <asm/arch/grf_rk322x.h>
57 /* Enable early UART2 channel 1 on the RK322x */
58 #define GRF_BASE 0x11000000
59 struct rk322x_grf * const grf = (void *)GRF_BASE;
60
61 rk_clrsetreg(&grf->gpio1b_iomux,
62 GPIO1B1_MASK | GPIO1B2_MASK,
63 GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
64 GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
65 /* Set channel C as UART2 input */
66 rk_clrsetreg(&grf->con_iomux,
67 CON_IOMUX_UART2SEL_MASK,
68 CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
69
70 return 0;
71 }
72
73 int dram_init_banksize(void)
74 {
75 /* Reserve 0x200000 for OPTEE */
76 gd->bd->bi_dram[0].start = 0x60000000;
77 gd->bd->bi_dram[0].size = 0x8400000;
78 gd->bd->bi_dram[1].start = 0x6a400000;
79 gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start;
80
81 return 0;
82 }
83
84 #ifndef CONFIG_SYS_DCACHE_OFF
85 void enable_caches(void)
86 {
87 /* Enable D-cache. I-cache is already enabled in start.S */
88 dcache_enable();
89 }
90 #endif
91
92 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
93 #include <usb.h>
94 #include <usb/dwc2_udc.h>
95
96 static struct dwc2_plat_otg_data rk322x_otg_data = {
97 .rx_fifo_sz = 512,
98 .np_tx_fifo_sz = 16,
99 .tx_fifo_sz = 128,
100 };
101
102 int board_usb_init(int index, enum usb_init_type init)
103 {
104 int node;
105 const char *mode;
106 bool matched = false;
107 const void *blob = gd->fdt_blob;
108
109 /* find the usb_otg node */
110 node = fdt_node_offset_by_compatible(blob, -1,
111 "rockchip,rk3288-usb");
112
113 while (node > 0) {
114 mode = fdt_getprop(blob, node, "dr_mode", NULL);
115 if (mode && strcmp(mode, "otg") == 0) {
116 matched = true;
117 break;
118 }
119
120 node = fdt_node_offset_by_compatible(blob, node,
121 "rockchip,rk3288-usb");
122 }
123 if (!matched) {
124 debug("Not found usb_otg device\n");
125 return -ENODEV;
126 }
127 rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
128
129 return dwc2_udc_probe(&rk322x_otg_data);
130 }
131
132 int board_usb_cleanup(int index, enum usb_init_type init)
133 {
134 return 0;
135 }
136 #endif