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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/arm/mach-rockchip/rk3288/rk3288.c
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
11 #include <asm/armv7.h>
13 #include <asm/arch-rockchip/bootrom.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <asm/arch-rockchip/grf_rk3288.h>
18 #include <asm/arch-rockchip/pmu_rk3288.h>
19 #include <asm/arch-rockchip/qos_rk3288.h>
20 #include <asm/arch-rockchip/sdram.h>
21 #include <linux/err.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #define GRF_BASE 0xff770000
27 const char * const boot_devices
[BROM_LAST_BOOTSOURCE
+ 1] = {
28 [BROM_BOOTSOURCE_EMMC
] = "/dwmmc@ff0f0000",
29 [BROM_BOOTSOURCE_SD
] = "/dwmmc@ff0c0000",
32 #ifdef CONFIG_SPL_BUILD
33 static void configure_l2ctlr(void)
37 l2ctlr
= read_l2ctlr();
38 l2ctlr
&= 0xfffc0000; /* clear bit0~bit17 */
41 * Data RAM write latency: 2 cycles
42 * Data RAM read latency: 2 cycles
43 * Data RAM setup latency: 1 cycle
44 * Tag RAM write latency: 1 cycle
45 * Tag RAM read latency: 1 cycle
46 * Tag RAM setup latency: 1 cycle
48 l2ctlr
|= (1 << 3 | 1 << 0);
53 int rk3288_qos_init(void)
55 int val
= 2 << PRIORITY_HIGH_SHIFT
| 2 << PRIORITY_LOW_SHIFT
;
56 /* set vop qos to higher priority */
57 writel(val
, CPU_AXI_QOS_PRIORITY
+ VIO0_VOP_QOS
);
58 writel(val
, CPU_AXI_QOS_PRIORITY
+ VIO1_VOP_QOS
);
60 if (!fdt_node_check_compatible(gd
->fdt_blob
, 0,
61 "rockchip,rk3288-tinker")) {
62 /* set isp qos to higher priority */
63 writel(val
, CPU_AXI_QOS_PRIORITY
+ VIO1_ISP_R_QOS
);
64 writel(val
, CPU_AXI_QOS_PRIORITY
+ VIO1_ISP_W0_QOS
);
65 writel(val
, CPU_AXI_QOS_PRIORITY
+ VIO1_ISP_W1_QOS
);
71 int arch_cpu_init(void)
73 #ifdef CONFIG_SPL_BUILD
76 /* We do some SoC one time setting here. */
77 struct rk3288_grf
* const grf
= (void *)GRF_BASE
;
79 /* Use rkpwm by default */
80 rk_setreg(&grf
->soc_con2
, 1 << 0);
83 * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
86 rk_clrreg(&grf
->soc_con0
, 1 << 12);
94 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
95 void board_debug_uart_init(void)
97 /* Enable early UART on the RK3288 */
98 struct rk3288_grf
* const grf
= (void *)GRF_BASE
;
100 rk_clrsetreg(&grf
->gpio7ch_iomux
, GPIO7C7_MASK
<< GPIO7C7_SHIFT
|
101 GPIO7C6_MASK
<< GPIO7C6_SHIFT
,
102 GPIO7C7_UART2DBG_SOUT
<< GPIO7C7_SHIFT
|
103 GPIO7C6_UART2DBG_SIN
<< GPIO7C6_SHIFT
);
107 __weak
int rk3288_board_late_init(void)
112 int rk_board_late_init(void)
114 return rk3288_board_late_init();
117 static int do_clock(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
120 static const struct {
127 { "cpll", CLK_CODEC
},
128 { "gpll", CLK_GENERAL
},
129 #ifdef CONFIG_ROCKCHIP_RK3036
138 ret
= rockchip_get_clk(&dev
);
140 printf("clk-uclass not found\n");
144 for (i
= 0; i
< ARRAY_SIZE(clks
); i
++) {
149 ret
= clk_request(dev
, &clk
);
153 rate
= clk_get_rate(&clk
);
154 printf("%s: %lu\n", clks
[i
].name
, rate
);
163 clock
, 2, 1, do_clock
,
164 "display information about clocks",