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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-rockchip/rk3399-board-spl.c
2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <debug_uart.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/periph.h>
21 #include <asm/arch/sdram.h>
22 #include <asm/arch/timer.h>
23 #include <dm/pinctrl.h>
27 #include <power/regulator.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL)
32 static int spl_node_to_boot_device(int node
)
34 struct udevice
*parent
;
37 * This should eventually move into the SPL code, once SPL becomes
38 * aware of the block-device layer. Until then (and to avoid unneeded
39 * delays in getting this feature out, it lives at the board-level).
41 if (!uclass_get_device_by_of_offset(UCLASS_MMC
, node
, &parent
)) {
43 struct blk_desc
*desc
= NULL
;
45 for (device_find_first_child(parent
, &dev
);
47 device_find_next_child(&dev
)) {
48 if (device_get_uclass_id(dev
) == UCLASS_BLK
) {
49 desc
= dev_get_uclass_platdata(dev
);
57 switch (desc
->devnum
) {
59 return BOOT_DEVICE_MMC1
;
61 return BOOT_DEVICE_MMC2
;
68 * SPL doesn't differentiate SPI flashes, so we keep the detection
69 * brief and inaccurate... hopefully, the common SPL layer can be
70 * extended with awareness of the BLK layer (and matching OF_CONTROL)
73 if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH
, node
, &parent
))
74 return BOOT_DEVICE_SPI
;
79 void board_boot_order(u32
*spl_boot_list
)
81 const void *blob
= gd
->fdt_blob
;
82 int chosen_node
= fdt_path_offset(blob
, "/chosen");
89 if (chosen_node
< 0) {
90 debug("%s: /chosen not found, using spl_boot_device()\n",
92 spl_boot_list
[0] = spl_boot_device();
97 (conf
= fdt_stringlist_get(blob
, chosen_node
,
98 "u-boot,spl-boot-order", elem
, NULL
));
100 /* First check if the list element is an alias */
101 const char *alias
= fdt_get_alias(blob
, conf
);
105 /* Try to resolve the config item (or alias) as a path */
106 node
= fdt_path_offset(blob
, conf
);
108 debug("%s: could not find %s in FDT", __func__
, conf
);
112 /* Try to map this back onto SPL boot devices */
113 boot_device
= spl_node_to_boot_device(node
);
114 if (boot_device
< 0) {
115 debug("%s: could not map node @%x to a boot-device\n",
120 spl_boot_list
[idx
++] = boot_device
;
123 /* If we had no matches, fall back to spl_boot_device */
125 spl_boot_list
[0] = spl_boot_device();
129 u32
spl_boot_device(void)
131 return BOOT_DEVICE_MMC1
;
134 u32
spl_boot_mode(const u32 boot_device
)
136 return MMCSD_MODE_RAW
;
139 #define TIMER_CHN10_BASE 0xff8680a0
140 #define TIMER_END_COUNT_L 0x00
141 #define TIMER_END_COUNT_H 0x04
142 #define TIMER_INIT_COUNT_L 0x10
143 #define TIMER_INIT_COUNT_H 0x14
144 #define TIMER_CONTROL_REG 0x1c
147 #define TIMER_FMODE (0 << 1)
148 #define TIMER_RMODE (1 << 1)
150 void secure_timer_init(void)
152 writel(0xffffffff, TIMER_CHN10_BASE
+ TIMER_END_COUNT_L
);
153 writel(0xffffffff, TIMER_CHN10_BASE
+ TIMER_END_COUNT_H
);
154 writel(0, TIMER_CHN10_BASE
+ TIMER_INIT_COUNT_L
);
155 writel(0, TIMER_CHN10_BASE
+ TIMER_INIT_COUNT_H
);
156 writel(TIMER_EN
| TIMER_FMODE
, TIMER_CHN10_BASE
+ TIMER_CONTROL_REG
);
159 void board_debug_uart_init(void)
161 #include <asm/arch/grf_rk3399.h>
162 #define GRF_BASE 0xff770000
163 struct rk3399_grf_regs
* const grf
= (void *)GRF_BASE
;
165 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
166 /* Enable early UART0 on the RK3399 */
167 rk_clrsetreg(&grf
->gpio2c_iomux
,
168 GRF_GPIO2C0_SEL_MASK
,
169 GRF_UART0BT_SIN
<< GRF_GPIO2C0_SEL_SHIFT
);
170 rk_clrsetreg(&grf
->gpio2c_iomux
,
171 GRF_GPIO2C1_SEL_MASK
,
172 GRF_UART0BT_SOUT
<< GRF_GPIO2C1_SEL_SHIFT
);
174 /* Enable early UART2 channel C on the RK3399 */
175 rk_clrsetreg(&grf
->gpio4c_iomux
,
176 GRF_GPIO4C3_SEL_MASK
,
177 GRF_UART2DGBC_SIN
<< GRF_GPIO4C3_SEL_SHIFT
);
178 rk_clrsetreg(&grf
->gpio4c_iomux
,
179 GRF_GPIO4C4_SEL_MASK
,
180 GRF_UART2DBGC_SOUT
<< GRF_GPIO4C4_SEL_SHIFT
);
181 /* Set channel C as UART2 input */
182 rk_clrsetreg(&grf
->soc_con7
,
183 GRF_UART_DBG_SEL_MASK
,
184 GRF_UART_DBG_SEL_C
<< GRF_UART_DBG_SEL_SHIFT
);
188 #define GRF_EMMCCORE_CON11 0xff77f02c
189 #define SGRF_DDR_RGN_CON16 0xff330040
190 #define SGRF_SLV_SECURE_CON4 0xff33e3d0
191 void board_init_f(ulong dummy
)
193 struct udevice
*pinctrl
;
200 * Debug UART can be used from here if required:
205 * printascii("string");
208 printascii("U-Boot SPL board init");
211 /* Emmc clock generator: disable the clock multipilier */
212 rk_clrreg(GRF_EMMCCORE_CON11
, 0x0ff);
214 ret
= spl_early_init();
216 debug("spl_early_init() failed: %d\n", ret
);
221 * Disable DDR and SRAM security regions.
223 * As we are entered from the BootROM, the region from
224 * 0x0 through 0xfffff (i.e. the first MB of memory) will
225 * be protected. This will cause issues with the DW_MMC
226 * driver, which tries to DMA from/to the stack (likely)
227 * located in this range.
229 rk_clrsetreg(SGRF_DDR_RGN_CON16
, 0x1FF, 0);
230 rk_clrreg(SGRF_SLV_SECURE_CON4
, 0x2000);
234 ret
= uclass_get_device(UCLASS_PINCTRL
, 0, &pinctrl
);
236 debug("Pinctrl init failed: %d\n", ret
);
240 ret
= uclass_get_device(UCLASS_RAM
, 0, &dev
);
242 debug("DRAM init failed: %d\n", ret
);
247 void spl_board_init(void)
249 struct udevice
*pinctrl
;
252 ret
= uclass_get_device(UCLASS_PINCTRL
, 0, &pinctrl
);
254 debug("%s: Cannot find pinctrl device\n", __func__
);
258 /* Enable debug UART */
259 ret
= pinctrl_request_noflags(pinctrl
, PERIPH_ID_UART_DBG
);
261 debug("%s: Failed to set up console UART\n", __func__
);
265 preloader_console_init();
266 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
272 printf("spl_board_init: Error %d\n", ret
);
274 /* No way to report error here */
278 #ifdef CONFIG_SPL_LOAD_FIT
279 int board_fit_config_name_match(const char *name
)
281 /* Just empty function now - can't decide what to choose */
282 debug("%s: %s\n", __func__
, name
);