]> git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-rockchip/rk3399-board-spl.c
Merge git://git.denx.de/u-boot-mmc
[people/ms/u-boot.git] / arch / arm / mach-rockchip / rk3399-board-spl.c
1 /*
2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <asm/arch/bootrom.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/grf_rk3399.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/periph.h>
14 #include <asm/io.h>
15 #include <debug_uart.h>
16 #include <dm.h>
17 #include <dm/pinctrl.h>
18 #include <ram.h>
19 #include <spl.h>
20 #include <syscon.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 void board_return_to_bootrom(void)
25 {
26 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
27 }
28
29 static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
30 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
31 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
32 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
33 };
34
35 const char *board_spl_was_booted_from(void)
36 {
37 u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
38 const char *bootdevice_ofpath = NULL;
39
40 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
41 bootdevice_ofpath = boot_devices[bootdevice_brom_id];
42
43 if (bootdevice_ofpath)
44 debug("%s: brom_bootdevice_id %x maps to '%s'\n",
45 __func__, bootdevice_brom_id, bootdevice_ofpath);
46 else
47 debug("%s: failed to resolve brom_bootdevice_id %x\n",
48 __func__, bootdevice_brom_id);
49
50 return bootdevice_ofpath;
51 }
52
53 u32 spl_boot_device(void)
54 {
55 u32 boot_device = BOOT_DEVICE_MMC1;
56
57 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
58 return BOOT_DEVICE_BOOTROM;
59
60 return boot_device;
61 }
62
63 #define TIMER_CHN10_BASE 0xff8680a0
64 #define TIMER_END_COUNT_L 0x00
65 #define TIMER_END_COUNT_H 0x04
66 #define TIMER_INIT_COUNT_L 0x10
67 #define TIMER_INIT_COUNT_H 0x14
68 #define TIMER_CONTROL_REG 0x1c
69
70 #define TIMER_EN 0x1
71 #define TIMER_FMODE (0 << 1)
72 #define TIMER_RMODE (1 << 1)
73
74 void secure_timer_init(void)
75 {
76 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
77 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
78 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
79 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
80 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
81 }
82
83 void board_debug_uart_init(void)
84 {
85 #define GRF_BASE 0xff770000
86 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
87
88 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
89 /* Enable early UART0 on the RK3399 */
90 rk_clrsetreg(&grf->gpio2c_iomux,
91 GRF_GPIO2C0_SEL_MASK,
92 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
93 rk_clrsetreg(&grf->gpio2c_iomux,
94 GRF_GPIO2C1_SEL_MASK,
95 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
96 #else
97 /* Enable early UART2 channel C on the RK3399 */
98 rk_clrsetreg(&grf->gpio4c_iomux,
99 GRF_GPIO4C3_SEL_MASK,
100 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
101 rk_clrsetreg(&grf->gpio4c_iomux,
102 GRF_GPIO4C4_SEL_MASK,
103 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
104 /* Set channel C as UART2 input */
105 rk_clrsetreg(&grf->soc_con7,
106 GRF_UART_DBG_SEL_MASK,
107 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
108 #endif
109 }
110
111 void board_init_f(ulong dummy)
112 {
113 struct udevice *pinctrl;
114 struct udevice *dev;
115 struct rk3399_pmusgrf_regs *sgrf;
116 struct rk3399_grf_regs *grf;
117 int ret;
118
119 #define EARLY_UART
120 #ifdef EARLY_UART
121 /*
122 * Debug UART can be used from here if required:
123 *
124 * debug_uart_init();
125 * printch('a');
126 * printhex8(0x1234);
127 * printascii("string");
128 */
129 debug_uart_init();
130 printascii("U-Boot SPL board init");
131 #endif
132
133 ret = spl_early_init();
134 if (ret) {
135 debug("spl_early_init() failed: %d\n", ret);
136 hang();
137 }
138
139 /*
140 * Disable DDR and SRAM security regions.
141 *
142 * As we are entered from the BootROM, the region from
143 * 0x0 through 0xfffff (i.e. the first MB of memory) will
144 * be protected. This will cause issues with the DW_MMC
145 * driver, which tries to DMA from/to the stack (likely)
146 * located in this range.
147 */
148 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
149 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
150 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
151
152 /* eMMC clock generator: disable the clock multipilier */
153 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
154 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
155
156 secure_timer_init();
157
158 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
159 if (ret) {
160 debug("Pinctrl init failed: %d\n", ret);
161 return;
162 }
163
164 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
165 if (ret) {
166 debug("DRAM init failed: %d\n", ret);
167 return;
168 }
169 }
170
171 #ifdef CONFIG_SPL_LOAD_FIT
172 int board_fit_config_name_match(const char *name)
173 {
174 /* Just empty function now - can't decide what to choose */
175 debug("%s: %s\n", __func__, name);
176
177 return 0;
178 }
179 #endif