arch/arm/mach-socfpga/qts-filter.sh

   1 #!/bin/sh
   2
   3 #
   4 # Process iocsr_config_*.[ch]
   5 # $1:   SoC type
   6 # $2:   Input directory
   7 # $3:   Output directory
   8 #
   9 process_iocsr_config() {
  10         soc="$1"
  11         in_dir="$2"
  12         out_dir="$3"
  13
  14         (
  15         cat << EOF
  16 /*
  17  * Altera SoCFPGA IOCSR configuration
  18  *
  19  * SPDX-License-Identifier:     BSD-3-Clause
  20  */
  21
  22 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
  23 #define __SOCFPGA_IOCSR_CONFIG_H__
  24
  25 EOF
  26
  27         # Retrieve the scan chain lengths
  28         grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'                 \
  29                 ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
  30
  31         echo ""
  32
  33         # Retrieve the scan chain config and zap the ad-hoc length encoding
  34         sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'      \
  35                 ${in_dir}/generated/iocsr_config_${soc}.c
  36
  37         cat << EOF
  38
  39 #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
  40 EOF
  41         ) > "${out_dir}/iocsr_config.h"
  42 }
  43
  44 #
  45 # Process pinmux_config_*.c (and ignore pinmux_config.h)
  46 # $1:   SoC type
  47 # $2:   Input directory
  48 # $3:   Output directory
  49 #
  50 process_pinmux_config() {
  51         soc="$1"
  52         in_dir="$2"
  53         out_dir="$3"
  54
  55         (
  56         cat << EOF
  57 /*
  58  * Altera SoCFPGA PinMux configuration
  59  *
  60  * SPDX-License-Identifier:     BSD-3-Clause
  61  */
  62
  63 #ifndef __SOCFPGA_PINMUX_CONFIG_H__
  64 #define __SOCFPGA_PINMUX_CONFIG_H__
  65
  66 EOF
  67
  68         # Retrieve the pinmux config and zap the ad-hoc length encoding
  69         sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \
  70                 ${in_dir}/generated/pinmux_config_${soc}.c
  71
  72         cat << EOF
  73
  74 #endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
  75 EOF
  76         ) > "${out_dir}/pinmux_config.h"
  77 }
  78
  79 #
  80 # Process pll_config.h
  81 # $1:   SoC type (not used)
  82 # $2:   Input directory
  83 # $3:   Output directory
  84 #
  85 process_pll_config() {
  86         soc="$1"
  87         in_dir="$2"
  88         out_dir="$3"
  89
  90         (
  91         cat << EOF
  92 /*
  93  * Altera SoCFPGA Clock and PLL configuration
  94  *
  95  * SPDX-License-Identifier:     BSD-3-Clause
  96  */
  97
  98 #ifndef __SOCFPGA_PLL_CONFIG_H__
  99 #define __SOCFPGA_PLL_CONFIG_H__
 100
 101 EOF
 102
 103         # Retrieve the pll config and zap parenthesis
 104         sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
 105                 ${in_dir}/generated/pll_config.h
 106
 107         cat << EOF
 108
 109 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
 110 EOF
 111         ) > "${out_dir}/pll_config.h"
 112 }
 113
 114 #
 115 # Filter out only the macros which are actually used by the code
 116 #
 117 grep_sdram_config() {
 118         egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]"
 119 }
 120
 121 #
 122 # Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
 123 # $1:   SoC type (not used)
 124 # $2:   Input directory
 125 # $3:   Output directory
 126 #
 127 process_sdram_config() {
 128         soc="$1"
 129         in_dir="$2"
 130         out_dir="$3"
 131
 132         (
 133         cat << EOF
 134 /*
 135  * Altera SoCFPGA SDRAM configuration
 136  *
 137  * SPDX-License-Identifier:     BSD-3-Clause
 138  */
 139
 140 #ifndef __SOCFPGA_SDRAM_CONFIG_H__
 141 #define __SOCFPGA_SDRAM_CONFIG_H__
 142
 143 EOF
 144
 145         echo "/* SDRAM configuration */"
 146         # Retrieve the sdram config, zap broken lines and zap parenthesis
 147         sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h |
 148         sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
 149                 sort -u | grep_sdram_config
 150
 151         echo ""
 152         echo "/* Sequencer auto configuration */"
 153         sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"            \
 154                 ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config
 155
 156         echo ""
 157         echo "/* Sequencer defines configuration */"
 158         sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"       \
 159                 ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config
 160
 161         echo ""
 162         echo "/* Sequencer ac_rom_init configuration */"
 163         sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
 164                 ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
 165
 166         echo ""
 167         echo "/* Sequencer inst_rom_init configuration */"
 168         sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
 169                 ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
 170
 171         cat << EOF
 172
 173 #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
 174 EOF
 175         ) > "${out_dir}/sdram_config.h"
 176 }
 177
 178 usage() {
 179         echo "$0 [soc_type] [input_dir] [output_dir]"
 180         echo "Process QTS-generated headers into U-Boot compatible ones."
 181         echo ""
 182         echo "  soc_type\t\tType of SoC, either 'cyclone5' or 'arria5',"
 183         echo "  input_dir\t\tDirectory with the QTS project."
 184         echo "  output_dir\t\tDirectory to store the U-Boot compatible headers."
 185         echo ""
 186 }
 187
 188 soc="$1"
 189 in_dir="$2"
 190 out_dir="$3"
 191
 192 if [ "$#" -ne 3 ] ; then
 193         usage
 194         exit 1
 195 fi
 196
 197 if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then
 198         usage
 199         exit 3
 200 fi
 201
 202 process_iocsr_config  "${soc}" "${in_dir}" "${out_dir}"
 203 process_pinmux_config "${soc}" "${in_dir}" "${out_dir}"
 204 process_pll_config    "${soc}" "${in_dir}" "${out_dir}"
 205 process_sdram_config  "${soc}" "${in_dir}" "${out_dir}"