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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-socfpga/spl.c
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/u-boot.h>
11 #include <asm/utils.h>
13 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/freeze_controller.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/scu.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/sections.h>
25 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26 #include <asm/arch/pinmux.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
32 static struct pl310_regs
*const pl310
=
33 (struct pl310_regs
*)CONFIG_SYS_PL310_BASE
;
34 static struct scu_registers
*scu_regs
=
35 (struct scu_registers
*)SOCFPGA_MPUSCU_ADDRESS
;
36 static struct nic301_registers
*nic301_regs
=
37 (struct nic301_registers
*)SOCFPGA_L3REGS_ADDRESS
;
40 static const struct socfpga_system_manager
*sysmgr_regs
=
41 (struct socfpga_system_manager
*)SOCFPGA_SYSMGR_ADDRESS
;
43 u32
spl_boot_device(void)
45 const u32 bsel
= readl(&sysmgr_regs
->bootinfo
);
47 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel
)) {
48 case 0x1: /* FPGA (HPS2FPGA Bridge) */
49 return BOOT_DEVICE_RAM
;
50 case 0x2: /* NAND Flash (1.8V) */
51 case 0x3: /* NAND Flash (3.0V) */
52 socfpga_per_reset(SOCFPGA_RESET(NAND
), 0);
53 return BOOT_DEVICE_NAND
;
54 case 0x4: /* SD/MMC External Transceiver (1.8V) */
55 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
56 socfpga_per_reset(SOCFPGA_RESET(SDMMC
), 0);
57 socfpga_per_reset(SOCFPGA_RESET(DMA
), 0);
58 return BOOT_DEVICE_MMC1
;
59 case 0x6: /* QSPI Flash (1.8V) */
60 case 0x7: /* QSPI Flash (3.0V) */
61 socfpga_per_reset(SOCFPGA_RESET(QSPI
), 0);
62 return BOOT_DEVICE_SPI
;
64 printf("Invalid boot device (bsel=%08x)!\n", bsel
);
69 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
70 static void socfpga_nic301_slave_ns(void)
72 writel(0x1, &nic301_regs
->lwhps2fpgaregs
);
73 writel(0x1, &nic301_regs
->hps2fpgaregs
);
74 writel(0x1, &nic301_regs
->acp
);
75 writel(0x1, &nic301_regs
->rom
);
76 writel(0x1, &nic301_regs
->ocram
);
77 writel(0x1, &nic301_regs
->sdrdata
);
80 void board_init_f(ulong dummy
)
82 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
83 const struct cm_config
*cm_default_cfg
= cm_get_default_config();
85 unsigned long sdram_size
;
89 * First C code to run. Clear fake OCRAM ECC first as SBE
90 * and DBE might triggered during power on
92 reg
= readl(&sysmgr_regs
->eccgrp_ocram
);
93 if (reg
& SYSMGR_ECC_OCRAM_SERR
)
94 writel(SYSMGR_ECC_OCRAM_SERR
| SYSMGR_ECC_OCRAM_EN
,
95 &sysmgr_regs
->eccgrp_ocram
);
96 if (reg
& SYSMGR_ECC_OCRAM_DERR
)
97 writel(SYSMGR_ECC_OCRAM_DERR
| SYSMGR_ECC_OCRAM_EN
,
98 &sysmgr_regs
->eccgrp_ocram
);
100 memset(__bss_start
, 0, __bss_end
- __bss_start
);
102 socfpga_nic301_slave_ns();
104 /* Configure ARM MPU SNSAC register. */
105 setbits_le32(&scu_regs
->sacr
, 0xfff);
107 /* Remap SDRAM to 0x0 */
108 writel(0x1, &nic301_regs
->remap
); /* remap.mpuzero */
109 writel(0x1, &pl310
->pl310_addr_filter_start
);
111 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
112 debug("Freezing all I/O banks\n");
113 /* freeze all IO banks */
114 sys_mgr_frzctrl_freeze_req();
116 /* Put everything into reset but L4WD0. */
117 socfpga_per_reset_all();
118 /* Put FPGA bridges into reset too. */
119 socfpga_bridges_reset(1);
121 socfpga_per_reset(SOCFPGA_RESET(SDR
), 0);
122 socfpga_per_reset(SOCFPGA_RESET(UART0
), 0);
123 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0
), 0);
127 debug("Reconfigure Clock Manager\n");
128 /* reconfigure the PLLs */
129 if (cm_basic_init(cm_default_cfg
))
132 /* Enable bootrom to configure IOs. */
133 sysmgr_config_warmrstcfgio(1);
135 /* configure the IOCSR / IO buffer settings */
136 if (scan_mgr_configure_iocsr())
139 sysmgr_config_warmrstcfgio(0);
141 /* configure the pin muxing through system manager */
142 sysmgr_config_warmrstcfgio(1);
143 sysmgr_pinmux_init();
144 sysmgr_config_warmrstcfgio(0);
146 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
148 /* De-assert reset for peripherals and bridges based on handoff */
149 reset_deassert_peripherals_handoff();
150 socfpga_bridges_reset(0);
152 debug("Unfreezing/Thaw all I/O banks\n");
153 /* unfreeze / thaw all IO banks */
154 sys_mgr_frzctrl_thaw_req();
156 /* enable console uart printing */
157 preloader_console_init();
159 if (sdram_mmr_init_full(0xffffffff) != 0) {
160 puts("SDRAM init failed.\n");
164 debug("SDRAM: Calibrating PHY\n");
165 /* SDRAM calibration */
166 if (sdram_calibration_full() == 0) {
167 puts("SDRAM calibration failed.\n");
171 sdram_size
= sdram_calculate_size();
172 debug("SDRAM: %ld MiB\n", sdram_size
>> 20);
174 /* Sanity check ensure correct SDRAM size specified */
175 if (get_ram_size(0, sdram_size
) != sdram_size
) {
176 puts("SDRAM size check failed!\n");
180 socfpga_bridges_reset(1);
182 /* Configure simple malloc base pointer into RAM. */
183 gd
->malloc_base
= CONFIG_SYS_TEXT_BASE
+ (1024 * 1024);
185 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
186 void spl_board_init(void)
188 /* configuring the clock based on handoff */
189 cm_basic_init(gd
->fdt_blob
);
192 config_dedicated_pins(gd
->fdt_blob
);
195 /* Release UART from reset */
196 socfpga_reset_uart(0);
198 /* enable console uart printing */
199 preloader_console_init();
202 void board_init_f(ulong dummy
)
205 * Configure Clock Manager to use intosc clock instead external osc to
206 * ensure success watchdog operation. We do it as early as possible.
210 socfpga_watchdog_disable();
214 #ifdef CONFIG_HW_WATCHDOG
215 /* release osc1 watchdog timer 0 from reset */
216 socfpga_reset_deassert_osc1wd0();
218 /* reconfigure and enable the watchdog */
221 #endif /* CONFIG_HW_WATCHDOG */